CN116344559A

CN116344559A - Photoelectric sensor, forming method thereof and electronic equipment

Info

Publication number: CN116344559A
Application number: CN202111581746.2A
Authority: CN
Inventors: 任惠; 阎大勇; 王志高
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2023-06-27

Abstract

A photoelectric sensor, a forming method thereof, and an electronic device, the photoelectric sensor includes: the connecting structure is positioned in the medium layer of the preset pixel unit area and is respectively contacted with the interconnection layer and the pixel substrate below the orthographic projection of the photosensitive area; a metal grid positioned on the isolation structure and in contact with the conductive layer; the first opening is positioned in the pixel substrate of the lead area and exposes the dielectric layer; a second opening in the dielectric layer at the bottom of the first opening and exposing the interconnect layer; a pad layer located in the first opening and the second opening and contacting the interconnection layer; the height of the welding pad layer in the first opening is lower than that of the first opening; the passivation layer is positioned on the first surface of the photosensitive area and covers the metal grid, and the passivation layer is positioned on the side wall and the bottom surface of the first opening of the lead area and the welding pad layer and exposes the top surface of the welding pad layer. The embodiment of the invention is beneficial to improving the interface state of the side wall of the isolation structure, reducing dark current, improving the consistency of the height of the bonding pad layer of the photoelectric sensor and optimizing the performance of the photoelectric sensor.

Description

Photoelectric sensor, forming method thereof and electronic equipment

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a photoelectric sensor, a forming method thereof and electronic equipment.

Background

A photosensor is a device that converts an optical signal into an electrical signal. The working principle is based on the photoelectric effect, which means that when light irradiates on certain substances, electrons of the substances absorb photon energy and corresponding electric effect phenomenon occurs.

For example, CCD (Charge Coupled Device ) image sensors and CMOS image sensors, which are widely used in digital cameras and other electronic optical devices, convert an optical image into an electrical signal by using a photoelectric conversion function and output the digital image. ToF (Time of Flight) distance sensor, for example: DTOF (Direct Time of Flight ) sensor, records the time at which the light pulse is emitted and detected, converting the time difference into distance information. The technique can be used in various ranging scenarios such as autopilot, sweeping robot, VR (Virtual Reality)/AR (Augmented Reality) modeling, etc.

However, the performance of the current photoelectric sensor still needs to be improved.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a photoelectric sensor, a forming method thereof and electronic equipment, and optimizes the performance of the photoelectric sensor.

To solve the above problems, an embodiment of the present invention provides a photoelectric sensor, including: the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area surrounding the photosensitive area, and the photosensitive area comprises pixel unit areas which are arranged in an array; one of the pixel unit areas is used as a preset pixel unit area; the isolation structure penetrates through the pixel substrate between the adjacent pixel unit areas and comprises a conductive layer, and the top surface of the conductive layer is exposed out of the first surface; the dielectric layer is positioned on the second surface of the pixel substrate; the interconnection layer is positioned in the dielectric layer below the orthographic projection of the photosensitive area and the lead area in the pixel substrate; the connecting structure is positioned in the medium layer of the preset pixel unit area and is respectively contacted with the interconnection layer below the orthographic projection of the photosensitive area and the pixel substrate; a metal mesh on the isolation structure and in contact with the conductive layer; a first opening located in the pixel substrate of the lead region and exposing the top surface of the dielectric layer; a second opening in the dielectric layer at the bottom of the first opening and exposing the top surface of the interconnect layer; a pad layer located in the first and second openings and contacting the interconnection layer of the lead region; the height of the welding pad layer in the first opening is lower than that of the first opening; and the passivation layer is positioned on the first surface of the photosensitive region in the pixel substrate and covers the metal grid, is positioned on the side wall and the bottom surface of the first opening of the lead region and the welding pad layer, and exposes the top surface of the welding pad layer.

Correspondingly, the embodiment of the invention also provides a method for forming the photoelectric sensor, which comprises the following steps: providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area surrounding the photosensitive area, the photosensitive area comprises pixel unit areas which are arranged in an array, one pixel unit area is used as a preset pixel unit area, an isolation structure penetrating through the pixel substrate is formed between the pixel unit areas, the isolation structure comprises a conductive layer, and the top surface of the conductive layer is exposed out of the first surface; a dielectric layer is formed on the second surface, and an interconnection layer is formed in the dielectric layer; a connecting structure is further formed in the dielectric layer of the preset pixel unit area, and the connecting structure is respectively contacted with the interconnection layer and the pixel substrate below the orthographic projection of the photosensitive area; forming a metal grid on the isolation structure and in contact with the conductive layer; forming a first passivation layer on the first surface, wherein the first passivation layer covers the metal grid; forming an opening penetrating through a dielectric layer, a pixel substrate and a first passivation layer above an interconnection layer of the lead region, wherein the opening comprises a first opening in the pixel substrate and the first passivation layer of the lead region and a second opening in the dielectric layer at the bottom of the first opening, and the second opening exposes the interconnection layer; and forming a welding pad layer in the opening, wherein the welding pad layer is contacted with the interconnection layer of the lead area.

Correspondingly, the embodiment of the invention also provides electronic equipment, which comprises: the embodiment of the invention provides a photoelectric sensor.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the photoelectric sensor provided by the embodiment of the invention, the connecting structure is positioned in the dielectric layer of the preset pixel unit area and is respectively contacted with the interconnection layer below the orthographic projection of the photosensitive area and the pixel substrate, accordingly, a negative potential is easily applied to the welding pad layer by electrically connecting the metal grid with the pixel substrate of the preset pixel unit area when the photoelectric sensor works, so that the conductive layer is connected with the negative potential, thereby being beneficial to adsorbing positive charges on the side wall of the isolation structure, improving the interface state of the side wall of the isolation structure and reducing the dark current of the pixel unit; in addition, the embodiment of the invention can enable the conductive layer of the isolation structure to be connected with the negative potential by applying the negative potential to the bonding pad layer, so that the bonding pad layer used for being electrically connected with the metal grid is not required to be additionally arranged on the passivation layer on the first surface, the height consistency of the bonding pad layer of the photoelectric sensor is correspondingly ensured, and the complexity of package testing is further reduced.

In an alternative scheme, the thickness of the passivation layer on the first surface of the photosensitive region is larger than the thickness of the first opening of the lead region, because in the formation process of the photoelectric sensor, after the metal grid is formed, the first passivation layer covering the metal grid is formed on the first surface, then the first opening and the second opening are formed, after the pad layer is formed in the first opening and the second opening, the second passivation layer exposing the pad layer is formed on the first passivation layer and the bottom and the side wall of the first opening, and the second passivation layer and the first passivation layer form the passivation layer.

In the method for forming the photoelectric sensor provided by the embodiment of the invention, the metal grid which is positioned on the isolation structure and is in contact with the conducting layer is formed, and the dielectric layer, the pixel substrate and the opening of the first passivation layer which penetrate through the upper part of the interconnection layer of the lead area are formed, and the welding pad layer which is in contact with the interconnection layer is formed in the opening; in addition, the embodiment of the invention can enable the conductive layer of the isolation structure to be connected with negative potential by applying the negative potential to the bonding pad layer, so that the bonding pad layer for being electrically connected with the metal grid is not required to be additionally formed on the first passivation layer on the first surface, the high consistency of the bonding pad layer of the photoelectric sensor is correspondingly ensured, and the complexity of the subsequent packaging process and testing is further reduced; in addition, compared with the method of forming the opening, filling the opening, the passivation layer on the first surface and the pad layer on the bottom of the opening, the method of forming the metal grid and then forming the first passivation layer and the pad layer does not need to etch the passivation layer on the top of the isolation structure or etch the passivation layer material on the first surface on the side of the opening, accordingly, light covers are saved, and the method is beneficial to simplifying the process flow.

Drawings

Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a photoelectric sensor;

FIGS. 7 to 8 are schematic structural views of an embodiment of a photosensor according to the present invention;

fig. 9 to 21 are schematic structural views corresponding to each step in an embodiment of a method for forming a photoelectric sensor according to the present invention.

Detailed Description

As known from the background art, the performance of the current photoelectric sensor needs to be improved. The reason why the performance of a photoelectric sensor is to be improved is now analyzed in conjunction with a method of forming a photoelectric sensor.

Fig. 1 to 6 are schematic structural views corresponding to each step in a method for forming a photoelectric sensor.

Referring to fig. 1, a pixel substrate is provided, including a first surface 11 and a second surface 12 opposite to each other, the pixel substrate includes a photosensitive region 10P and a lead region 10N surrounding the photosensitive region 10P, the photosensitive region 10P includes pixel unit regions (not labeled) arranged in an array, an isolation structure 13 is formed in the pixel substrate 10 between the pixel unit regions, and a top surface of the isolation structure 13 is exposed from the first surface 11; a dielectric layer 14 is formed on the second surface 12, and an interconnection layer 15 is formed in the dielectric layer 14 of the lead area 10N; a logic substrate is also bonded to the dielectric layer 14 of the second surface 12.

Referring to fig. 2, an opening 16 is formed through the pixel substrate 10 of the lead region 10N and the dielectric layer 14 over the interconnect layer 15, the opening 16 exposing a portion of the top of the interconnect layer 15 toward the first surface 11.

Referring to fig. 3, a pad layer 17 contacting the interconnect layer 15 is formed at the bottom of the opening 16.

Referring to fig. 4, a passivation layer 18 is formed filling the opening 16 and being located on the first surface 11, the passivation layer 18 covering the pad layer 17 and the top surface of the isolation structure 13.

Referring to fig. 5, a metal mesh 19 is formed on the passivation layer 18 on top of the isolation structure 13.

Referring to fig. 6, after forming the metal mesh 19, an interconnection trench 20 penetrating the passivation layer 18 above the pad layer 17 is formed, exposing the pad layer 17.

In the above-mentioned method for forming a photoelectric sensor, the step of forming an isolation structure generally includes: forming an isolation trench in the pixel substrate between adjacent pixel unit areas; an isolation structure is formed within the isolation trench. The isolation trench is usually formed by an etching process, the isolation structure is formed in the isolation trench by a filling process, after the etching process and the filling process are performed, interface states are usually generated on the side wall of the isolation structure, the surface of the interface states can absorb negative charge electron layers in an inverted mode, and dark current of the pixel unit can be increased due to the existence of the interface states.

In order to prevent dark current caused by interface states, P-type ion implantation is typically performed on the pixel substrate before bonding of the pixel substrate to the logic substrate is achieved. By carrying out P-type ion implantation, the negative charge electron layer in the interface state can be neutralized to a certain extent, the problem of dark current caused by the interface state is correspondingly improved,

however, in the field of photosensors, the absorption thickness and optical path length of light are generally increased by increasing the thickness of the pixel substrate, thereby increasing photon detection efficiency and thus photon detection sensitivity.

With the gradual increase of the thickness of the pixel substrate, when the thickness of the pixel substrate is greater than the maximum depth of ion implantation, the side wall of the isolation structure cannot be completely surrounded by P-type ions, and when the photoelectric sensor works, the side wall of the isolation structure which is not surrounded by the P-type ions can increase the dark current of the pixel.

In addition, when the first surface is the back surface of the pixel substrate, the front-stage device is already manufactured due to the fact that ion implantation is performed, and in order to prevent adverse effects on the electrical performance of the front-stage device, even if ion implantation can be performed, the implanted ions cannot be subjected to a high-temperature activation process, and the ion implantation cannot perform a corresponding function.

In order to solve the technical problem, in the photoelectric sensor provided by the embodiment of the invention, the connecting structure is positioned in the dielectric layer of the preset pixel unit area and is respectively contacted with the interconnection layer below the orthographic projection of the photosensitive area and the pixel substrate, accordingly, a negative potential is easily applied to the welding pad layer in a mode of electrically connecting the metal grid with the pixel substrate of the preset pixel unit area, so that the conductive layer is connected with the negative potential, the adsorption of positive charges on the side wall of the isolation structure is facilitated, the improvement of the interface state of the side wall of the isolation structure is facilitated, and the dark current of the pixel unit is reduced; in addition, the embodiment of the invention can enable the conductive layer of the isolation structure to be connected with the negative potential by applying the negative potential to the bonding pad layer, so that the bonding pad layer used for being electrically connected with the metal grid is not required to be additionally arranged on the passivation layer on the first surface, the height consistency of the bonding pad layer of the photoelectric sensor is correspondingly ensured, and the complexity of package testing is further reduced.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 7 and 8, fig. 7 is a cross-sectional view, and fig. 8 is a top view corresponding to fig. 7, showing a schematic structural diagram of an embodiment of a photoelectric sensor according to the present invention.

As an example, the present embodiment is described with a photoelectric sensor as a TOF (Time of Flight) sensor as an example. More specifically, the photosensor may be a DTOF (Direct Time of Flight ) sensor. In other embodiments, the photosensor may also be an iTOF (indirect Time of Flight ) sensor.

In other embodiments, the photosensor may also be a CCD (Charge Coupled Device ) image sensor, a CMOS image sensor, or other type of photosensor.

As shown in fig. 7 and 8, in the present embodiment, the photoelectric sensor includes: the pixel substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, the pixel substrate 100 includes a photosensitive region 100P and a lead region 100N surrounding the photosensitive region 100P, the photosensitive region 100P includes pixel unit regions (not labeled) arranged in an array, wherein one of the pixel unit regions is used as a preset pixel unit region 100px; the isolation structure penetrates through the pixel substrate 100 between the adjacent pixel unit areas, the isolation structure comprises a conductive layer 110, and the top surface of the conductive layer 110 is exposed out of the first surface 101; a dielectric layer 120 on the second surface 102 of the pixel substrate 100; an interconnect layer within the dielectric layer 120 under the orthographic projection of the photosensitive region 100P and the lead region 100N in the pixel substrate 100; the connection structure 115 is located in the dielectric layer 120 of the preset pixel unit area 100px and is respectively contacted with the interconnection layer 111 and the pixel substrate 100 below the orthographic projection of the photosensitive area 100P; a metal mesh 210 on the isolation structure and in contact with the conductive layer 110; a first opening 141 (refer to fig. 17) located in the pixel substrate 100 of the lead region 100N and exposing the top surface of the dielectric layer 120; a second opening 142 (see fig. 17 in combination) located in the dielectric layer 120 at the bottom of the first opening 141 and exposing the top surface of the interconnect layer; a pad layer 150 located in the first and

second openings

141 and 142 and contacting the interconnection layer of the lead region 100N, the pad layer 150 being located in the first opening 141 at a height lower than that of the first opening 141; and a passivation layer on the first surface 101 of the photosensitive region 100P in the pixel substrate 100 and covering the metal grid 210, the passivation layer being on the sidewalls and bottom surfaces of the first opening 141 of the lead region 100N and the pad layer and exposing the top surface of the pad layer.

The pixel substrate 100 is used to provide an operational platform for the formation of photosensors.

In this embodiment, the pixel base 100 includes a substrate (not shown). In particular, the material of the substrate may include one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. As one example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

In this embodiment, the first surface 101 is a back surface of the pixel substrate 100, and the second surface 102 is a front surface of the pixel substrate 100. Specifically, the pixel substrate 100 is a backside illuminated (Backside Illumination, BSI) pixel wafer, and the first surface 101 of the pixel substrate 100 is a light-receiving surface.

The pixel substrate 100 includes a photosensitive region 100P, and the photosensitive region 100P is configured to receive an optical signal and convert the optical signal into an electrical signal. In this embodiment, the photosensitive area 100P includes an array of pixel unit areas, in which pixel units (not shown) are formed, and the pixel units are configured to receive optical signals so as to convert the optical signals into electrical signals.

The pixel substrate 100 of the predetermined pixel unit area 100px is used for connecting with the connection structure 115 and the ground line 220.

The lead region 100N is used for wiring and forming leads to make electrical connection between the pixel cell or other device structure and external circuitry.

The isolation structure is used to reduce optical and electrical crosstalk between adjacent pixel cells. The isolation structure penetrates through the pixel substrates 100 of the adjacent pixel unit areas, so that electrical isolation between the pixel substrates 100 of the adjacent pixel unit areas is realized, and when the pixel substrates 100 are electrified through the pad layer 150, the second interconnection layer 112, the first interconnection layer 111 and the connection structure 115, electric leakage can be prevented from occurring in the pixel substrates 100 of the adjacent pixel unit areas.

In this embodiment, the isolation structure is a deep trench isolation (Deep Trench Isolation, DTI) structure.

In this embodiment, the isolation structure includes the conductive layer 110, so that when the photoelectric sensor works, a voltage is applied to the conductive layer 110, positive charges can be adsorbed on the side wall of the isolation structure, which is beneficial to improving the interface state of the side wall of the isolation structure and reducing the dark current of the pixel unit.

The end of the conductive layer 110 is exposed on the first surface 101, so that the metal grid 210 can be located on the first surface 101 and contact with the conductive layer 110, and the electrical property of the conductive layer 110 is led out through the metal grid 210.

In this embodiment, the material of the conductive layer 110 is a metal material. The metal material has good conductivity, is usually an opaque material, and can also play a role in isolating light between adjacent pixel units.

In this embodiment, the material of the conductive layer 110 includes one or more of tungsten, aluminum, titanium nitride, tantalum nitride, and copper. As an embodiment, the material of the conductive layer 110 is tungsten, which is not easy to diffuse and has superior hole filling capability, so that the filling effect of the conductive layer 110 in the deep trench is improved, and the tungsten is a light-tight metal material, which can play a role in light isolation, and is beneficial to making the reduction effect of the isolation structure on the optical crosstalk between adjacent pixel units more remarkable.

In this embodiment, the isolation structure further includes: the insulating layer 105 is located between the conductive layer 110 and the pixel substrate 100, and between the conductive layer 105 and the dielectric layer 120, and the insulating layer 105 is also located on the first surface 101 at the side of the conductive layer 110.

The insulating layer 105 serves to insulate between the conductive layer 110 and the pixel substrate 100. The insulating layer 105 is also positioned on the first surface 101 at the side of the conductive layer 110, thereby protecting the first surface 101 of the pixel substrate 100.

In this embodiment, the material of the insulating layer 105 includes any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

In this embodiment, the insulating layer 105 includes a negatively charged dielectric layer (not shown), which has a more comprehensive negative charge than the conventional dielectric layer, and the negative charge can increase hole accumulation at the interface of the negatively charged dielectric layer, and can correspondingly collect holes at the bottom and the side wall of the isolation structure, so as to form a P-type protection structure, which is beneficial to improving the leakage problem of the side wall of the isolation structure.

More specifically, the material of the negatively charged dielectric layer comprises a high-k dielectric material. As an example, the high-k dielectric material includes any one or more of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.

Dielectric layer 120 is used to achieve isolation between interconnect layers. The material of the dielectric layer 120 is a dielectric material, for example: one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, and ultra-low-k dielectric material.

The interconnect layer is used to make electrical connection between the pixel cells and also between the pixel cells and an external circuit or other interconnect structure. In particular, the interconnect layer includes one or more layers of interconnect lines.

In this embodiment, the interconnect layers include a first interconnect layer 111 located in the dielectric layer 100P of the photosensitive region 100P, and a second interconnect layer 112 located in the dielectric layer 120 of the lead region 100N, the second interconnect layer 112 being electrically connected to the first interconnect layer 111. The first and second interconnection layers 111 and 112 serve to make electrical connection between the pixel unit and the pad layer 150 to make electrical connection between the pixel unit and an external circuit.

The materials of the first interconnect layer 111 and the second interconnect layer 112 are metals, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

In this embodiment, the connection structure 115 is in contact with the first interconnection layer 111 and in contact with the pixel substrate 100 of the preset pixel unit area 100px, thereby achieving electrical connection between the pixel substrate 100 of the preset pixel unit area 100px and the first interconnection layer 111.

In this embodiment, the interconnection layer further includes: a third interconnect layer 113 in the dielectric layer 120 of the photosensitive region 100P and the wiring region 100N, the third interconnect layer 113 being located on a side of the first interconnect layer 111 away from the second surface 102 and on a side of the second interconnect layer 112 away from the second surface; and a first conductive plug 121 between the first interconnect layer 111 and the third interconnect layer 113, and a second conductive plug 122 between the second interconnect layer 112 and the third interconnect layer 113, the first conductive plug 121 for making an electrical connection between the first interconnect layer 111 and the third interconnect layer 113, the second conductive plug 122 for making an electrical connection between the second interconnect layer 112 and the third interconnect layer 113.

The electrical connection between the first interconnect layer 111 and the second interconnect layer 112 is achieved by the third interconnect layer 113, and the first conductive plug 121 and the second conductive plug 122.

The materials of the third interconnection layer 113, and the first and second

conductive plugs

121 and 122 are metals, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

The connection structure 115 is located in the dielectric layer 120 under the pixel substrate 100 of the preset pixel unit area 100px and is respectively in contact with the first interconnection layer 111 and the pixel substrate 100, so as to realize electrical connection between the first interconnection layer 111 and the pixel substrate 100 of the preset pixel unit area 100 px.

In this embodiment, the connection structure 115 is formed in a back-end-of-line process. In this embodiment, the material of the connection structure 115 is the same as that of the first conductive plug 121 and the second conductive plug 122, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

In this embodiment, the photoelectric sensor further includes: the logic substrate 200 or the memory chip or the sensor chip is bonded to the dielectric layer 120 of the second surface 102 of the pixel substrate 100.

In this embodiment, the logic substrate 200 is bonded to the dielectric layer 120 on the second surface 102 of the pixel substrate 100.

The Logic substrate 200 serves as a Logic Wafer (Logic Wafer) for analyzing the electrical signals provided by the pixel substrate 100. Specifically, a logic device for analyzing and processing the electrical signal supplied from the pixel substrate 100 is formed in the logic substrate 200.

By disposing the pixel region (i.e., the photosensitive region 100P) and the logic region on different substrates, and bonding the pixel substrate 100 and the logic substrate 200 together, the pixel area is advantageously increased, the path of light reaching the photoelectric element is also advantageously shortened, the scattering of light is reduced, the light is more focused, the photosensitive capability of the photoelectric sensor in a weak light environment is further improved, and system noise and crosstalk are reduced.

As an embodiment, the bonding between the logic substrate 200 and the dielectric layer 120 of the second surface 102 of the pixel substrate 100 is achieved by Hybrid bonding (Hybrid bonding).

The metal mesh 210 corresponds to the position and shape of the isolation structure, and the area surrounded by the metal mesh 210 corresponds to each pixel cell area, thereby preventing optical crosstalk between adjacent pixel cells.

Specifically, the metal mesh 210 is a mesh-like structure, and the metal mesh 210 is located on the first surface 101 of the pixel substrate 100, that is, the metal mesh 210 is located on the back surface of the pixel substrate 100, and the metal mesh 210 is a back metal mesh.

In this embodiment, the metal mesh 210 is in contact with a portion of the top surface of the conductive layer 110, or the metal mesh 210 is in contact with the top surface of all of the conductive layer 110. Wherein, since the conductive layers 110 in the respective isolation structures are connected, even if the metal mesh 210 is in contact with only a portion of the top surface of the conductive layer 110, electrical connection between the entire conductive layer 110 and an external circuit can be achieved through the metal mesh 210.

In this embodiment, the material of the metal mesh 210 is a metal material, and the material of the metal mesh 210 includes one or both of aluminum and tungsten. As an example, the material of the metal mesh 210 is aluminum. Aluminum is a material which is easy to etch, so that a patterning process for forming the metal grid 210 is convenient to carry out, the aluminum is good in conductivity, the electric connection performance of the metal grid 210 is improved, and in addition, aluminum is an opaque material, so that the effect of reducing optical crosstalk between adjacent pixel units by the metal grid 210 is guaranteed.

In this embodiment, the photoelectric sensor further includes: and a ground line 220 disposed on the first surface 101 and contacting the pixel substrate 100 of the predetermined pixel unit area 100px, wherein the ground line is connected to the metal grid 210 at 220. Accordingly, in this embodiment, the passivation layer is located on the first surface 101 and covers the metal grid 210 and the ground line 220.

The ground line 220 is used to electrically connect the metal mesh 210 with the pixel substrate 100 of the predetermined pixel unit area 100 px. In addition, during the formation of the metal mesh 210, more charges are generally generated, and the ground line 230 contacts the pixel substrate 100 to release charges through the pixel substrate 100 during the formation of the metal mesh 210, thereby preventing the charges from accumulating on the first surface 101 of the pixel substrate 100 and thus preventing arcing (arcing) during the formation of the metal mesh 210.

In this embodiment, the material of the grounding wire 220 is a metal material. As an example, the material of the ground line 220 includes one or both of aluminum and tungsten.

In this embodiment, the material of the grounding wire 220 is the same as that of the metal mesh 210.

More specifically, in the present embodiment, the ground wire 220 and the metal mesh 210 are formed in the same step, and the ground wire 220 and the metal mesh 210 are in an integrated structure, so that not only is the process flow simplified, but also the electrical connection performance between the ground wire 220 and the metal mesh 210 is improved.

In this embodiment, the ground line 220 penetrates the insulating layer 105 of the predetermined pixel unit area 100 px. As an embodiment, the ground line 220 further penetrates the pixel substrate 100 with a partial thickness of the predetermined pixel unit area 100 px.

Referring to fig. 8 in combination, as an embodiment, the ground line 220 is a ring structure surrounding a plurality of pixel unit areas, so that the area of the ground line 220 is increased, and the resistance of the ground line 220 is correspondingly reduced. The shape of the ground line 220 is not limited thereto. In other embodiments, the shape of the ground wire may also be other shapes, such as: the ground wire may have a strip-like structure.

The first and

second openings

141 and 142 serve to provide a spatial location for forming the pad layer 150, and the second opening 142 exposes the interconnect layer so that the pad layer 150 can contact the interconnect layer, thereby achieving an electrical connection between the pad layer 150 and the interconnect layer.

Specifically, the second opening 142 exposes a portion of the top of the second interconnect layer 112 facing the first surface 101, so that the pad layer 150 is electrically connected to the second interconnect layer 112.

In this embodiment, the first opening 141 and the second opening 142 are in communication to form the opening 140.

In this embodiment, the pad layer 150 is used to access a negative potential.

The bond pad layer 150 is in contact with the interconnect layer for making electrical connection between the interconnect layer and an external circuit or other interconnect structure.

More specifically, the pad layer 150 contacts the second interconnect layer 112, the second interconnect layer 112 is connected to the first interconnect layer 111, the first interconnect layer 111 is electrically connected to the pixel substrate 100 through the connection structure 115, the pixel substrate 100 is electrically connected to the conductive layer 110 sequentially through the ground line 220 and the metal grid 210, and accordingly, when the photoelectric sensor operates, the conductive layer 110 of the isolation structure can be connected to the negative potential by applying the negative potential to the pad layer 150 through the pad layer 150, the second interconnect layer 112, the first interconnect layer 111, the connection structure 115, the pixel substrate 100 and the ground line sequentially connected to each other, so that positive charges are adsorbed on the side wall of the isolation structure, interface states of the side wall of the isolation structure are improved, and dark current of the pixel unit is reduced.

In addition, in this embodiment, by applying a negative potential to the pad layer 150, the conductive layer 110 of the isolation structure is connected to the negative potential, so that the pad layer electrically connected to the metal grid does not need to be additionally formed on the first surface, and accordingly, the height consistency of the pad layer 150 of the photoelectric sensor is ensured, and further, the complexity of the subsequent packaging process and testing is reduced.

The material of pad layer 150 is a conductive material. In this embodiment, the material of the pad layer 150 includes one or more of aluminum, titanium, gold, and tin-doped indium oxide. As an example, the material of the pad layer 150 is aluminum. Aluminum has good conductivity, and aluminum is a material that is easily etched, so that the first pad layer 150 is easily formed in a patterned manner.

The pad layer 150 is located in the opening 140, and the top surface of the pad layer 150 is lower than the first surface 101.

The passivation layer 160 serves to protect the metal mesh 210 and the ground line 220 from the external environment.

In this embodiment, the material of the passivation layer 160 is an insulating material, and the material of the passivation layer 160 includes one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an embodiment, the passivation layer 160 is made of silicon oxide.

In this embodiment, the thickness of the passivation layer 160 on the first surface 101 of the photosensitive region 100P is greater than that of the passivation layer 160 at the position of the first opening 141 of the lead region 100N, because, in the formation process of the photoelectric sensor, after the metal grid 210 is formed, the first passivation layer 160 covering the metal grid 210 is formed on the first surface 101, then the first opening 141 and the second opening 142 are formed, and after the pad layer 150 is formed in the first opening 141 and the second opening 142, the second passivation layer 155 exposing the pad layer 150 is formed on the first passivation layer 160 and on the bottom and the side wall of the first opening 142, and the second passivation layer 155 and the first passivation layer 160 form a passivation layer.

Specifically, in this embodiment, the passivation layer includes: a first passivation layer 160 on the first surface 101 at the side of the opening 140 and covering the metal mesh 210 and the ground line 220; a second passivation layer 155 conformally covering sidewalls and bottom surfaces of the first opening 141, the pad layer 150, and the first passivation layer 160, the second passivation layer 155 exposing the pad layer 150.

More specifically, the first passivation layer 160 is located on the insulating layer 105 of the first surface 101 and covers the metal grid 210 and the ground line 220.

In this embodiment, the first passivation layer 160 is located on the first surface 101 at the side of the opening 140 and covers the metal grid 210 and the ground line 220, and the first passivation layer 160 is formed after the metal grid 210 and the ground line 220 are formed and before the opening 140 and the pad layer 150 are formed in the formation process of the photoelectric sensor, and the first passivation layer 160 is formed on the first surface 101 instead of being filled in the opening, and accordingly, the first passivation layer 160 is formed on a relatively flat surface, so that the consistency of the height of the top surface of the first passivation layer 160 is better, and etching of the passivation layer material of the first surface at the side of the opening is not required in the formation process of the first passivation layer 160, thereby being beneficial to saving a photomask, reducing the complexity of the process for forming the first passivation layer 160, and simplifying the process flow.

The second passivation layer 155 serves to protect the solder pad layer 150. The second passivation layer 155 exposes the pad layer 150 so as to enable electrical connection between the pad layer 150 and an external circuit, for example: and the packaging and testing processes are facilitated.

In this embodiment, the material of the second passivation layer 155 is silicon oxide. In other embodiments, the material of the second passivation layer may also be silicon nitride or silicon oxynitride.

Specifically, the second passivation layer 155 conformally covers the sidewalls and bottom surface of the first opening 141, the pad layer 150, and the first passivation layer 160.

In this embodiment, since the passivation layer 160 is formed after the metal grid 210 and the ground line 220 are formed during the formation of the photoelectric sensor, and then the opening 140 and the second passivation layer 155 are formed, accordingly, the second passivation layer 155 does not need to fill the opening 140 during the formation of the second passivation layer 155, and the second passivation layer 155 conformally covers the side walls and the bottom surface of the opening 140, the pad layer 150 and the passivation layer 160, so that the second passivation layer 155 can be thinner, which is beneficial to simplifying the process complexity of forming the second passivation layer 155.

As an example, the passivation layer on the sidewall and bottom surfaces of the first opening 141 and the pad layer 150 has a thickness of 10nm to 10000nm, that is, the second passivation layer 155 has a thickness of 10nm to 10000nm, so that the thickness of the second passivation layer 155 is reduced while securing the protection of the pad layer 150 by the second passivation layer 155, thereby simplifying the process complexity and saving materials.

In this embodiment, the passivation layer further includes: isolation layer 145 is located between the first passivation layer 160 and the second passivation layer 155, between the pixel substrate 100 and the second passivation layer 155, and between the dielectric layer 120 and the second passivation layer 155 on the first passivation layer 160 at the side of the opening 140, on the sidewall of the first opening 141, and on the top surface of the dielectric layer 120 at the bottom of the first opening 141.

The isolation layer 145 is used for protecting the pixel substrate 100 and also for isolating the pixel substrate 100 from the pad layer 150. In this embodiment, the material of the isolation layer 145 is silicon oxide.

In order to solve the problems, the invention also provides a method for forming the photoelectric sensor. Fig. 9 to 21 are schematic structural views corresponding to each step in an embodiment of a method for forming a photoelectric sensor according to the present invention.

The method of forming the photoelectric sensor of the present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 9, a pixel substrate 100 is provided, including a first surface 101 and a second surface 102 opposite to each other, the pixel substrate 100 includes a photosensitive region 100P and a lead region 100N surrounding the photosensitive region 100P, the photosensitive region 100P includes pixel unit regions (not labeled) arranged in an array, one of the pixel unit regions is used as a preset pixel unit region 100px, an isolation structure penetrating through the pixel substrate 100 is formed between the pixel unit regions, the isolation structure includes a conductive layer 110, and a top surface of the conductive layer 110 is exposed on the first surface 101; a dielectric layer 120 is formed on the second surface 102, and an interconnect layer is formed in the dielectric layer 120; a connection structure 115 is further formed in the dielectric layer 120 of the preset pixel unit area 100px, and the connection structure 115 is respectively contacted with the interconnection layer and the pixel substrate 100 under the orthographic projection of the photosensitive area 100P.

The pixel substrate 100 is used to provide an operation platform for subsequent processing. In this embodiment, the pixel base 100 includes a substrate (not shown). Specifically, the material of the substrate includes one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. As an example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

The pixel substrate 100 of the preset pixel unit area 100px is used for connecting with the connection structure 115 and the subsequent ground line.

The isolation structure is used to reduce optical and electrical crosstalk between adjacent pixel cells. The isolation structure penetrates through the pixel substrate 100 to realize electrical isolation between the pixel substrates 100 of the adjacent pixel unit areas, so that when the pixel substrate 100 is electrified through the pad layer, the second interconnection layer 112, the first interconnection layer 111 and the connection structure 115, electric leakage can be prevented from occurring in the pixel substrate 100 of the adjacent pixel unit areas.

In this embodiment, the isolation structure includes the conductive layer 110, so that a voltage is applied to the conductive layer 110 subsequently, thereby adsorbing positive charges on the sidewall of the isolation structure, thereby being beneficial to improving the interface state of the sidewall of the isolation structure and reducing dark current of the pixel unit.

The end of the conductive layer 110 is exposed on the first surface 101, so that a metal grid contacting with the conductive layer 110 can be formed on the first surface 101 later, and the electrical property of the conductive layer 110 can be led out through the metal grid.

In this embodiment, an insulating layer 105 is further formed between the conductive layer 110 and the pixel substrate 100, and between the conductive layer 110 and the dielectric layer 120.

The insulating layer 105 serves to insulate between the conductive layer 110 and the pixel substrate 100, and the conductive layer 110 and the insulating layer 105 on the bottom and side walls of the conductive layer 110 also serve to constitute an isolation structure.

In this embodiment, the insulating layer 105 is further formed on the first surface 101 at the side of the conductive layer 110, thereby protecting the first surface 101 of the pixel substrate 100.

In this embodiment, the interconnect layers include a first interconnect layer 111 located within the dielectric layer 100P of the photosensitive region, and a second interconnect layer 112 located in the dielectric layer 120 of the lead region 100N, the second interconnect layer 112 being electrically connected to the first interconnect layer 111. The first interconnect layer 111 and the second interconnect layer 112 are used to make electrical connection between the pixel unit and the subsequent pad layer, thereby making electrical connection between the pixel unit and an external circuit.

It should be noted that, in this embodiment, the interconnection layer further includes: a third interconnect layer 113 in the dielectric layer 120 of the photosensitive region 100P and the wiring region 100N, the third interconnect layer 113 being located on a side of the first interconnect layer 111 away from the second surface 102 and on a side of the second interconnect layer 112 away from the second surface; and a first conductive plug 121 between the first interconnect layer 111 and the third interconnect layer 113, and a second conductive plug 122 between the second interconnect layer 112 and the third interconnect layer 113, the first conductive plug 121 for making an electrical connection between the first interconnect layer 111 and the third interconnect layer 113, the second conductive plug 122 for making an electrical connection between the second interconnect layer 112 and the third interconnect layer 113.

The materials of the third interconnection layer 113, and the first and second

conductive plugs

In this embodiment, the connection structure 115 is formed in a back-end-of-line process, thereby providing process compatibility. Specifically, in the present embodiment, the connection structure 115 is formed during the process of forming the interconnection layer and the conductive plugs, and the material of the connection structure 115 is the same as that of the first conductive plug 121 and the second conductive plug 122, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

In this embodiment, the logic substrate 200 or the memory chip or the sensor chip is further bonded on the dielectric layer 120 of the second surface 102 of the pixel substrate 100.

In this embodiment, the logic substrate 200 is bonded on the dielectric layer 120 of the second surface 102 of the pixel substrate 100 as an example. The Logic substrate 200 serves as a Logic Wafer (Logic Wafer) for analyzing the electrical signals provided by the pixel substrate 100. Specifically, a logic device for analyzing and processing the electrical signal supplied from the pixel substrate 100 is formed in the logic substrate 200.

As one example, the step of providing the pixel substrate 100 to which the logic substrate is bonded includes: providing a pixel substrate 100; providing a logic substrate 200; bonding between the dielectric layer 120 of the second side 102 of the pixel substrate 100 and the logic substrate 200 is achieved; after bonding is achieved, thinning processing is performed on the first surface 101 of the pixel substrate 100; after the thinning process is performed, an isolation structure penetrating the pixel substrate 100 is formed in the pixel substrate 100 between adjacent pixel unit regions.

In this embodiment, the step of forming the isolation structure includes: forming an isolation trench (not shown) in the pixel substrate 100 between adjacent pixel cell regions, the bottom of the isolation trench exposing the dielectric layer 120; an insulating layer 105 is formed on the sidewalls and bottom of the isolation trench, and a conductive layer 110 is formed on the insulating layer 105 and fills the isolation trench.

In this embodiment, the process of forming the isolation trench includes: an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, has higher process controllability and etching precision, is easy to realize an isolation trench with higher depth-to-width ratio, is favorable for enabling the isolation trench to have higher dimensional precision and profile controllability under the condition that the isolation trench penetrates through the pixel substrate 100, and is easy to realize higher etching selection ratio, so that the bottom of the isolation trench is easy to stop on the dielectric layer 120, and the probability of damaging the dielectric layer 120 is reduced.

In this embodiment, the step of forming the isolation structure in the isolation trench includes: forming an insulating layer 105 on the sidewalls and bottom of the isolation trench, the insulating layer 105 also being formed on the first surface 101; filling the isolation trench formed with the insulating layer 105 with a conductive material layer (not shown), the conductive material layer also being formed on the insulating layer of the first surface 101; the layer of conductive material located on the first surface 101 is removed and the remaining layer of conductive material filled in the isolation trenches is used as the conductive layer 110 and the insulating layer 105 and the conductive layer 110 located in the isolation trenches are used to form the isolation structure.

In this embodiment, the process of forming the insulating layer 105 includes: one or more of oxidation, chemical vapor deposition, and atomic layer deposition. Wherein the oxidation process may comprise a decoupled plasma oxidation process.

In this embodiment, the process of filling the conductive material layer in the isolation trench includes one or more of a chemical vapor deposition process, a physical vapor deposition process, and an electrochemical plating process.

In this embodiment, a planarization process is used to remove the conductive material layer on the first surface 101. In particular, the planarization process may include a chemical mechanical planarization process.

The insulating layer 105 on the first surface 101 is remained in the process of removing the conductive material layer on the first surface 101, so that the insulating layer 105 can protect the first surface 101, so as to avoid damage to the surface of the pixel substrate 100 caused by the process of removing the conductive material layer on the first surface 101.

Referring to fig. 10 to 13, a metal mesh 210 is formed on the isolation structure and in contact with the conductive layer 110.

By forming the metal grid 210 in contact with the conductive layer 110, the pad layer 150, the interconnection layer, the connection structure 115, the pixel substrate 100 and the metal grid 210 are electrically connected with the conductive layer 110 in a manner of electrically connecting the metal grid 210 with the pixel substrate 100 of the preset pixel unit area 100px, and the conductive layer 110 of the isolation structure is connected with a negative potential by applying the negative potential to the pad layer 150, so that positive charges are adsorbed on the side wall of the isolation structure, the interface state of the side wall of the isolation structure is improved, and dark current of the pixel unit is reduced.

In addition, compared with the mode of improving the interface state of the side wall of the isolation structure by carrying out P-type ion doping on the pixel substrate, the embodiment is also beneficial to avoiding being limited by the ion doping depth, and the absorption thickness and the optical path of light are increased by increasing the thickness of the pixel substrate 100 correspondingly, so that the photon detection efficiency of a photosensitive area is improved, and the photon detection sensitivity performance of the photoelectric sensor is improved.

In addition, before forming the passivation layer and the pad layer, the metal grid 210 is formed, and compared with the method of forming the opening, filling the opening and the passivation layer on the first surface, and the pad layer on the bottom of the opening, the passivation layer on the top of the isolation structure and the passivation layer material on the first surface on the side of the opening do not need to be etched, so that a photomask is correspondingly saved, and the process flow is simplified.

In summary, this embodiment optimizes the performance of the photosensor.

The metal mesh 210 is in contact with the conductive layer 110, and is used for electrically connecting the conductive layer 110 with the pixel substrate 100 of the preset pixel unit area 100 px.

In this embodiment, the forming method further includes: in the step of forming the metal mesh 210, a ground line 220 contacting the pixel substrate 100 of the predetermined pixel unit area 100px is formed, and the ground line 220 is electrically connected to the metal mesh 210.

The ground line 220 is used to electrically connect the metal mesh 210 with the pixel substrate 100 of the predetermined pixel unit area 100 px.

Specifically, by forming the metal grid 210 in contact with the conductive layer 110 and the ground line 220 in contact with the pixel substrate 100 of the preset pixel unit area 100px, the ground line 220 is electrically connected with the metal grid 10, and accordingly, when the photoelectric sensor works, the conductive layer 110 of the isolation structure can be connected to the negative potential by applying the negative potential to the pad layer 150 through the pad layer 150, the second interconnect layer 112, the first interconnect layer 111, the connection structure 115, the pixel substrate 100 and the ground line 220 which are sequentially connected, thereby facilitating the adsorption of positive charges on the side wall of the isolation structure, further facilitating the improvement of the interface state of the side wall of the isolation structure, and reducing the dark current of the pixel unit.

Also, during the formation of the metal mesh 210, more charges are generally generated, and the ground line 230 is in contact with the pixel substrate 100 for discharging charges through the pixel substrate 100 during the formation of the metal mesh 210, preventing charges from accumulating on the first surface 101 of the pixel substrate 100, thereby preventing arcing during the formation of the metal mesh 210.

In this embodiment, the material of the grounding wire 220 is the same as that of the metal mesh 210. More specifically, in the present embodiment, the ground wire 220 and the metal mesh 210 are formed in the same step, and the ground wire 220 and the metal mesh 210 are in an integrated structure, so that not only is the process flow simplified, but also the electrical connection performance between the ground wire 220 and the metal mesh 210 is improved.

Referring to fig. 13 in combination, as an embodiment, the ground line 220 is a ring structure surrounding a plurality of pixel unit areas, so as to increase the area of the ground line 220 and correspondingly reduce the resistance of the ground line 220. The shape of the ground line 220 is not limited thereto. In other embodiments, the shape of the ground wire may also be other shapes, such as: the ground wire may have a strip-like structure.

The specific steps of forming the metal mesh 210 and the ground line 220 according to the present embodiment will be described in detail with reference to the accompanying drawings.

As shown in fig. 10, a ground trench 180 penetrating the insulating layer 105 of the predetermined pixel unit area 100px is formed, and the pixel substrate 100 is exposed by the ground trench 180.

The ground trenches 180 are used to provide a spatial location for forming a ground line. The ground trench 180 exposes the pixel substrate 100 so that the ground line contacts the pixel substrate 100.

In this embodiment, during the process of forming the grounding trench 180, an over-etching process is further performed to prevent the problem that the grounding trench cannot expose the pixel substrate 100 due to the insulation layer 105 located in the preset pixel unit area 100px not being completely removed, so that the grounding trench 180 also penetrates through a part of the thickness of the pixel substrate 100.

In other embodiments, the second trench may also extend through only the insulating layer.

As shown in fig. 11 to 13, a ground line 220 positioned in the ground trench 180 and contacting the pixel substrate 100, and a metal mesh 210 positioned on the isolation structure and contacting the conductive layer 110 are formed.

Specifically, as shown in fig. 11, a metal material layer 190 is formed on the insulating layer 105, the metal material layer 190 covering the conductive layer 110 and filling the ground trench 180; as shown in fig. 12 and 13, fig. 12 is a cross-sectional view, fig. 13 is a top view corresponding to fig. 12, the metal material layer 190 is patterned, the metal material layer 190 on top of the isolation structure is reserved for use as the metal grid 210, the metal material layer 190 in the ground trench 180 is reserved for use as the ground line 220, and the ground line 220 is connected to the metal grid 210.

The metal material layer 190 is used to form a metal mesh and a ground line. In this embodiment, a physical vapor deposition (Physical Vapor Deposition, PVD) process is used to form the metal material layer 190.

The first surface 101 of the pixel substrate 100 is an insulating surface formed by the insulating layer 105, and before the metal material layer 190 is formed, the conductive layer 110 is electrically isolated from the pixel substrate 100, so that a large amount of charges are easily accumulated on the first surface 101 during the process of forming the metal material layer 190 by using a physical vapor deposition process, and the metal material layer 190 is further formed in the grounding trench 180 and contacts with the pixel substrate 100, so that charges are released through the pixel substrate 100, so as to avoid arcing problems caused by charge accumulation on the first surface 101.

In this embodiment, an etching process is used to pattern the metal material layer 190. Specifically, the metal material layer 190 is patterned using an anisotropic dry etching process.

Referring to fig. 14, a first passivation layer 160 is formed on the first surface 101, the first passivation layer 160 covering the metal mesh 210. In this embodiment, the first passivation layer 160 also covers the ground line 220.

The first passivation layer 160 is used to protect the metal mesh 210 and the ground line 220 from the subsequent process.

In this embodiment, after the metal grid 210 and the ground line 220 are formed and before the openings and the pad layers are formed, the first passivation layer 160 is formed on the first surface 101 instead of being filled in the openings, accordingly, the first passivation layer 160 is formed on a relatively flat surface, the top surface of the first passivation layer 160 has better uniformity, and in the process of forming the first passivation layer 160, the passivation layer material on the first surface of the side portion of the openings is not required to be etched, so that the light mask is saved, the complexity of the process for forming the first passivation layer 160 is reduced, and the process flow is simplified.

In this embodiment, the material of the first passivation layer 160 is an insulating material, including one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the material of the first passivation layer 160 is silicon oxide.

In this embodiment, the step of forming the first passivation layer 160 includes: forming a passivation material layer (not shown) on the first surface 101 using a deposition process, the passivation material layer covering the metal grid 210 and the ground line 220; the passivation material layer is planarized, and the passivation material layer which is located on the first surface 101 and covers the metal mesh 210 and the ground line 220 is remained as the first passivation layer 160.

The planarization process is performed on the passivation material layer after the deposition process, so that the flatness and the high uniformity of the top surface of the first passivation layer 160 are improved, so that a flat surface is provided for the subsequent process.

As an embodiment, the deposition process may be a chemical vapor deposition process, which has a strong coverage capability, low process cost and high process compatibility. As an embodiment, the planarization process is performed using a chemical mechanical planarization process.

In other embodiments, the step of forming the passivation layer may further include only: and a passivation layer is formed on the first surface by adopting a deposition process, and covers the metal grid and the grounding wire, so that the process flow is correspondingly simplified.

Referring to fig. 15 to 17, an opening 140 (as shown in fig. 17) is formed through the dielectric layer 120, the pixel substrate 100, and the first passivation layer 160 over the second interconnect layer 112, the opening 140 including a first opening 141 in the pixel substrate 100 and the first passivation layer 160 of the lead region 100N and a second opening 142 in the dielectric layer 120 at the bottom of the first opening 141, the second opening 142 exposing the interconnect layer.

In this embodiment, the second opening 142 exposes the second interconnect layer 112. Specifically, the opening 140 exposes a portion of the top of the second interconnect layer 112 that faces the first surface 101.

The openings 140 are used to provide space for the subsequent formation of the pad layer, and the openings 140 expose the second interconnect layer 112, so that the pad layer formed at the bottom of the openings 140 can contact the second interconnect layer 112, thereby achieving electrical connection between the pad layer and the second interconnect layer 112.

The steps of forming the opening 140 in this embodiment will be described in detail with reference to the accompanying drawings.

As shown in fig. 15, a first opening 141 of the pixel substrate 100 penetrating the lead region 100N is formed, and the first opening 141 exposes the dielectric layer 120.

As an example, the first opening 141 is formed using an anisotropic dry etching process. The anisotropic dry etching process has high etching profile control, and is beneficial to accurately controlling the profile shape of the first opening 141.

In this embodiment, as shown in fig. 16, after forming the first opening 141, the forming method further includes: an isolation layer 145 is formed on sidewalls and bottom of the first opening 141 and the first passivation layer 160.

The isolation layer 145 is used for protecting the pixel substrate 100 and isolating the pixel substrate 100 from subsequent pad layers. In this embodiment, the material of the isolation layer 145 is silicon oxide. In this embodiment, the isolation layer 145 conformally covers the sidewalls and bottom of the first opening 141 and the first passivation layer 160.

As shown in fig. 17, a second opening 142 is formed in the dielectric layer 120 under the first opening 141, the second opening 142 exposing the second interconnect layer 112, the second opening 142 and the first opening 141 constituting the opening 140.

Specifically, the second opening 142 exposes a portion of the top of the second interconnect layer 112 toward the first surface 101. In this embodiment, the second opening 142 also penetrates a portion of the isolation layer 145 above the second interconnect layer 112.

As an example, a second opening 142 penetrating the dielectric layer 120 under the first opening 141 is formed using an anisotropic dry etching process. The anisotropic dry etching process has high etching profile control, is favorable for precisely controlling the profile of the second opening 142, and reduces the probability of causing false etching of the second interconnection layer 112.

Referring to fig. 18, a pad layer 150 is formed in the opening 140, and the pad layer 150 is in contact with the interconnection layer of the lead region 100N. In this embodiment, the pad layer 150 is in contact with the second interconnect layer 112.

In this embodiment, the pad layer 150 is used to access a negative potential.

In this embodiment, the pad layer 150 is in contact with the second interconnect layer 112 for making electrical connection between the second interconnect layer 112 and an external circuit or other interconnect structure.

In this embodiment, the step of forming the pad layer 150 includes: forming a pad material layer (not shown) on the bottom and sidewalls of the opening 140 and the isolation layer 145; a portion of the pad material layer at the first surface 101 and at the bottom of the opening 140 is removed, and the remaining pad material layer at the bottom of the opening 140 and in contact with the second interconnect layer 112 is used as a pad layer 150.

Referring to fig. 19, in this embodiment, the forming method further includes: after forming the pad layer 150, a second passivation layer 155 is formed on the top and side walls of the pad layer 150, the side and bottom walls of the first opening 141, and the first passivation layer 160.

In this embodiment, after the metal grid 210 and the ground line 220 are formed, the first passivation layer 160 and the opening 140 are sequentially formed, and the pad layer 150 contacting the second interconnection layer 112 is formed in the opening 140, accordingly, in the process of forming the second passivation layer 155, the second passivation layer 155 does not need to fill the first opening 141, so that the forming difficulty of the second passivation layer 155 is reduced, and the complexity of the process is simplified.

Specifically, the second passivation layer 155 conformally covers the sidewalls and bottom surface of the first opening 141, the pad layer 150, and the first passivation layer 160. More specifically, the second passivation layer 155 conformally covers the isolation layer 145 and the pad layer 150.

The second passivation layer 155 serves to protect the solder pad layer 150. In this embodiment, the material of the second passivation layer 155 is silicon oxide. In other embodiments, the material of the second passivation layer may also be silicon nitride or silicon oxynitride.

In this embodiment, since the second passivation layer 155 does not need to fill the first opening 141 during the process of forming the second passivation layer 155, and accordingly, the second passivation layer 155 conformally covers the sidewalls and the bottom surface of the first opening 141, the pad layer 150 and the first passivation layer 160, the second passivation layer 155 can be thinner, which is beneficial to simplifying the process complexity of forming the second passivation layer 155. As an example, the thickness of the second passivation layer 155 is 10nm to 10000nm, so that the thickness of the second passivation layer 155 is reduced while ensuring the protection of the second passivation layer 155 against the pad layer 150, to simplify the process complexity and save materials, and to reduce the process difficulty of subsequent etching of the second passivation layer 155 to expose the pad layer 150.

In this embodiment, the second passivation layer 155 is formed using a chemical vapor deposition process. The chemical vapor deposition process has higher covering capability, mature process and high process compatibility. In other embodiments, the second passivation layer may also be formed using an atomic layer deposition process, or an atomic layer deposition process and a chemical vapor deposition process.

Referring to fig. 20 and 21, fig. 20 is a cross-sectional view, fig. 21 is a top view corresponding to fig. 20, a portion of the second passivation layer 155 on the top surface of the pad layer 150 is removed, the pad layer 150 is exposed, and the remaining second passivation layer 155 and the first passivation layer 160 are used to form a passivation layer.

The pad layer 150 is exposed so as to enable electrical connection between the pad layer 150 and an external circuit, for example: and the packaging and testing processes are facilitated.

In this embodiment, the second passivation layer 155 conformally covers the pad layer 150, and compared with the second passivation layer filling the pad layer and filling the opening 140, the thickness of the second passivation layer 155 is thinner, and accordingly, the difficulty of removing a portion of the second passivation layer 155 on the top surface of the pad layer 150 to expose the pad layer 150 is smaller, thereby being beneficial to reducing the process complexity.

In this embodiment, an anisotropic dry etching process is used to remove a portion of the second passivation layer 155 on the top surface of the pad layer 150.

In order to solve the problems, the embodiment of the invention also provides electronic equipment, which comprises the photoelectric sensor provided by the embodiment of the invention.

The electronic device of the embodiment may be any electronic product or device having a photoelectric sensing function, such as a mobile phone, a tablet computer, a notebook computer, a navigator, a camera, a video camera, a sweeping robot, a virtual reality device, an augmented reality device, or any intermediate product including the aforementioned photoelectric sensor.

As can be seen from the foregoing description, the photoelectric sensor provided in the embodiment of the present invention has excellent performance, and by using the photoelectric sensor provided in the embodiment of the present invention, the performance of the electronic device is improved, and the use sensitivity of the user is improved.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A photoelectric sensor, comprising:

The pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area surrounding the photosensitive area, and the photosensitive area comprises pixel unit areas which are arranged in an array; one of the pixel unit areas is used as a preset pixel unit area;

the isolation structure penetrates through the pixel substrate between the adjacent pixel unit areas and comprises a conductive layer, and the top surface of the conductive layer is exposed out of the first surface;

the dielectric layer is positioned on the second surface of the pixel substrate;

the interconnection layer is positioned in the dielectric layer below the orthographic projection of the photosensitive area and the lead area in the pixel substrate;

the connecting structure is positioned in the medium layer of the preset pixel unit area and is respectively contacted with the interconnection layer below the orthographic projection of the photosensitive area and the pixel substrate;

a metal mesh on the isolation structure and in contact with the conductive layer;

a first opening located in the pixel substrate of the lead region and exposing the top surface of the dielectric layer;

a second opening in the dielectric layer at the bottom of the first opening and exposing the top surface of the interconnect layer;

a pad layer located in the first and second openings and contacting the interconnection layer of the lead region; the height of the welding pad layer in the first opening is lower than that of the first opening;

And the passivation layer is positioned on the first surface of the photosensitive region in the pixel substrate and covers the metal grid, is positioned on the side wall and the bottom surface of the first opening of the lead region and the welding pad layer, and exposes the top surface of the welding pad layer.

2. The photosensor according to claim 1, wherein the photosensor further comprises: the grounding wire is positioned on the first surface and is contacted with the pixel substrate of the preset pixel unit area, and the grounding wire is connected with the metal grid;

the passivation layer is positioned on the first surface and covers the metal grid and the grounding wire.

3. The photosensor of claim 1 wherein the pad layer is configured to be connected to a negative potential.

4. The photosensor of claim 1 wherein the passivation layer thickness on the first surface of the photosensitive region is greater than the passivation layer thickness at the location of the first opening of the lead region.

5. The photosensor of claim 2, wherein the ground line is of unitary construction with the metal mesh.

6. The photosensor of claim 1, wherein the metal mesh is in contact with a portion of the top surface of the conductive layer or in contact with all of the top surface of the conductive layer.

7. The photosensor according to claim 1, wherein the photosensor further comprises: and the logic substrate, the memory chip or the sensor chip is bonded on the dielectric layer of the second surface of the pixel substrate.

8. The photosensor of claim 1 or 7, wherein the first surface is a back surface of the pixel substrate and the second surface is a front surface of the pixel substrate.

9. The photosensor of claim 1 or 4, wherein the passivation layer on the sidewalls and bottom of the first opening and the pad layer has a thickness of 10nm to 10000nm.

10. The photosensor of claim 1, wherein the material of the pixel substrate includes one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium arsenide;

the material of the conductive layer comprises one or more of tungsten, aluminum, titanium nitride, tantalum nitride and copper;

the material of the interconnection layer comprises one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride;

the material of the connecting structure comprises one or more of copper, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride;

The material of the welding pad layer comprises one or more of aluminum, titanium, gold and tin-doped indium oxide;

the material of the passivation layer comprises one or more of silicon oxide, silicon oxynitride and silicon nitride;

the material of the metal mesh comprises one or two of aluminum and tungsten.

11. A method of forming a photoelectric sensor, comprising:

providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area surrounding the photosensitive area, the photosensitive area comprises pixel unit areas which are arranged in an array, one pixel unit area is used as a preset pixel unit area, an isolation structure penetrating through the pixel substrate is formed between the pixel unit areas, the isolation structure comprises a conductive layer, and the top surface of the conductive layer is exposed out of the first surface; a dielectric layer is formed on the second surface, and an interconnection layer is formed in the dielectric layer; a connecting structure is further formed in the dielectric layer of the preset pixel unit area, and the connecting structure is respectively contacted with the interconnection layer and the pixel substrate below the orthographic projection of the photosensitive area;

forming a metal grid on the isolation structure and in contact with the conductive layer;

Forming a first passivation layer on the first surface, wherein the first passivation layer covers the metal grid;

forming an opening penetrating through a dielectric layer, a pixel substrate and a first passivation layer above an interconnection layer of the lead region, wherein the opening comprises a first opening in the pixel substrate and the first passivation layer of the lead region and a second opening in the dielectric layer at the bottom of the first opening, and the second opening exposes the interconnection layer;

and forming a welding pad layer in the opening, wherein the welding pad layer is contacted with the interconnection layer of the lead area.

12. The method of claim 11, wherein the pad layer is used to access a negative potential.

13. The method of forming a photosensor of claim 11, further comprising: in the step of forming the metal mesh, a ground line contacting the pixel substrate of the preset pixel unit area is further formed, and the ground line is electrically connected with the metal mesh.

14. The method of forming a photosensor according to claim 13, wherein in the step of providing a pixel substrate, an insulating layer is further formed between the conductive layer and the pixel substrate and between the conductive layer and a dielectric layer, the insulating layer being further formed on the first surface of the conductive layer side portion;

The step of forming the metal mesh and the ground line includes: forming a grounding groove penetrating through the insulating layer of the preset pixel unit area, wherein the grounding groove exposes the pixel substrate;

and forming a grounding wire which is positioned in the grounding groove and is contacted with the pixel substrate, and a metal grid which is positioned on the isolation structure and is contacted with the conductive layer.

15. The method of forming a photosensor of claim 11, where forming the first passivation layer includes: forming a first passivation layer on the first surface by adopting a deposition process, wherein the first passivation layer covers the metal grid and the grounding wire;

or alternatively;

the step of forming the first passivation layer includes: forming a passivation material layer on the first surface by adopting a deposition process, wherein the passivation material layer covers the grounding wire; and carrying out planarization treatment on the passivation material layer, and using the passivation material layer which is positioned on the first surface and covers the metal grid as the first passivation layer.

16. The method of claim 11, wherein in the step of providing a pixel substrate, a logic substrate or a memory chip or a sensor chip is further bonded to the dielectric layer on the second surface of the pixel substrate.

17. The method of claim 11 or 16, wherein the first surface is a back surface of a pixel substrate and the second surface is a front surface of the pixel substrate.

18. The method of forming a photosensor according to claim 11, wherein the method of forming a photosensor further comprises: forming a second passivation layer on the top and side walls of the pad layer, the side and bottom walls of the first opening, and the first passivation layer after forming the pad layer; and removing part of the second passivation layer positioned on the top surface of the bonding pad layer to expose the bonding pad layer, wherein the rest of the second passivation layer and the first passivation layer are used for forming a passivation layer.

19. The method of claim 18, wherein forming the second passivation layer comprises one or both of an atomic layer deposition process and a chemical vapor deposition process.

20. An electronic device, comprising: a photoelectric sensor according to any one of claims 1 to 10.