CN117080228A

CN117080228A - Method for forming photoelectric sensor

Info

Publication number: CN117080228A
Application number: CN202210505387.0A
Authority: CN
Inventors: 阎大勇; 任惠; 王志高; 张大明; 王丙泉
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2022-05-10
Filing date: 2022-05-10
Publication date: 2023-11-17

Abstract

A method for forming a photoelectric sensor includes: providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite, the pixel substrate comprises a photosensitive area and a lead area, the photosensitive area comprises a plurality of pixel unit areas, at least one pixel unit area is used as a preset pixel unit area, an interconnection layer is formed on the second surface, and an isolation groove is formed between the pixel unit areas; forming an insulating layer on the first surface outside the isolation trench, wherein a first opening communicated with the isolation trench and a grounding trench which is positioned in a preset pixel unit area and exposes the pixel substrate are formed in the insulating layer; forming an isolation structure in the isolation trench and the first opening, wherein the isolation structure comprises a conductive layer, and a grounding wire which is contacted with a pixel substrate of a preset pixel unit area is formed in the grounding trench; a metal mesh is formed on the isolation structure in contact with the conductive layer and the ground line. The embodiment of the invention is beneficial to simplifying the process flow and reducing the number of photomasks.

Description

Method for forming photoelectric sensor

Technical Field

The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a photoelectric sensor.

Background

Photoelectric sensors are devices which convert optical signals into electrical signals, and the working principle of the photoelectric sensors is based on the photoelectric effect, wherein the photoelectric effect refers to the phenomenon that electrons of substances absorb photon energy to generate corresponding electric effect when light irradiates on certain substances.

For example, CCD (Charge Coupled Device ) image sensors and CMOS image sensors, which are widely used in digital cameras and other electronic optical devices, convert an optical image into an electrical signal by using a photoelectric conversion function and output the digital image. ToF (Time of Flight) distance sensor, for example: DTOF (Direct Time of Flight ) sensor, records the time at which the light pulse is emitted and detected, converting the time difference into distance information. The technique can be used in various ranging scenarios such as autopilot, sweeping robot, VR (Virtual Reality)/AR (Augmented Reality) modeling, etc.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a method for forming a photoelectric sensor, which is beneficial to simplifying the process flow and reducing the number of photomasks.

In order to solve the above problem, an embodiment of the present invention further provides a method for forming a photoelectric sensor, including: providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite, the pixel substrate comprises a photosensitive area and a lead area, the photosensitive area comprises a plurality of pixel unit areas, at least one pixel unit area is used as a preset pixel unit area, an interconnection layer is formed on the second surface, and an isolation groove is formed between the pixel unit areas; forming an insulating layer on the first surface outside the isolation trench, wherein a first opening communicated with the isolation trench and a grounding trench which is positioned in the preset pixel unit area and exposes the pixel substrate are formed in the insulating layer; forming an isolation structure in the isolation trench and the first opening, wherein the isolation structure comprises a conductive layer, and a grounding wire which is contacted with a pixel substrate of the preset pixel unit area is formed in the grounding trench; forming a metal grid on the isolation structure, wherein the metal grid is in contact with the conductive layer and the grounding wire; and forming a welding pad layer positioned above the interconnection layer, wherein the welding pad layer is connected with the interconnection layer of the lead area.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming the photoelectric sensor provided by the embodiment of the invention, in the same step, the first opening communicated with the isolation groove is formed in the insulating layer, and the grounding groove exposing the pixel substrate is formed in the insulating layer of the preset pixel unit area.

Drawings

Fig. 1 to 9 are schematic structural views corresponding to steps in a method for forming a photoelectric sensor;

fig. 10 to 22 are schematic structural views corresponding to each step in an embodiment of a method for forming a photoelectric sensor according to the present invention;

fig. 23 to 25 are schematic structural views corresponding to steps in another embodiment of a method for forming a photoelectric sensor according to the present invention;

fig. 26 and 27 are schematic structural views corresponding to steps in a further embodiment of a method for forming a photoelectric sensor according to the present invention.

Detailed Description

The current process flow for forming the photoelectric sensor is complex, and the number of required photomasks is large. The reason why the performance of the photoelectric sensor is to be improved is analyzed by combining a forming method of the photoelectric sensor. Fig. 1 to 9 are schematic structural views corresponding to each step in a method for forming a photoelectric sensor.

Referring to fig. 1, a pixel substrate 800 is provided, including a first surface 801 and a second surface 802 opposite to each other, where the pixel substrate 800 includes a photosensitive region 800P and a lead region 800N surrounding the photosensitive region 800P, the photosensitive region 800P includes pixel unit regions arranged in an array, at least one pixel unit region is used as a preset pixel unit region 800px, a dielectric layer 820 is formed on the second surface 802, an interconnection layer 845 is formed in the dielectric layer 820, an isolation trench 870 penetrating the pixel substrate 800 is formed between the pixel unit regions, and a light trapping trench 850 is also formed in the first surface 801 of the pixel unit region.

Referring to fig. 2, a first insulating layer 821 is formed on the first surface 801, the first insulating layer 821 covering the light trapping groove 850 and the first surface 801 and sealing the top of the isolation trench 870.

Referring to fig. 3, the first insulating layer 821 on top of the isolation trench 870 is removed.

Referring to fig. 4, an isolation structure 871 is formed within the isolation trench 870, the isolation structure 871 top being flush with the first insulating layer 821 top, the isolation structure 871 comprising a conductive layer.

Referring to fig. 5, a second insulating layer 872 is formed on the isolation structure 871 and the insulating layer 821.

Referring to fig. 6, the first and second insulating layers 821 and 872 located at the preset pixel unit area 800px are removed, and a ground groove 843 exposing the bottom of the pixel substrate 800 is formed in the first and second insulating layers 821 and 872 of the preset pixel unit area 800 px.

Referring to fig. 7, the second insulating layer 872 on top of the isolation structure 871 is removed, and an opening 844 exposing the isolation structure 871 is formed in the second insulating layer 872.

Referring to fig. 8, a ground line 851 contacting the pixel substrate 800 of the preset pixel unit area 800px is formed in the ground groove 843, and a metal mesh 852 contacting the conductive layer is formed in the opening 844, and the metal mesh 852 is electrically connected to the ground line 851.

Referring to fig. 9, after the metal mesh 852 is formed, a pad layer 854 is formed in the pixel substrate 800 and the dielectric layer 820 above the interconnect layer 845 in the lead region 800N, and the pad layer 854 is connected to the interconnect layer 845 of the lead region 800N.

Removing the first insulation layer 821 and the second insulation layer 872 located in the preset pixel unit area 800px, and forming a grounding groove 843 exposing the pixel substrate 800 in the first insulation layer 821 and the second insulation layer 872 of the preset pixel unit area 800 px; the first insulating layer 821 and the second insulating layer 872 on top of the isolation structure 871 are removed, and an opening 844 exposing the isolation structure 871 is formed in the second insulating layer 872, and therefore, the opening 844 and the ground groove 843 are formed in different steps, respectively, resulting in a complicated process flow for forming the photoelectric sensor and an increased number of masks.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a photoelectric sensor, including:

providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite, the pixel substrate comprises a photosensitive area and a lead area, the photosensitive area comprises a plurality of pixel unit areas, one pixel unit area is used as a preset pixel unit area, an interconnection layer is formed on the second surface, and an isolation groove is formed between the pixel unit areas; forming an insulating layer on the first surface outside the isolation trench, wherein a first opening communicated with the isolation trench and a grounding trench which is positioned in the preset pixel unit area and exposes the pixel substrate are formed in the insulating layer; forming an isolation structure in the isolation trench and the first opening, wherein the isolation structure comprises a conductive layer, and a grounding wire which is contacted with a pixel substrate of the preset pixel unit area is formed in the grounding trench; forming a metal grid on the isolation structure, wherein the metal grid is in contact with the conductive layer and the grounding wire; and forming a welding pad layer positioned above the interconnection layer, wherein the welding pad layer is connected with the interconnection layer of the lead area.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 10 to 22, schematic structural diagrams corresponding to the steps in an embodiment of a method for forming a photoelectric sensor according to the present invention are shown.

Referring to fig. 10, a pixel substrate 100 is provided, including a first surface 101 and a second surface 102 opposite to each other, the pixel substrate 100 includes a photosensitive region 100P and a lead region 100N, the photosensitive region 100N includes a plurality of pixel unit regions (not shown), at least one of the pixel unit regions is used as a predetermined pixel unit region 100px, an interconnection layer is formed on the second surface 102, and an isolation trench 143 is formed between the pixel unit regions.

The pixel substrate 100 is used to provide an operational platform for the formation of photosensors.

In this embodiment, the pixel base 100 includes a substrate (not shown). In particular, the material of the substrate may include one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. As one example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.

In this embodiment, the first surface 101 is a back surface of the pixel substrate 100, and the second surface 102 is a front surface of the pixel substrate 100. Specifically, the pixel substrate 100 is a backside illuminated (Backside Illumination, BSI) pixel wafer, and the first surface 101 of the pixel substrate 100 is a light-receiving surface.

The pixel substrate 100 includes a photosensitive region 100P, and the photosensitive region 100P is configured to receive an optical signal and convert the optical signal into an electrical signal. In this embodiment, the photosensitive area 100P includes an array of pixel unit areas, in which pixel units (not shown) are formed, and the pixel units are configured to receive optical signals so as to convert the optical signals into electrical signals.

In this embodiment, in the step of the pixel substrate 100, the plurality of pixel unit areas are arranged in an array, so that it is beneficial to uniformly receive the optical signals.

The pixel substrate 100 of the predetermined pixel unit area 100px is used for electrically connecting with the interconnection layer and the ground line.

In this embodiment, the number of pixel unit areas in the preset pixel unit area 100px is 1, and in other embodiments, the number of pixel unit areas may be a natural number greater than 1.

The lead region 100N is used for wiring and forming leads to make electrical connection between the pixel cell or other device structure and external circuitry.

In this embodiment, in the step of providing the pixel substrate 100, the lead area 100N is disposed around the photosensitive area 100P, so as to facilitate the photosensitive area 100P to receive an optical signal.

The interconnect layer is used to make electrical connection between the pixel cells and also between the pixel cells and an external circuit or other interconnect structure. In particular, the interconnect layer includes one or more layers of interconnect lines.

In this embodiment, the interconnect layers include a first interconnect layer 111 located in the dielectric layer 100P of the photosensitive region 100P, and a second interconnect layer 112 located in the dielectric layer 120 of the lead region 100N, the second interconnect layer 112 being electrically connected to the first interconnect layer 111. The first interconnect layer 111 and the second interconnect layer 112 are used to make electrical connection between the pixel unit and the pad layer 150 (shown in fig. 20), thereby making electrical connection between the pixel unit and an external circuit.

The materials of the first interconnect layer 111 and the second interconnect layer 112 are metals, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

In this embodiment, a connection structure 115 is further formed in the dielectric layer 120 of the preset pixel unit area 100px, and the connection structure 115 is respectively contacted with the first interconnection layer 111 and the pixel substrate 100 under the orthographic projection of the photosensitive area 100P.

The connection structure 115 is in contact with the first interconnection layer 111 and with the pixel substrate 100 of the preset pixel unit area 100px, thereby achieving electrical connection between the pixel substrate 100 of the preset pixel unit area 100px and the first interconnection layer 111.

The connection structure 115 penetrates through the dielectric layer 120 between the first interconnection layer 111 and the pixel substrate 100 of the preset pixel unit area 100px, and contacts with the first interconnection layer 111 and the pixel substrate 100, respectively, so as to realize electrical connection between the first interconnection layer 111 and the pixel substrate 100 of the preset pixel unit area 100 px.

In this embodiment, the connection structure 115 is formed in a back-end-of-line process. In this embodiment, the material of the connection structure 115 is the same as that of the first conductive plug 121 and the second conductive plug 122, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

In this embodiment, the interconnection layer further includes: a third interconnect layer 113 in the dielectric layer 120 of the photosensitive region 100P and the wiring region 100N, the third interconnect layer 113 being located on a side of the first interconnect layer 111 away from the second surface 102 and on a side of the second interconnect layer 112 away from the second surface; and a first conductive plug 121 between the first interconnect layer 111 and the third interconnect layer 113, and a second conductive plug 122 between the second interconnect layer 112 and the third interconnect layer 113, the first conductive plug 121 for making an electrical connection between the first interconnect layer 111 and the third interconnect layer 113, the second conductive plug 122 for making an electrical connection between the second interconnect layer 112 and the third interconnect layer 113.

The electrical connection between the first interconnect layer 111 and the second interconnect layer 112 is achieved by the third interconnect layer 113, and the first conductive plug 121 and the second conductive plug 122.

The materials of the third interconnection layer 113, the first conductive plugs 121, and the second conductive plugs 122 are all metals, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

The isolation trench 143 is located between adjacent pixel cell regions, and is used for isolating the adjacent pixel cell regions and also for providing a space position for the subsequent formation of an isolation structure.

In this embodiment, the isolation trench 143 is a deep trench isolation (Deep Trench Isolation, DTI), the depth of the isolation trench 143 penetrating through the pixel substrate 100 is larger, the depth of the isolation trench 143 is larger than the depth of the light trapping groove 197, and even much larger than the depth of the light trapping groove 197, so that a better isolation effect can be achieved for the adjacent pixel unit regions, and the depth of the subsequently formed isolation structure is also larger, which is beneficial to better realizing the optical isolation for the adjacent pixel unit regions.

In this embodiment, in the step of providing the pixel substrate 100, the isolation trench 142 penetrates through the pixel substrate 143, so that the isolation effect of the adjacent pixel unit area is improved, and the depth of the subsequently formed isolation structure is also larger, so that the optical isolation of the adjacent pixel unit area is better realized.

In this embodiment, in the step of providing the pixel substrate 100, a dielectric layer 120 is formed on the second surface 102, and the dielectric layer 120 is formed with the interconnection layer.

Dielectric layer 120 is used to achieve isolation between interconnect layers. The material of the dielectric layer 120 is a dielectric material, for example: one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, and ultra-low-k dielectric material. In this embodiment, in the step of providing the pixel substrate 100, the logic substrate 200 or the memory chip or the sensor chip is further bonded on the dielectric layer 120 of the second surface 102 of the pixel substrate 100.

In this embodiment, the logic substrate 200 is bonded to the dielectric layer 120 on the second surface 102 of the pixel substrate 100.

The Logic substrate 200 serves as a Logic Wafer (Logic Wafer) for analyzing the electrical signals provided by the pixel substrate 100. Specifically, a logic device for analyzing and processing the electrical signal supplied from the pixel substrate 100 is formed in the logic substrate 200.

By disposing the pixel region (i.e., the photosensitive region 100P) and the logic region on different substrates, and bonding the pixel substrate 100 and the logic substrate 200 together, the pixel area is advantageously increased, the path of light reaching the photoelectric element is also advantageously shortened, the scattering of light is reduced, the light is more focused, the photosensitive capability of the photoelectric sensor in a weak light environment is further improved, and system noise and crosstalk are reduced.

As an embodiment, the bonding between the logic substrate 200 and the dielectric layer 120 of the second surface 102 of the pixel substrate 100 is achieved by Hybrid bonding (Hybrid bonding).

In this embodiment, in the step of providing the pixel substrate 100, the light trapping groove 197 is further formed in the first surface 101 of the pixel unit area.

The light trapping groove 197 is used for forming a conformal medium layer subsequently, so that the refractive index change between air and the pixel substrate 100 can be slowed down, the high reflectivity caused by the refractive index mutation at the interface of the medium change is reduced, more light enters the photoelectric element, and the transmittance of the incident light is improved.

In this embodiment, the light trapping groove 197 has an inverted pyramid structure (Inverted Pyramid Structure).

The shape of the light trapping groove 197 is not limited to this. In a practical process, the light trapping groove may also have other shapes, for example: the pixel unit can be in a rectangular structure, and accordingly the effect of improving the optical transmittance of the pixel unit area can be achieved.

Referring to fig. 11 to 13 in combination, an insulating layer 151 is formed on the first surface 101 outside the isolation trench 143, and a first opening 154 communicating with the isolation trench 143 and a ground trench 148 in the predetermined pixel cell region 100px and exposing the pixel substrate 100 are formed in the insulating layer 151.

The first opening 154 is used to provide a spatial location for a subsequently formed isolation structure, and the ground trench 148 is used to provide a spatial location for a subsequently formed ground line.

In this embodiment, in the same step, the first opening 154 communicating with the isolation trench 143 is formed in the insulating layer 151, and the grounding trench 148 exposing the pixel substrate 100 is formed in the insulating layer 151 of the preset pixel unit area 100 px.

The step of forming the insulating layer 151 having the first opening 154 and the ground trench 148 is described in detail below with reference to the accompanying drawings.

Referring to fig. 11, an insulating layer 151 is formed on the first surface 101, the insulating layer 151 covering the first surface 101 and sealing the top of the isolation trench 143.

The insulating layer 151 is used to provide a space for the subsequent formation of the ground trench and the first opening.

In this embodiment, the insulating layer 151 is made of an insulating material, so as to prevent the electrical performance of the photoelectric sensor from being affected. In this embodiment, the material of the insulating layer 151 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. As an example, the material of the insulating layer 151 is silicon oxide. The silicon oxide has high process compatibility and low cost, and has good light transmission performance and insulating performance.

In this embodiment, the insulating layer 151 is formed by a chemical vapor deposition process. By means of a chemical vapor deposition process, the probability that the insulating layer 151 is filled in the isolation groove 143 is reduced while the insulating layer 151 seals the top of the isolation groove 143, so that the influence on the subsequent process for forming the isolation structure in the isolation groove 143 is reduced.

With continued reference to fig. 11, before forming the insulating layer 151, further includes: a conformal dielectric layer 166 is formed in the light trapping trenches 197 and isolation trenches 143.

Note that the conformal dielectric layer 166 is also formed on the remaining first surface 101. The conformal dielectric layer 166 is used to optically isolate adjacent pixel cell regions in conjunction with subsequently filled isolation structures.

The conformal dielectric layer 166 is a stacked structure, and includes an interfacial buffer layer 180, a negatively charged dielectric layer 181, and an isolation layer 182, which are stacked in sequence.

The interface buffer layer 180 is used for repairing surface defects of the inner surfaces of the isolation trench 143 and the light trap 197, and is beneficial to improving problems of dark current (dark current) and white pixel (white pixel) of the photosensor caused by the surface defects, and improving smoothness and interface quality of the inner surfaces of the isolation trench 143 and the light trap 197 and the first surface 101.

As an example, the material of the interface buffer layer 180 is silicon oxide. In particular, the interface buffer layer 180 may be decoupled plasma silicon oxide (Decouple plasma oxide, DPO).

In this embodiment, the process of forming the interface buffer layer 180 includes a decoupled plasma oxidation (Decouple plasma oxide) process.

In other embodiments, other oxidation processes may also be employed, such as: a high temperature oxidation process (HighTemperature Oxide, HTO) and the like, to form the interfacial buffer layer. In other embodiments, a deposition process may also be used to form the interfacial buffer layer.

The negatively charged dielectric layer 181 has a more comprehensive negative charge than a conventional dielectric layer, and the negative charge can increase hole accumulation at the interface of the negatively charged dielectric layer 181, and accordingly can gather holes at the bottom and the side wall of the first surface 101 and the isolation structure formed subsequently, so as to form a P-type protection structure, which is beneficial to preventing the leakage problem of the first surface 101 and the side wall of the isolation structure, and is also beneficial to improving the uniformity of the electric field inside the pixel.

The negatively charged dielectric layer 181 may have a single layer structure or a stacked structure. As an example, the negatively charged dielectric layer 181 has a stacked structure and includes a first dielectric layer 181a and a second dielectric layer 181b disposed on the first dielectric layer 181 a. As an embodiment, the material of the first dielectric layer 181a is alumina, and the material of the second dielectric layer 181b is tantalum oxide. The second dielectric layer 181b is made of tantalum oxide, and can also play a role in increasing transmission, so that alignment of a subsequent photolithography process is facilitated.

As an embodiment, a furnace tube process is used to form the first dielectric layer 181a; the second dielectric layer 181b is formed using a Physical Vapor Deposition (PVD) process.

In other embodiments, the material of the negatively charged dielectric layer may also be a nitride dielectric material. The nitride material may be silicon nitride, nitrogen-rich silicon nitride, or other nitrogen-rich dielectric films such as tantalum nitride, titanium nitride, hafnium nitride, aluminum nitride, magnesium nitride, or other metal nitrides.

The isolation layer 182 is used for isolating the negatively charged dielectric layer 181 from the subsequently formed isolation structure, so as to ensure the stability of the P-type protection structure formed at the interface of the negatively charged dielectric layer 181, and further ensure that the negatively charged dielectric layer 181 is used for preventing the first surface 101 and the sidewall of the isolation structure from generating leakage.

The material of the isolation layer 182 is a dielectric material. As an example, the material of the isolation layer 182 is silicon oxide. In other embodiments, the material of the isolation layer may also be other dielectric materials.

In this embodiment, the process of forming the isolation layer 182 includes an Atomic Layer Deposition (ALD) process. The thin film prepared by the atomic layer deposition process has the advantages of good bonding strength, consistent film thickness, good component uniformity, good conformality and the like, and is beneficial to improving the thickness consistency and the step coverage capability of the isolation layer 50.

Referring to fig. 12, the insulating layer 151 is planarized.

Specifically, the insulating layer 151 is planarized, so that it is advantageous to provide a flat and smooth surface for subsequent processes.

In this embodiment, the planarization process is performed on the insulating layer 151 through a Chemical Mechanical Polishing (CMP) process.

It should be noted that this step may be omitted if the subsequent planarization process is performed on the first conductive material layer higher than the top surface of the insulating layer 151.

Referring to fig. 13, the insulating layer 151 on top of the isolation trench 143 and the predetermined pixel unit region 100px is removed, a first opening 154 communicating with the isolation trench 143 is formed in the insulating layer 151, and a ground trench 148 exposing the pixel substrate 100px is formed in the insulating layer 151 of the predetermined pixel unit region 100 px.

In this embodiment, removing the insulating layer 151 on top of the isolation trench 143 and the insulating layer 151 of the preset pixel unit area includes: a photolithography pattern layer (not shown) is formed on the insulating layer 151, and exposes the insulating layer 151 on top of the isolation trench 143 and the insulating layer 151 of the predetermined pixel cell region.

Specifically, a photoresist layer (not shown) is formed on the insulating layer 151, and the photoresist layer is converted into a photoresist pattern layer by means of exposure and development.

In this embodiment, after forming the photolithography pattern layer, the exposed insulating layer 151 is removed by using the photolithography pattern layer as a mask, so as to form the first opening 154 and the ground trench 148.

In this embodiment, the exposed insulating layer 151 is removed by an anisotropic etching process.

Specifically, the anisotropic etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, and has higher process controllability and etching precision, thereby improving the size precision and the morphology quality of the first opening 154 and the grounding groove 148, and being beneficial to reducing the probability of damaging the pixel substrate 100.

After the first openings 154 and the ground trenches 148 are formed, the photolithographic pattern layer is removed, thereby reducing the probability of the photolithographic pattern layer affecting the subsequent process. In this embodiment, an ashing process is used to remove the photolithographic pattern layer.

Referring to fig. 14, an isolation structure including a conductive layer 110 is formed in the isolation trench 143 and the first opening 154, and a ground line 220 contacting the pixel substrate 100 of the predetermined pixel cell area 100px is formed in the ground trench 148.

The isolation structure is used to reduce optical and electrical crosstalk between adjacent pixel cells.

In this embodiment, the isolation structure is a deep trench isolation (Deep Trench Isolation, DTI) structure.

In this embodiment, the isolation structure includes the conductive layer 110, so that a voltage is applied to the conductive layer 110 subsequently, thereby adsorbing positive charges on the sidewall of the isolation structure, thereby being beneficial to improving the interface state of the sidewall of the isolation structure and reducing dark current of the pixel unit.

The end of the conductive layer 110 is exposed on the first surface 101, so that a metal grid contacting with the conductive layer 110 can be formed on the first surface 101 later, and the electrical property of the conductive layer 110 can be led out through the metal grid.

In this embodiment, the material of the conductive layer 110 is a metal material. The metal material has good conductivity, is usually an opaque material, and can also play a role in isolating light between adjacent pixel units.

In this embodiment, the material of the conductive layer 110 includes one or more of tungsten, aluminum, titanium nitride, tantalum nitride, and copper. As an embodiment, the material of the conductive layer 110 is tungsten, which is not easy to diffuse and has superior hole filling capability, so that the filling effect of the conductive layer 110 in the deep trench is improved, and the tungsten is a light-tight metal material, which can play a role in light isolation, and is beneficial to making the reduction effect of the isolation structure on the optical crosstalk between adjacent pixel units more remarkable.

The ground line 220 is used for realizing the electrical connection between the pixel substrate 100 of the predetermined pixel unit area 100px and the subsequent pixel unit area.

Specifically, by forming the ground line 220 in contact with the pixel substrate 100 of the preset pixel unit area 100px and subsequently forming the metal grid in contact with the conductive layer 110, and the ground line 220 is electrically connected with the metal grid, accordingly, when the photoelectric sensor works, through the pad layer 150, the second interconnection layer 112, the first interconnection layer 111, the connection structure 115, the pixel substrate 100 and the ground line 220 which are sequentially connected, the conductive layer 110 of the isolation structure can be connected with a negative potential by applying the negative potential to the pad layer 150, thereby being beneficial to adsorbing positive charges on the side wall of the isolation structure, further being beneficial to improving the interface state of the side wall of the isolation structure, and reducing the dark current of the pixel unit.

In this embodiment, the material of the grounding wire 220 is a metal material. As an example, the material of the ground line 220 includes one or both of aluminum and tungsten.

In this embodiment, the ground line 220 and the conductive layer 110 are formed in the same step, so that the material of the ground line 220 and the material of the conductive layer 110 are the same.

Specifically, the step of forming the isolation structure within the isolation trench 143 and the first opening 154, and forming the ground line 220 within the ground trench 148 includes: forming a first conductive material layer (not shown) within the isolation trench 143, the first opening 154, and the ground trench 148; the first conductive material layer is planarized to remove the first conductive material layer higher than the top surface of the insulating layer 151, the first conductive material layer located in the isolation trench 143 and the first opening 154 serves as the conductive layer 110, and the remaining first conductive material layer located in the ground trench 148 serves as the ground line 220.

The first conductive material layer is used to subsequently form the isolation structures and the ground line 220.

In this embodiment, the process of forming the first conductive material layer includes a chemical vapor deposition process, and in other embodiments, the process of forming the first conductive material layer may also be a physical vapor deposition process.

In this embodiment, spacers 105 are formed on the sidewalls and bottom of the isolation trenches prior to forming the first conductive material layer.

Spacer layer 105 serves to enhance bonding between the subsequently formed first conductive material layer and the second dielectric layer 181b and, when the material of the first conductive material layer is tungsten, to facilitate reducing the probability of fluorine-containing reactive precursors corroding the conformal dielectric layer 166 during tungsten formation.

In this embodiment, the material of the spacer layer 105 is titanium nitride, and in other embodiments, the material of the spacer layer 105 may also be titanium.

In this embodiment, the first conductive material layer is planarized to remove the first conductive material layer higher than the top surface of the insulating layer 151, so as to expose the top surfaces of the conductive layer 110 and the ground line 220, which is beneficial to forming a metal grid electrically connected to the ground line 220.

In this embodiment, the planarization process is performed on the first conductive material layer through a chemical mechanical polishing process.

Referring to fig. 15, a metal mesh 144 contacting the conductive layer 110 and the ground line 220 is formed on the isolation structure.

In this embodiment, after the conductive layer 110 and the ground line 220 are formed, the metal grid 144 contacting with the conductive layer 110 is directly formed on the isolation structure, so that the process flow is simplified, the number of photomasks is reduced, the process cost is saved, and the process efficiency is improved.

The metal grid 144 is electrically connected with the grounding wire 220, so that the interconnection layer, the connection structure 115, the pixel substrate 100, the metal grid 144 and the conductive layer 110 are electrically connected with a subsequently formed welding pad layer, and the conductive layer 110 of the isolation structure can be connected with negative potential by applying negative potential to the welding pad layer 150, thereby being beneficial to adsorbing positive charges on the side wall of the isolation structure, improving the interface state of the side wall of the isolation structure and reducing dark current of a pixel unit.

In this embodiment, the material of the metal mesh 144 is a metal material, and the material of the metal mesh 144 includes one or both of aluminum and tungsten. As one example, the material of the metal mesh 144 is aluminum. Aluminum is a material which is easy to etch, so that a patterning process for forming the metal grid 144 is facilitated, the aluminum is good in conductivity, the electrical connection performance of the metal grid 144 is improved, and in addition, aluminum is an opaque material, so that the effect of reducing optical crosstalk between adjacent pixel units by the metal grid 144 is guaranteed.

In this embodiment, the step of forming the metal mesh 144 includes: forming a metal material layer (not shown) on the isolation structure, the insulating layer 151, and the ground line 220; the metal material layer is patterned, leaving the metal material layer on top of the conductive layer 110 as a metal mesh, and the metal mesh 144 extends to cover the top of the ground line 220 and is connected to the ground line 220.

In this embodiment, the metal material layer is directly formed on the isolation structure, the insulating layer 151 and the ground line 220, so that the number of masks can be reduced.

In this embodiment, a metal material layer on top of the ground line 220 is reserved as the ground line 220, and the ground line 220 is connected to the metal mesh 144, so that the ground line 220 is advantageously electrically connected to the metal mesh 144.

The metal material layer is used to form the metal mesh 144 and the ground line 220.

In this embodiment, the metal material layer is formed by a physical vapor deposition process, and in other embodiments, the metal material layer may also be formed by a chemical vapor deposition process.

In this embodiment, an etching process is used to pattern the metal material layer. Specifically, an anisotropic dry etching process is used to pattern the metal material layer. The anisotropic dry etching process has higher etching profile control, so that the profile morphology of the metal material layer is controlled accurately.

Referring to fig. 16, after forming the metal mesh 144, a first passivation layer 160 is formed on the first surface 101, and the first passivation layer 160 covers the metal mesh 144 and the ground line 220.

The first passivation layer 160 is used to protect the metal mesh 144 and the ground line 220, and reduce the probability that the metal mesh 144 and the ground line 220 are affected by the subsequent process.

In this embodiment, the material of the first passivation layer 160 is an insulating material, including one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the material of the first passivation layer 160 is silicon oxide.

In this embodiment, the step of forming the first passivation layer 160 includes: forming a passivation material layer (not shown) on the first surface 101 using a deposition process, the passivation material layer covering the metal grid 144; the passivation material layer is planarized, and the remaining passivation material layer on the first surface 101 and covering the metal mesh 144 is used as the first passivation layer 160.

The planarization process is performed on the passivation material layer after the deposition process, so that the flatness and the high uniformity of the top surface of the first passivation layer 160 are improved, so that a flat surface is provided for the subsequent process.

As an embodiment, the planarization process is performed using a chemical mechanical planarization process.

It should be noted that, whether to perform planarization treatment on the passivation material layer can be determined according to the requirement of the subsequent process.

Referring to fig. 17 to 20, a pad layer 150 is formed over the interconnection layer, and the pad layer 150 is connected to the interconnection layer of the lead region. In this embodiment, after the metal mesh 144 is formed, the pad layer 150 is formed in the lead region 100N.

In this embodiment, in the step of forming the pad layer 150 above the interconnection layer, the pad layer 150 is located in the pixel substrate 100 and the dielectric layer 120.

The pad layer 150 is in contact with the interconnect layer of the lead region 100N. In this embodiment, the pad layer 150 is in contact with the second interconnect layer 112.

In this embodiment, the pad layer 150 is used to access a negative potential, so that the conductive layer 110 of the isolation structure is accessed to the negative potential, thereby facilitating the adsorption of positive charges on the sidewall of the isolation structure, further facilitating the improvement of the interface state of the sidewall of the isolation structure, and reducing the dark current of the pixel unit.

The specific steps of forming the pad layer 150 according to this embodiment will be described in detail with reference to the accompanying drawings.

As shown in fig. 17 to 19, the step of forming the pad layer 150 includes: in the lead region 100N, an opening 140 penetrating the pixel substrate 100 above the interconnect layer and exposing the interconnect layer is formed.

The openings 140 are used to provide space for the subsequent formation of the pad layer 150, and the openings 140 expose the second interconnect layer 112, so that the pad layer 150 formed at the bottom of the openings 140 can contact the second interconnect layer 112, thereby electrically connecting the pad layer 150 and the second interconnect layer 112.

Specifically, in the step of forming the opening 140, the opening includes a second opening 199 located in the pixel substrate 100 and a third opening 142 located in the dielectric layer 120 at the bottom of the second opening 199, and the second opening 199 and the third opening 142 are in communication.

As an example, the bottom opening size of the second opening 199 is larger than the top opening size of the third opening 142.

Specifically, as shown in fig. 17, the step of forming the opening 140 includes: a second opening 199 is formed through the pixel substrate 100 of the lead region 100N, the second opening 199 exposing the dielectric layer 120.

The second opening 199 is used to expose the dielectric layer 120, thereby facilitating the subsequent formation of a third opening.

As an example, the second opening 199 is formed using an anisotropic dry etching process. The anisotropic dry etching process has high etching profile control, and is favorable for precisely controlling the profile shape of the second opening 199.

As shown in fig. 18, the step of forming the opening 140 further includes: after forming the second opening 199, the isolation layer 145 is formed on the sidewalls and bottom of the second opening 199 and the first passivation layer 160.

The isolation layer 145 is used for protecting the pixel substrate 100 and also for isolating the pixel substrate 100 from a subsequently formed pad layer. In this embodiment, the material of the isolation layer 145 is silicon oxide.

In this embodiment, the isolation layer 145 conformally covers the sidewalls and bottom of the second opening 199 and the first passivation layer 160.

As shown in fig. 19, the step of forming the opening 140 further includes: a third opening 142 is formed through the dielectric layer 120 under the second opening 199, exposing the second interconnect layer 112, the third opening 142 and the second opening 199 constituting the opening 140. Specifically, the third opening 142 exposes a portion of the top of the second interconnect layer 112 toward the first surface 101.

The third opening 142 is used to expose the second interconnect layer 112, so as to facilitate electrical connection between a subsequently formed pad layer and the second interconnect layer 112.

In the step of forming the third opening 142, the third opening 142 also penetrates a portion of the isolation layer 145 above the second interconnect layer 112.

As an example, a third opening 142 is formed through the dielectric layer 120 under the second opening 199 using an anisotropic dry etching process. The anisotropic dry etching process has high etching profile control, is favorable for precisely controlling the profile of the third opening 142, and reduces the probability of causing false etching of the second interconnection layer 112.

As shown in fig. 20, a pad layer 150 is formed in the opening.

In this embodiment, the pad layer 150 is in contact with the second interconnect layer 112 for making electrical connection between the second interconnect layer 112 and an external circuit or other interconnect structure.

More specifically, the pad layer 150 is in contact with the second interconnect layer 112, the second interconnect layer 112 is electrically connected with the first interconnect layer 111, the first interconnect layer 111 is electrically connected with the pixel substrate 100 through the connection structure 115, the pixel substrate 100 is electrically connected with the conductive layer 110 sequentially through the grounding wire 220 and the metal grid 144, accordingly, when the photoelectric sensor works, the conductive layer 110 of the isolation structure can be connected with the negative potential by applying the negative potential to the pad layer 150 through the pad layer 150, the second interconnect layer 112, the first interconnect layer 111, the connection structure 115, the pixel substrate 100 and the grounding wire 220 sequentially electrically connected with each other, so that positive charges are adsorbed on the side wall of the isolation structure, interface states of the side wall of the isolation structure are improved, and dark current of the pixel unit is reduced.

In addition, in this embodiment, by applying a negative potential to the pad layer 150, the conductive layer 110 of the isolation structure is connected to the negative potential, so that the pad layer electrically connected to the metal grid 144 does not need to be additionally formed on the first surface, and accordingly, the height consistency of the pad layer 150 of the photoelectric sensor is ensured, and further, the complexity of the subsequent packaging process and testing is reduced.

The material of pad layer 150 is a conductive material. In this embodiment, the material of the pad layer 150 includes one or more of aluminum, titanium, gold, and tin-doped indium oxide. As an example, the material of the pad layer 150 is aluminum. Aluminum has good conductivity and is a material that is easily etched, thereby easily patterning the pad layer 150.

The pad layer 150 is located in the opening 140, and the top surface of the pad layer 150 is lower than the first surface 101.

In this embodiment, the step of forming the pad layer 150 includes: forming a pad material layer (not shown) on the bottom and sidewalls of the opening 140 and the isolation layer 145; a portion of the pad material layer at the first surface 101 and at the bottom of the opening 140 is removed, and the remaining pad material layer at the bottom of the opening 140 and in contact with the second interconnect layer 112 is used as a pad layer 150.

As shown in fig. 21, after forming the pad layer 150, a second passivation layer 155 is formed on the top and side walls of the pad layer 150, the side and bottom walls of the second opening 199, and the first passivation layer 160.

Specifically, the second passivation layer 155 covers sidewalls and bottom surfaces of the second opening 199, the pad layer 150, and the first passivation layer 160. More specifically, the second passivation layer 155 conformally covers the isolation layer 145 and the pad layer 150.

The second passivation layer 155 serves to protect the solder pad layer 150.

In this embodiment, the material of the second passivation layer 155 is silicon oxide. In other embodiments, the material of the second passivation layer may also be silicon nitride or silicon oxynitride.

In this embodiment, the second passivation layer 155 is formed using a chemical vapor deposition process. The chemical vapor deposition process has higher covering capability, mature process and high process compatibility. In other embodiments, the second passivation layer may also be formed using an atomic layer deposition process, or an atomic layer deposition process and a chemical vapor deposition process.

Referring to fig. 21 and 22, fig. 21 is a cross-sectional view, fig. 22 is a top view corresponding to fig. 21, a portion of the second passivation layer 155 on the top surface of the pad layer 150 is removed, the pad layer 150 is exposed, and the remaining second passivation layer 155 and the first passivation layer 160 are used to form a passivation layer.

The pad layer 150 is exposed so as to enable electrical connection between the pad layer 150 and an external circuit, for example: and the packaging and testing processes are facilitated.

In this embodiment, an anisotropic dry etching process is used to remove a portion of the second passivation layer 155 on the top surface of the pad layer 150.

Fig. 23 to 25 are schematic structural views corresponding to each step in another embodiment of the method for forming a photoelectric sensor of the present invention. The points of the present embodiment that are the same as those of the foregoing embodiment are not described in detail here, and the difference between the present embodiment and the foregoing embodiment is that: a first protective layer is formed over the isolation structure, insulating layer, and ground line prior to forming the metal material layer.

The specific steps of the present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 23, the forming method further includes: a first protective layer 448 is formed on the isolation structure, the insulating layer 451, and the ground line 420 before the metal material layer is formed.

In one case, when a portion of the conductive layer 410 does not need to contact with the metal grid, the first protection layer 448 is used to protect the conductive layer 410 that does not need to contact with the metal grid, so that it is beneficial to reduce the probability of misetching the conductive layer 410 in the process of etching the metal material layer after the metal material layer is subsequently formed, and further is beneficial to determine the position and the number of the conductive layers 410 that contact with the metal grid according to the actual situation.

In another case, when the metal grid does not completely cover the conductive layer 410 below the metal grid, the first protection layer 448 is used to protect the surface of the conductive layer 410 that cannot be covered by the metal grid, so that the probability of misetching the conductive layer 410 is reduced in the subsequent etching process of the metal material layer.

In this embodiment, the first protection layer is formed by a chemical vapor deposition process.

Referring to fig. 24, a fourth opening 449 is formed in the first protective layer 448, the fourth opening 449 exposing the conductive layer 410 of all the isolation structures or a portion of the conductive layer 410 of the isolation structures, and the fourth opening 449 also exposing the ground line 420.

The fourth opening 449 is used to provide a spatial location for the subsequent formation of the metal grid.

In this embodiment, the fourth opening 449 is formed by using an anisotropic dry etching process. The anisotropic dry etching process has higher etching profile control, and is favorable for accurately controlling the profile shape of the fourth opening 449.

Referring to fig. 25, in the step of forming the metal material layer 499 on the isolation structure, the insulating layer 451, and the ground line 420, the metal material layer 499 covers the first protective layer 448 and fills in the fourth opening 449.

The metal material layer 499 is used for subsequent formation of metal grids.

The metal material layer covers the first protective layer 448 and fills the fourth opening 449, thereby facilitating the electrical connection of the metal mesh formed later to the ground line 420 and the conductive layer 410.

Specifically, the specific description of the forming method of the present embodiment may be combined with the related description referring to the first embodiment, which is not repeated here.

Fig. 26 and 27 are schematic structural views corresponding to steps in a further embodiment of a method for forming a photoelectric sensor according to the present invention. The points of the present embodiment that are the same as those of the foregoing embodiment are not described herein, and the difference between the present embodiment and the first embodiment is that: in the same step, the isolation structure, the ground line, and the metal mesh are formed.

The isolation structure, the ground line 520 and the metal grid 544 are formed in the same step, which is beneficial to further simplifying the process flow, reducing the number of photomasks, further saving the process cost and improving the process efficiency.

In the following, the detailed description of the formation of the isolation structure, the ground line and the metal mesh in the same step will be given with reference to the accompanying drawings.

Referring to fig. 26, the step of forming the isolation structure, the ground line, and the metal mesh includes: a first conductive material layer 599 is formed within the isolation trench (not labeled), the first opening (not labeled), and the ground trench (not labeled), the first conductive material layer 599 also covering the insulating layer 551.

The first conductive material layer 599 is used for subsequent formation of a conductive layer, a metal mesh, and a ground line.

The material of the first conductive material layer 599 includes one or both of aluminum and tungsten. In this embodiment, the material of the first conductive material layer 599 is tungsten.

In this embodiment, the first conductive material layer 599 is formed by a chemical vapor deposition process, and in other embodiments, the first conductive material layer may also be formed by a physical vapor deposition process.

In this embodiment, the step of forming isolation structures, ground lines, and metal grid 544 further includes: before the first conductive material layer 599 is subjected to the patterning process, a second protective layer 598 is formed to cover the first conductive material layer 599.

In this embodiment, when the first conductive material layer 599 is patterned to form a metal grid, the second protective layer 598 is patterned correspondingly, so that the remaining second protective layer 598 above the metal grid can form a grid structure, thereby improving the total thickness of the grid structure, and being beneficial to improving the effect of the grid structure on reducing optical crosstalk between adjacent pixel units, and the second protective layer 598 is used for protecting the first conductive material layer 599 during the subsequent patterning of the first conductive material layer 599, and in addition, the second protective layer 598 also increases a process window for patterning the first conductive material layer 599. In this embodiment, the material of the second protection layer 598 is silicon oxide, and in other embodiments, the second protection layer may be silicon nitride or silicon oxynitride. In this embodiment, the material of the second protection layer 598 is silicon oxide, and in other embodiments, the second protection layer 598 may be silicon nitride or silicon oxynitride.

In this embodiment, the second protection layer 598 is formed by a chemical vapor deposition process, and the process for forming the second protection layer 598 is the same as the process for forming the first conductive material layer 599, so that the process compatibility is improved. In other embodiments, the second protective layer may also be formed by a physical vapor deposition process.

Referring to fig. 27, first conductive material layer 599 is patterned to leave first conductive material layer located within the isolation trenches and first openings as conductive layer 510, remaining first conductive material layer 599 located on top of conductive layer 510 and in contact with conductive layer 510 as metal grid 544, first conductive material layer 599 located within the ground trenches as ground line 520, and metal grid 544 extending over the top of ground line 520 and connected to ground line 520.

Specifically, a photolithography pattern layer (not shown) is formed on the first conductive material layer 599, the photolithography pattern layer covering the first conductive material layer 599 on top of the isolation trench and the ground trench; the exposed first conductive material layer 599 is removed using the photolithographic patterned layer as a mask, the remaining first conductive material layer 599 located within the isolation trench and the first opening is used as the conductive layer 510, the remaining first conductive material layer 599 located on top of the conductive layer 510 and in contact with the conductive layer 510 is used as the metal grid 544, and the first conductive material layer 599 located within the ground trench is used as the ground line 520.

In this embodiment, the second protection layer 598 is formed on the first conductive material layer 599, so in the step of patterning, the second protection layer 598 and the first conductive material layer 599 are sequentially patterned from top to bottom.

Accordingly, the metal grid 544, with the remaining second protective layer 598 on top of the metal grid 544, forms a grid structure.

After forming isolation structures, ground lines 520, and metal grid 544, the photolithographic pattern layer is removed using an ashing process.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a photoelectric sensor, comprising:

providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite, the pixel substrate comprises a photosensitive area and a lead area, the photosensitive area comprises a plurality of pixel unit areas, at least one pixel unit area is used as a preset pixel unit area, an interconnection layer is formed on the second surface, and an isolation groove is formed between the pixel unit areas;

Forming an insulating layer on the first surface outside the isolation trench, wherein a first opening communicated with the isolation trench and a grounding trench which is positioned in the preset pixel unit area and exposes the pixel substrate are formed in the insulating layer;

forming an isolation structure in the isolation trench and the first opening, wherein the isolation structure comprises a conductive layer, and a grounding wire which is contacted with a pixel substrate of the preset pixel unit area is formed in the grounding trench;

forming a metal grid on the isolation structure, wherein the metal grid is in contact with the conductive layer and the grounding wire;

and forming a welding pad layer positioned above the interconnection layer, wherein the welding pad layer is connected with the interconnection layer of the lead area.

2. The method of forming a photosensor of claim 1 where the step of forming the pad layer includes: forming an opening penetrating through the pixel substrate above the interconnection layer and exposing the interconnection layer in the lead region;

a pad layer is formed within the opening.

3. The method of forming a photosensor according to claim 1, wherein in the step of providing a pixel substrate, a dielectric layer is formed on the second surface, the dielectric layer having the interconnect layer formed therein;

In the step of forming the opening, the opening comprises a second opening positioned in the pixel substrate and a third opening positioned in a dielectric layer at the bottom of the second opening, and the second opening and the third opening are communicated.

4. The method of forming a photoelectric sensor according to claim 1, wherein the step of forming an insulating layer having the first opening and a ground trench on the first surface outside the isolation trench comprises: forming an insulating layer on the first surface, the insulating layer covering the first surface and sealing the top of the isolation trench;

and removing the insulating layer positioned at the top of the isolation groove and in the preset pixel unit area, forming a first opening communicated with the isolation groove in the insulating layer, and forming a grounding groove exposing the pixel substrate in the insulating layer of the preset pixel unit area.

5. The method of forming a photosensor of claim 4, where removing the insulating layer at the top of the isolation trench and the insulating layer of the predetermined pixel cell region includes: forming a photoetching pattern layer on the insulating layer, wherein the photoetching pattern layer exposes the insulating layer at the top of the isolation groove and the insulating layer of the preset pixel unit area;

Removing the exposed insulating layer by taking the photoetching pattern layer as a mask to form the first opening and the grounding groove;

and removing the photoetching pattern layer.

6. The method of forming a photosensor of claim 1, where forming isolation structures in the isolation trenches and first openings and forming ground lines in the ground trenches includes: forming a first conductive material layer in the isolation trench, the first opening and the ground trench;

and flattening the first conductive material layer, removing the first conductive material layer higher than the top surface of the insulating layer, wherein the first conductive material layer positioned in the isolation groove and the first opening is used as a conductive layer, and the rest first conductive material layer positioned in the grounding groove is used as a grounding wire.

7. The method of forming a photosensor according to claim 1 or 6, wherein the step of forming the metal mesh includes: forming a metal material layer on the isolation structure, the insulating layer and the grounding wire; and patterning the metal material layer, and reserving the metal material layer positioned on the top of the conductive layer as a metal grid, wherein the metal grid extends to cover the top of the grounding wire and is connected with the grounding wire.

8. The method of claim 7, wherein the process of forming the metal material layer comprises a chemical vapor deposition process or a physical vapor deposition process.

9. The method of forming a photosensor of claim 7, further comprising: forming a first protective layer on the isolation structure, the insulating layer and the ground line before forming the metal material layer;

forming a fourth opening in the protective layer, wherein the fourth opening exposes all conductive layers of the isolation structures or part of conductive layers of the isolation structures, and the fourth opening also exposes the grounding wire;

in the step of forming a metal material layer on the isolation structure, the insulating layer and the ground line, the metal material layer covers the protective layer and fills in the fourth opening.

10. The method of forming a photosensor of claim 1, where the step of forming the isolation structure, ground line and metal mesh includes: forming a first conductive material layer in the isolation trench, the first opening and the ground trench, the first conductive material layer also covering the insulating layer;

And patterning the first conductive material layer, reserving the first conductive material layer positioned in the isolation groove and the first opening as a conductive layer, taking the remaining first conductive material layer positioned at the top of the conductive layer and contacted with the conductive layer as a metal grid, taking the first conductive material layer positioned in the grounding groove as a grounding wire, and extending the metal grid to cover the top of the grounding wire and connecting with the grounding wire.

11. The method of claim 6 or 10, wherein the process of forming the first conductive material layer comprises a chemical vapor deposition process or a physical vapor deposition process.

12. The method of forming a photosensor of claim 10 where the step of forming the isolation structure, ground line and metal mesh further comprises: forming a second protective layer covering the first conductive material layer before patterning the first conductive material layer;

and in the step of patterning, the second protective layer and the first conductive material layer are sequentially subjected to patterning from top to bottom, and the metal grid and the rest of the second protective layer positioned at the top of the metal grid form a grid structure.

13. The method of forming a photosensor according to claim 10 or 12, wherein the patterning process includes: an anisotropic etching process.

14. The method of forming a photosensor of claim 1 where the conductive layer material includes one or more of tungsten, aluminum, titanium nitride, tantalum nitride, copper;

the material of the grounding wire comprises one or two of aluminum and tungsten;

the material of the welding pad layer comprises one or more of aluminum, titanium, gold and tin-doped indium oxide;

the material of the metal mesh comprises one or two of aluminum and tungsten.

15. The method of claim 1, wherein the first surface is a back surface of a pixel substrate and the second surface is a front surface of the pixel substrate.

16. The method of forming a photosensor of claim 1 where in the step of providing a pixel substrate, a logic substrate or a memory chip or a sensor chip is also bonded to the second surface of the pixel substrate.

17. The method of forming a photosensor according to claim 1, wherein in the step of providing a pixel substrate, a light trapping groove is further formed in the first surface of the pixel unit area, and the insulating layer covers the light trapping groove.

18. The method of claim 1, wherein in the step of providing the pixel substrate, the isolation trench penetrates the pixel substrate.