CN116978972A - Photoelectric sensor and forming method thereof - Google Patents

Photoelectric sensor and forming method thereof Download PDF

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Publication number
CN116978972A
CN116978972A CN202210433912.2A CN202210433912A CN116978972A CN 116978972 A CN116978972 A CN 116978972A CN 202210433912 A CN202210433912 A CN 202210433912A CN 116978972 A CN116978972 A CN 116978972A
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layer
opening
hard mask
dielectric layer
forming
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石强
高长城
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202210433912.2A priority Critical patent/CN116978972A/en
Publication of CN116978972A publication Critical patent/CN116978972A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A photoelectric sensor and a forming method thereof, the photoelectric sensor includes: the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area positioned at the side part of the photosensitive area, and the photosensitive area comprises pixel unit areas which are arranged in an array; a dielectric layer on the second surface; the interconnection layer is positioned in the dielectric layer of the lead area and is electrically connected with the pixel unit area to be interconnected; the bottom hard mask layer is positioned in the dielectric layer, is positioned between the interconnection layer and the second surface and is provided with a first opening; and the second opening is positioned on one side of the first surface and penetrates through the pixel substrate and the dielectric layer on the bottom hard mask layer, and the bottom size of the second opening is larger than that of the first opening. The embodiment of the invention is beneficial to improving the performance of the photoelectric sensor.

Description

Photoelectric sensor and forming method thereof
Technical Field
The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a photoelectric sensor and a forming method thereof.
Background
A photosensor is a device that converts an optical signal into an electrical signal. The working principle is based on the photoelectric effect, which means that when light irradiates on certain substances, electrons of the substances absorb photon energy and corresponding electric effect phenomenon occurs.
For example, CCD (Charge Coupled Device ) image sensors and CMOS image sensors, which are widely used in digital cameras and other electronic optical devices, convert an optical image into an electrical signal by using a photoelectric conversion function and output the digital image. ToF (Time of Flight) distance sensor, for example: DTOF (Direct Time of Flight ) sensor, records the time at which the light pulse is emitted and detected, converting the time difference into distance information. The technique can be used in various ranging scenarios such as autopilot, sweeping robot, VR (Virtual Reality)/AR (Augmented Reality) modeling, etc.
However, the performance of the current photoelectric sensor still needs to be improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a photoelectric sensor and a forming method thereof, which are beneficial to improving the performance of the photoelectric sensor.
To solve the above problems, an embodiment of the present invention provides a photoelectric sensor, including: the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area positioned at the side part of the photosensitive area, and the photosensitive area comprises pixel unit areas which are arranged in an array; a dielectric layer on the second surface; the interconnection layer is positioned in the dielectric layer of the lead area and is electrically connected with the pixel unit area to be interconnected; the bottom hard mask layer is positioned in the dielectric layer, is positioned between the interconnection layer and the second surface and is provided with a first opening; the second opening is positioned on one side of the first surface and penetrates through the pixel substrate and the dielectric layer on the bottom hard mask layer, and the bottom size of the second opening is larger than that of the first opening; a third opening penetrating the dielectric layer at the bottom of the first opening and exposing the interconnection layer, wherein the second opening, the first opening and the third opening are communicated and form an opening; and the welding pad layer is positioned at the bottom of the opening and is contacted with the interconnection layer.
Correspondingly, the embodiment of the invention also provides a method for forming the photoelectric sensor, which comprises the following steps: providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite, the pixel substrate comprises a photosensitive area and a lead area positioned at the side part of the photosensitive area, the photosensitive area comprises pixel unit areas which are arranged in an array, a dielectric layer is formed on the second surface, an interconnection layer and a bottom hard mask layer are formed in the dielectric layer of the lead area, the interconnection layer is electrically connected with the pixel unit areas to be interconnected, a first opening is formed in the bottom hard mask layer, the first opening is filled with the dielectric layer, and the bottom hard mask layer is positioned between the interconnection layer and the second surface; forming a patterned top hard mask layer on the first surface, wherein a first mask opening positioned in the lead region is formed in the top hard mask layer, and the projection of the first opening on the first surface is positioned in the projection of the first mask opening on the first surface; removing the pixel substrate and the dielectric layer at the bottom of the first mask opening by taking the top hard mask layer as a mask, and forming an opening penetrating through the pixel substrate, the bottom hard mask layer and the dielectric layer at the top of the interconnection layer; and forming a pad layer in contact with the interconnection layer in the opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the photoelectric sensor provided by the embodiment of the invention, the bottom hard mask layer is positioned between the interconnection layer and the second surface, and the first opening is formed in the bottom hard mask layer, so that in the process of forming the third opening, the bottom hard mask layer can play a role of a mask, a photoetching mask is not required to be formed in the first opening, and only the mask layer is formed on the outer side of the second opening, so that the process of forming the third opening is avoided from depositing an excessively thick first photoetching mask layer, correspondingly, the first photoetching mask layer with patterns is avoided from being obtained by needing larger exposure energy, correspondingly, the service cycle of a machine is shortened, the process cost is reduced, meanwhile, the difficulty of a photoetching process is also reduced, the photoetching quality is correspondingly improved, and the forming quality of the opening is also improved; in addition, since the photolithographic mask is not required to be formed in the first opening, the limitation of the photolithographic mask thickness to the thickness of the pixel substrate is avoided correspondingly, the thickness of the pixel substrate is conveniently set according to the performance requirement of the photoelectric sensor, and in summary, the embodiment is beneficial to improving the performance of the photoelectric sensor.
In the method for forming the photoelectric sensor provided by the embodiment of the invention, the top hard mask layer is formed on the first surface, compared with the scheme of directly adopting the first photoetching mask layer for pattern transfer, the adoption of the top hard mask layer is beneficial to avoiding depositing the excessively thick first photoetching mask layer in the process of forming the patterned top hard mask layer, correspondingly, excessively large exposure energy is not needed, the service cycle of a machine is shortened, the process cost is reduced, meanwhile, the difficulty of a photoetching process is reduced, the photoetching quality is correspondingly improved, and the forming quality of an opening is improved; the first opening is formed in the bottom hard mask layer, so that the bottom hard mask layer is taken as a mask after the dielectric layer positioned in the first opening is removed in the process of forming the opening, the dielectric layer at the bottom of the first opening is removed without forming a photoetching mask layer additionally, the steps of depositing an excessively thick photoetching mask layer and carrying out secondary exposure are avoided, accordingly, the service cycle of a machine is shortened, the process cost is reduced, and in sum, the performance of the photoelectric sensor is improved.
Drawings
Fig. 1 to 8 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
FIG. 9 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 10 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the performance of the current semiconductor structure needs to be improved. The reason why the performance of a semiconductor structure is to be improved is analyzed by combining a method for forming the semiconductor structure. Fig. 1 to 8 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a pixel substrate 100 is provided, including a first surface 101 and a second surface 102 opposite to each other, where the pixel substrate 100 includes a photosensitive region 100P and a lead region 100N located at a side of the photosensitive region 100P, the photosensitive region 100P includes pixel unit regions (not shown) arranged in an array, a dielectric layer 105 is formed on the second surface 102, an interconnection layer 106 is formed in the dielectric layer 105 of the lead region 100N, and the interconnection layer 106 is electrically connected to the pixel unit regions to be interconnected.
Referring to fig. 2, a second substrate 110 is provided and the dielectric layer 105 is bonded to the second substrate 110.
Referring to fig. 3, a hard mask layer 111 and a protective layer 112 on the hard mask layer 111 are formed on the first surface 101.
Referring to fig. 4, a first photolithography mask layer 114 having a first mask opening 113 is formed on the protection layer 112.
Referring to fig. 5, the first photolithographic mask layer 114 (as shown in fig. 4) is used as a mask, the hard mask layer 111, the protection layer 112 and the pixel substrate 100 are removed along the first mask opening 113, and the surface of the dielectric layer 105 is exposed, so as to form a first trench 144 penetrating the hard mask layer 111, the protection layer 112 and the pixel substrate 100.
Referring to fig. 6, a second photolithographic mask layer 120 having a second mask opening 118 is formed on the protective layer 112 and the exposed surface of the dielectric layer 105, and a projection of the second mask opening 118 on the surface of the dielectric layer 105 is located inside the first trench 144.
Referring to fig. 7, the dielectric layer 105 on the interconnect layer 106 is removed along the second mask opening 118 by using the second photolithography mask layer 120 as a mask, and a second trench 148 exposing the interconnect layer 106 is formed in the dielectric layer 105.
Referring to fig. 8, a pad layer 122 is formed at the bottom of the first trench 144 and the bottom of the second trench 148, the pad layer 122 being in contact with the interconnect layer 106.
At present, by increasing the thickness of the pixel substrate 100, the path of the pixel unit is advantageously prolonged, so that the pixel substrate 100 can absorb quanta to a greater extent, and quantum efficiency is improved.
Therefore, in order to make the thickness of the first photolithographic mask layer 114 sufficient to form the first trench 144 penetrating the hard mask layer 111, the protective layer 112 and the pixel substrate 100, the first photolithographic mask layer 114 having the first mask opening 113 needs to be formed to be larger in thickness when the first photolithographic mask layer 114 is formed on the protective layer 112. However, increasing the thickness of the first photolithography mask layer 114 may result in a need for a larger exposure energy, shortening the lifetime of the tool, increasing the process cost, and at the same time, increasing the difficulty of the photolithography process and decreasing the photolithography quality.
The increase in thickness of the pixel substrate 100 correspondingly increases the depth of the first trench 144, which correspondingly also results in that when the second photolithography mask layer 120 with the second mask opening 118 is formed on the protection layer 112 and on the exposed surface of the dielectric layer 105, the thickness of the second photolithography mask layer 120 is too large, so that too much exposure energy is required and the second exposure is performed, the service period of the machine is increased, the process cost is increased, and meanwhile, the process window is too small, so that the difficulty of the photolithography process is increased, and the photolithography quality is reduced.
In order to solve the technical problem, an embodiment of the present invention provides a photoelectric sensor, including: the bottom hard mask layer is positioned between the interconnection layer and the second surface, and a first opening is formed in the bottom hard mask layer, so that in the process of forming a third opening, the bottom hard mask layer can play a role of a mask, a photoetching mask is not required to be formed in the first opening, and only a mask layer is formed outside the second opening, so that the process of forming the third opening is avoided, an excessively thick first photoetching mask layer is required to be deposited, correspondingly, the process of needing larger exposure energy to obtain the first photoetching mask layer with patterns is avoided, correspondingly, the service cycle of a machine is shortened, the process cost is reduced, meanwhile, the difficulty of a photoetching process is reduced, the photoetching quality is correspondingly improved, and the forming quality of the openings is improved; in addition, since the photolithographic mask is not required to be formed in the first opening, the limitation of the photolithographic mask thickness to the thickness of the pixel substrate is avoided correspondingly, the thickness of the pixel substrate is conveniently set according to the performance requirement of the photoelectric sensor, and in summary, the embodiment is beneficial to improving the performance of the photoelectric sensor.
In order to solve the technical problems, the embodiment of the invention provides a method for forming a photoelectric sensor, which is characterized in that a top hard mask layer is formed on a first surface, compared with the scheme of directly adopting the first photoetching mask layer for pattern transfer, the method is beneficial to avoiding depositing an excessively thick first photoetching mask layer in the process of forming the patterned top hard mask layer, correspondingly avoiding the adoption of excessive exposure energy, correspondingly, being beneficial to shortening the service period of a machine, reducing the process cost, simultaneously being beneficial to reducing the difficulty of the photoetching process, correspondingly improving the photoetching quality, and being beneficial to improving the forming quality of an opening; the first opening is formed in the bottom hard mask layer, so that the bottom hard mask layer is taken as a mask after the dielectric layer positioned in the first opening is removed in the process of forming the opening, the dielectric layer at the bottom of the first opening is removed without forming a photoetching mask layer additionally, the steps of depositing an excessively thick photoetching mask layer and carrying out secondary exposure are avoided, accordingly, the service cycle of a machine is shortened, the process cost is reduced, and in sum, the performance of the photoelectric sensor is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 9, a schematic structural diagram of an embodiment of the photosensor of the present invention is shown.
As shown in fig. 9, in this embodiment, the photoelectric sensor includes: a pixel substrate 600 including a first surface 601 and a second surface 602 opposite to each other, wherein the pixel substrate 600 includes a photosensitive region 600P and a lead region 600N located at a side of the photosensitive region 600P, and the photosensitive region 600P includes pixel unit regions (not shown) arranged in an array; a dielectric layer 620 located on the second surface 602; an interconnection layer 630 located in the dielectric layer 620 of the lead area 600N, where the interconnection layer 630 is electrically connected to the pixel unit area to be interconnected; a bottom hard mask layer 631 located within the dielectric layer 620, the bottom hard mask layer 631 located between the interconnect layer 630 and the second surface 602, the bottom hard mask layer having a first opening 632 formed therein; a second opening 661 located at one side of the first surface 601 and penetrating the pixel substrate 600 and the dielectric layer 620 on the bottom hard mask layer 631, wherein the bottom dimension of the second opening 661 is larger than the bottom dimension of the first opening 632; a third opening 660 penetrating the dielectric layer at the bottom of the first opening 632 and exposing the interconnection layer 630, wherein the second opening 661, the first opening 632 and the third opening 660 are communicated and form an opening 662; a pad layer 670 is located at the bottom of the opening 662 and is in contact with the interconnect layer 630.
The pixel substrate 600 is used to provide an operation platform for subsequent processing. In this embodiment, the pixel base 600 includes a substrate (not shown). In particular, the material of the substrate may include one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. As one example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.
In this embodiment, the first surface 601 is a back surface of the pixel substrate 600, and the second surface 602 is a front surface of the pixel substrate 600. Specifically, the pixel substrate 600 is a back-illuminated (BSI) pixel wafer, and the first surface 601 of the pixel substrate 600 is a light-receiving surface.
The pixel substrate 600 includes a photosensitive region 600P, and the photosensitive region 600P is configured to receive an optical signal and convert the optical signal into an electrical signal. In this embodiment, the photosensitive area 600P includes an array of pixel unit areas, in which pixel units are formed, and the pixel units are configured to receive optical signals and convert the optical signals into electrical signals.
The lead area 600N is used for wiring and forming leads to make electrical connection between the pixel cell or other device structure and external circuitry.
In this embodiment, an RGB diode 680 is further disposed in the pixel substrate 600, so as to facilitate rectifying the photosensor.
The dielectric layer 620 is used to achieve isolation between the interconnect layer 630 and the bottom hard mask layer 631.
Along the direction in which the second surface 602 points to the dielectric layer 620, the dielectric layer 620 includes a first dielectric layer 621, a second dielectric layer 622, a third dielectric layer 623, and a fourth dielectric layer 624 stacked in order from bottom to top. That is, the first dielectric layer 621 is closest to the second surface 602.
The first dielectric layer 621 is used to achieve isolation between the bottom hard mask layer 631 and the pixel substrate 600.
The second dielectric layer 622 is used to isolate the bottom hard mask layer 631 from the interconnect layer 630.
The third dielectric layer 623 is used to achieve isolation between the bottom hard mask layer 631 and the interconnect layer 630.
The fourth dielectric layer 624 is used to isolate the interconnect layer 630 from other substrates.
The material of the dielectric layer 620 is a dielectric material, for example: one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, and ultra-low-k dielectric material.
The photosensor further includes: a logic substrate or memory chip or sensor chip is bonded to the dielectric layer 620 of the second surface 602. In this embodiment, the logic substrate 645 is used to analyze the electrical signal provided by the pixel substrate 600. Specifically, a logic device for analyzing and processing the electrical signal supplied from the pixel substrate 600 is formed in the logic substrate. In other embodiments, the second substrate may also be a memory chip, a sensor chip, or a carrier substrate.
The interconnection layer 630 is used to realize a circuit connection between the pixel units, and is also used to realize an electrical connection between the pixel units and the pad layer 670, thereby realizing an electrical connection between the pixel units and an external circuit.
The material of the interconnection layer 630 is metal, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.
The bottom hard mask layer 631 serves as a stop position in the process of forming the second opening 661, exposing the top of the bottom hard mask layer 631. In addition, the bottom hard mask layer 631 can play a role of a mask, a photolithography mask is not required to be formed in the first opening 632, and only a mask layer is required to be formed on the outer side of the second opening 661, so that the process of forming the third opening 660 is avoided from depositing an excessively thick photolithography mask layer (not shown), and correspondingly, the process of needing larger exposure energy to obtain the patterned photolithography mask layer is avoided, accordingly, the service period of a machine is shortened, the process cost is reduced, meanwhile, the difficulty of a photolithography process is reduced, the photolithography quality is correspondingly improved, and the formation quality of the opening 662 is improved; in addition, since there is no need to form a photolithography mask in the first opening 632, this accordingly avoids the limitation of the thickness of the photolithography mask on the thickness of the pixel substrate 600, and facilitates setting the thickness of the pixel substrate 600 according to the performance requirement of the photosensor.
In this embodiment, the material of the bottom hard mask layer 631 and the material of the dielectric layer 620 have a higher etching selectivity ratio, so that the material of the bottom hard mask layer 631 is a metal hard mask material, which is favorable for forming an opening, and is used as a mask, and the probability of mistakenly etching the dielectric layer 620 is reduced, so that the dielectric layer 620 is favorable for protection. For example, to improve the etch resistance of the bottom hard mask layer 631, the bottom hard mask layer 631 is a metal nitride material, and the material of the bottom hard mask layer 631 may include one or more of titanium nitride and aluminum nitride. As an embodiment, the material of the bottom hard mask layer 631 is titanium nitride.
In this embodiment, the thickness of the bottom hard mask layer 631 is not too small or too large, if the thickness of the bottom hard mask layer 631 is too small, the effect of the bottom hard mask layer 631 for defining the stop position is easily degraded in the process of forming the second opening 661, and the probability of damaging the dielectric layer 620 is increased in the process of forming the third opening; if the thickness of the bottom hard mask layer 631 is too large, the thickness of the dielectric layer 620 is increased, so that the path of light reaching the optoelectronic element is increased, which is disadvantageous for the RGB diode to absorb light, and for this reason, in this embodiment, the thickness of the bottom hard mask layer 631 is 300 to 500 angstroms.
The first opening 632 is used to define the size of the third opening 660.
The second opening 661 is used for exposing the top of the bottom hard mask layer 631 and the first opening 632.
The third opening 660 is for exposing the interconnect layer 630.
The pad layer 670 is used to make electrical connection between the interconnect layer 630 and an external circuit or other interconnect structure.
It should be added that the pad layer 670 fills the first opening 632 and the third opening 660 and is located at the bottom of the second opening 661.
In this embodiment, the material of the pad layer 670 includes one or more of aluminum, titanium, tungsten, gold, and tin-doped indium oxide. As an example, the material of the pad layer 670 is aluminum. Aluminum has good conductivity and is a material that is easily etched, thereby easily patterning the pad layer 670.
In this embodiment, the photosensor further includes a dielectric layer 638 on the first surface 601 and a protective layer 639 on the dielectric layer 638.
The dielectric layer 638 is used to induce charge and thereby improve the performance of the photosensor.
In this embodiment, the material of the dielectric layer 638 is alumina, and in other embodiments, the material of the dielectric layer may be any one or more of titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.
The protective layer 639 is used to protect the dielectric layer 638.
In this embodiment, the material of the protective layer 639 is silicon oxide, and in other embodiments, the material of the protective layer is silicon nitride.
Correspondingly, the invention further provides a forming method of the photoelectric sensor. Fig. 10 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.
Referring to fig. 10 to 15, a pixel substrate 800 is provided, including a first surface 801 and a second surface 802 opposite to each other, the pixel substrate 800 includes a photosensitive region 800P and a lead region 800N located at a side portion of the photosensitive region 800P, the photosensitive region 800P includes pixel unit regions (not shown) arranged in an array, a dielectric layer 820 is formed on the second surface 802, an interconnection layer 830 and a bottom hard mask layer 831 are formed in the dielectric layer 820 of the lead region 800N, the interconnection layer 830 is electrically connected with the pixel unit regions to be interconnected, a first opening 832 is formed in the bottom hard mask layer 831, the first opening 832 is filled with the dielectric layer 820, and the bottom hard mask layer 831 is located between the interconnection layer 830 and the second surface 802.
The pixel substrate 800 is used to provide an operation platform for subsequent processing. In this embodiment, the pixel base 800 includes a substrate (not shown). In particular, the material of the substrate may include one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. As one example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.
In this embodiment, the first surface 801 is a back surface of the pixel substrate 800, and the second surface 802 is a front surface of the pixel substrate 800. Specifically, the pixel substrate 800 is a back-illuminated (BSI) pixel wafer, and the first surface 801 of the pixel substrate 800 is a light-receiving surface.
The pixel substrate 800 includes a photosensitive region 800P, and the photosensitive region 800P is configured to receive an optical signal and convert the optical signal into an electrical signal. In this embodiment, the photosensitive area 800P includes an array of pixel unit areas, in which pixel units are formed, and the pixel units are configured to receive optical signals and convert the optical signals into electrical signals.
The lead area 800N is used for wiring and forming leads to make electrical connection between the pixel cell or other device structure and external circuitry.
In this embodiment, an RGB diode 880 is further disposed in the pixel substrate 800, so as to facilitate rectifying the photosensor.
The dielectric layer 820 is used to achieve isolation between the interconnect layer 830 and the bottom hard mask layer 831.
The material of the dielectric layer 820 is a dielectric material, for example: one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, and ultra-low-k dielectric material.
The steps of forming the dielectric layer 820, the interconnect layer 830 and the bottom hard mask layer 831 according to this embodiment are described in detail below with reference to fig. 11 to 15.
As shown in fig. 11, a first dielectric layer 821 is formed on the second surface 802.
The first dielectric layer 821 is used to isolate the bottom hard mask layer 831 from the pixel substrate 800.
As shown in fig. 11 and 12, a bottom hard mask layer 831 having a first opening 832 (shown in fig. 12) is formed on the first dielectric layer 821.
The bottom hard mask layer 831 is used to define a stop position during the formation of the second opening 861 during the subsequent opening formation, i.e., the subsequently formed second opening 861 exposes the top of the bottom hard mask layer 831. In addition, after the dielectric layer 820 located in the first opening 832 is removed, the dielectric layer 820 at the bottom of the first opening 832 is removed by using the bottom hard mask layer 831 as a mask, so as to form a third opening, without forming an extra photo mask layer, which avoids the steps of depositing an excessively thick photo mask layer and performing a secondary exposure.
In this embodiment, the material of the bottom hard mask layer 831 has a higher etching selection ratio with the material of the dielectric layer 820, so that the material of the bottom hard mask layer 831 is a metal hard mask material, which is favorable for being used as a mask in the subsequent process of forming an opening, and reduces the probability of mistakenly etching the dielectric layer 820, thereby being favorable for protecting the dielectric layer 820. For example, to improve the etch resistance of the bottom hard mask layer 831, the bottom hard mask layer 831 is a metal nitride material, and the material of the bottom hard mask layer 831 may include one or more of titanium nitride and aluminum nitride. As an embodiment, the material of the bottom hard mask layer 831 is titanium nitride.
In this embodiment, in the step of providing the pixel substrate 800, the thickness of the bottom hard mask layer 831 should not be too small or too large, if the thickness of the bottom hard mask layer 831 is too small, when the second opening is subsequently formed, the probability of being unable to define the stop position is increased, and in the process of forming the third opening, the probability of damaging the dielectric layer 820 is increased; if the thickness of the bottom hard mask layer 831 is too large, the thickness of the dielectric layer 820 is increased, so that the path of light reaching the optoelectronic element is increased, which is disadvantageous for the RGB diode to absorb light, and for this reason, in this embodiment, the thickness of the bottom hard mask layer 831 is 300 to 500 angstroms.
The first opening 832 is used to define the size of a third opening to be formed later.
In this embodiment, the width of the first opening 832 defines the width of the bottom of the pad layer to be formed later.
Specifically, a bottom hard mask material layer 835 and a second photolithographic mask layer (not shown) having a third mask opening (not shown) and a fourth mask opening (not shown) on the bottom hard mask material layer 835 are formed on the first dielectric layer 821, the fourth mask opening defining the size and location of the first opening 832; the pattern of the third mask opening and the four mask openings is transferred into the bottom hard mask material layer 835 using the second photolithographic mask layer as a mask, forming a bottom hard mask layer 831 having a first opening 832.
In this embodiment, a physical vapor deposition (Physical Vapor Deposition, PVD) process is used to rapidly form the bottom hard mask material layer 835.
In this embodiment, a dry etching process is used to form a bottom hard mask layer 831 having a first opening 832.
As shown in fig. 13, a second dielectric layer 822 is formed to cover the first dielectric layer 821 and the bottom hard mask layer 831, and the second dielectric layer 822 is further filled in the first opening 832.
The second dielectric layer 822 is used to isolate the bottom hard mask layer 831 from the subsequently formed interconnect layer 830.
With continued reference to fig. 13, a third dielectric layer 823 is formed on the second dielectric layer 822.
The third dielectric layer 823 is used to realize isolation between the interconnection layers formed later.
As shown in fig. 14, an interconnect layer 830 is formed in the third dielectric layer 823.
The interconnection layer 830 is used for realizing circuit connection between the pixel units, and is also used for realizing electric connection between the pixel units and a subsequently formed pad layer, so as to realize electric connection between the pixel units and an external circuit.
The material of the interconnect layer 830 is metal, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. In this embodiment, the interconnect layer 830 is copper.
With continued reference to fig. 14, a fourth dielectric layer 824 is formed overlying the third dielectric layer 823 and the interconnect layer 830, the first dielectric layer 821, the second dielectric layer 822, the third dielectric layer 823, and the fourth dielectric layer 824 comprising the dielectric layer 820.
The fourth dielectric layer 824 is used to protect the interconnect layer 830, and to isolate the interconnect layer 830 from a subsequently bonded second substrate.
In this embodiment, the first dielectric layer 821, the second dielectric layer 822, the third dielectric layer 823 and the fourth dielectric layer 824 are formed by chemical vapor deposition.
Referring to fig. 15, before forming the patterned top hard mask layer on the first surface 801, the method for forming the photosensor further includes: a second substrate 845 is provided such that a dielectric layer 820 located on the second surface 802 is bonded to the second substrate 845.
The second substrate 845 provides support for subsequent processing on the first surface 801, and also serves a corresponding electrical function when the second substrate 845 is a functional device substrate.
In this embodiment, the second substrate 845 includes: a logic substrate, a memory chip, a sensor chip, or a carrier substrate.
In this embodiment, the second substrate 845 is a Logic Wafer (Logic Wafer) for performing analysis processing on the electrical signal provided by the pixel substrate 800. Specifically, a logic device for analyzing and processing the electrical signal supplied from the pixel substrate 800 is formed in the logic substrate. The second substrate 845 is used for increasing the pixel area, and is also beneficial to shortening the path of light reaching the photoelectric element, reducing the scattering of the light, enabling the light to be more focused, further improving the light sensing capability of the photoelectric sensor in a weak light environment, and reducing system noise and crosstalk.
In this embodiment, the Bonding between the logic substrate 200 and the dielectric layer 820 is implemented by Hybrid Bonding (Fusion Bonding), and in other embodiments, fusion Bonding may be also implemented.
Referring to fig. 16, a dielectric layer 838 and a protective layer 839 overlying the dielectric layer 838 are formed on the first surface 801.
The dielectric layer 838 is used to induce charge and thereby improve the performance of the photosensor.
In this embodiment, the material of the dielectric layer 838 is alumina, and in other embodiments, the material of the dielectric layer may be any one or more of titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.
The protective layer 839 is used to protect the dielectric layer 838 during subsequent removal of the top hard mask layer.
In this embodiment, the material of the protection layer 839 is silicon oxide, and in other embodiments, the material of the protection layer is silicon nitride. In this embodiment, before forming the patterned top dielectric layer 838 on the first surface 801, the method further includes: the first surface 801 of the pixel substrate 800 is thinned.
The thinning process is advantageous in shortening the path of light to the photocell, thereby facilitating the RGB diode to absorb light.
In this embodiment, in order to increase the absorption quantum in the pixel substrate 800, thereby improving the quantum efficiency, the thickness of the pixel substrate 800 is greater than 1um.
Referring to fig. 16 and 17, a patterned top hard mask layer 855 (as shown in fig. 18) is formed on the first surface 801, and a first mask opening (not labeled) is formed in the top hard mask layer 855 and located in the lead region, and a projection of the first opening 832 on the first surface 801 is located within a projection of the first mask opening on the first surface 801.
The top hard mask layer 855 is used as a mask for forming the second openings 861.
The first mask opening is used to define the size of the second opening 861.
In this embodiment, the step of forming the patterned top hard mask layer 855 on the first surface 801 includes: forming a top hard mask material layer 857 on the first surface 801; the top hard mask material layer 857 is patterned, forming a patterned top hard mask layer 855.
The top hard mask material layer 857 is used to form the top hard mask layer 855.
In this embodiment, in the step of forming the patterned top hard mask layer 855 on the first surface 801, the thickness of the top hard mask layer 855 is not too small, and if the thickness of the top hard mask layer 855 is too small, the effect of the top hard mask layer 855 as a mask is easily degraded; if the thickness of the top hard mask layer 855 is too large, the process time for patterning the top hard mask layer 855 is increased, and thus the process cost is increased, and for this reason, in this embodiment, the thickness of the top hard mask layer 855 is 700 to 1000 angstroms.
In this embodiment, a physical vapor deposition process is used to form the top hard mask material layer 857.
In this embodiment, the material of the top hard mask layer 855 has a higher etching selectivity ratio with the material of the pixel substrate 800, so that the material of the top hard mask layer 855 is a metal hard mask material, which is favorable for being used as a mask in the subsequent process of forming an opening, and reduces the probability of mistakenly etching the pixel substrate 800, thereby being favorable for protecting the pixel substrate 800. For example, to improve the etch resistance of the top hard mask layer 855, the top hard mask layer 855 is a metal nitride material, and the material of the top hard mask layer 855 may include one or more of titanium nitride and aluminum nitride. As an embodiment, the material of the top hard mask layer 855 is titanium nitride.
Referring to fig. 17, the step of patterning the top hard mask material layer 857 includes: forming a first photolithographic mask layer 859 having a second mask opening 858 on the top hard mask material layer 857; the pattern of the second mask openings 858 is transferred into the top hard mask material layer 857 using the first photolithographic mask layer 859 as a mask.
The first photolithographic masking layer 859 is used as a mask to pattern the top hard mask material layer 857.
The second mask openings 858 have the same size as the second openings 861 formed later.
In this embodiment, in the step of forming the first photoresist mask layer 859 with the second mask opening 858, compared with the step of etching the protective layer 839, the dielectric layer 838 and the pixel substrate 800 by using the first photoresist mask layer 859 as a mask, only the top hard mask material layer 857 is etched by using the first photoresist mask layer 859 as a mask, so that the thickness of the first photoresist mask layer 859 is smaller, and a larger exposure energy is avoided to obtain the first photoresist mask layer 859 with a pattern, which is beneficial to shortening the service period of a machine and reducing the process cost, and simultaneously, is beneficial to reducing the difficulty of the photolithography process, and correspondingly improving the photolithography quality, thereby being beneficial to improving the formation quality of the second opening 861.
In this embodiment, the thickness of the first photo-etching mask layer 859 is not too small or too large, if the thickness of the first photo-etching mask layer 859 is too small, it is not beneficial to obtain the top hard mask layer 855 with patterns, and if the thickness of the first photo-etching mask layer 859 is too large, larger exposure energy is required to obtain the first photo-etching mask layer 859 with patterns, which is easy to increase the service cycle of the machine and raise the process cost. For this reason, in this embodiment, the thickness of the first photolithography mask layer 859 is 4000 angstroms to 56000 angstroms.
Referring to fig. 18, with the top hard mask layer 857 as a mask, the pixel substrate 800 and the dielectric layer 820 at the bottom of the first mask opening are removed, and an opening 862 is formed through the pixel substrate 800, the bottom hard mask layer 831 and the dielectric layer 820 at the top of the interconnect layer 830.
The opening 862 is used to expose the pixel substrate 800, the bottom hard mask layer 831, and the dielectric layer 820 that are located on top of the interconnect layer 830, thereby facilitating subsequent formation of a pad layer in the opening 862 that is electrically connected to the interconnect layer 830.
In this embodiment, the step of forming the opening 862 through the pixel substrate 800, the bottom hard mask layer 831, and the dielectric layer 820 on top of the interconnect layer 830 includes: removing the pixel substrate 800 and the dielectric layer 820 on the bottom hard mask layer 831 along the first mask opening to form a second opening 861, wherein the second opening 861 exposes the top of the bottom hard mask layer 831 and the dielectric layer 820 in the first opening 832; the second opening 861 exposes the top of the bottom hard mask layer 831 and the dielectric layer 820 in the first opening 832, which is advantageous for removing the dielectric layer 820 in the first opening 832 by using the exposed bottom hard mask layer 831 as a mask.
Specifically, a top opening (not shown) is formed through the pixel substrate 800 on the bottom hard mask layer 831, the top opening exposing the surface of the dielectric layer 820; forming a bottom opening (not shown) of the dielectric layer 820 below the top opening exposing a portion of the top of the bottom hard mask layer 831 facing the second surface 802, the bottom opening and top opening forming the second opening 861
With continued reference to fig. 18, forming an opening 862 through the pixel substrate 800, the bottom hard mask layer 831, and the dielectric layer 820 at the top of the interconnect layer 830 includes removing the dielectric layer 820 within the first opening 832 using the bottom hard mask layer 831 as a mask after forming the second opening 861.
The dielectric layer 820 located within the first opening 832 is removed, thereby facilitating subsequent removal of the dielectric layer 820 located at the bottom of the first opening 832.
With continued reference to fig. 18, the step of forming an opening 862 through the pixel substrate 800, the bottom hard mask layer 831, and the dielectric layer 820 located at the top of the interconnect layer 830 includes removing the dielectric layer 820 located in the first opening 832, and then removing the dielectric layer 820 located at the bottom of the first opening 832 with the bottom hard mask layer 831 as a mask, thereby forming a third opening 860 exposing the interconnect layer 830, where the second opening 861, the first opening 832, and the third opening 860 are communicated and form the opening 862.
The third opening 860 is used to expose the interconnect layer 830, thereby facilitating subsequent formation of a pad layer in the third opening 860 that is electrically connected to the interconnect layer 830.
In this embodiment, in the same etching process, the top hard mask material layer 857, the pixel substrate 800 and the dielectric layer 820 on the bottom hard mask layer 831, the dielectric layer 820 located in the first opening 832, and the dielectric layer 820 at the bottom of the first opening 832 are etched in sequence, so that the openings are formed in the same step, thereby being beneficial to reducing the process flow and saving the process cost.
In this embodiment, the process of patterning the top hard mask material layer 857, removing the pixel substrate 800 and the dielectric layer 820 on the bottom hard mask layer 831 along the mask opening, removing the dielectric layer 820 located in the first opening 832, and removing the dielectric layer 820 at the bottom of the first opening 832 is anisotropic dry etching. The anisotropic dry etching process has high etching profile control, is favorable for precisely controlling the profile shape of the opening, and reduces the probability of causing false etching on the interconnection layer 830 and the pixel substrate 800.
Referring to fig. 19, a pad layer 870 is formed in the opening 862 in contact with the interconnect layer 830.
The pad layer 870 is used to make electrical connection between the interconnect layer 830 and an external circuit or other interconnect structure.
In this embodiment, the pad layer 870 is filled in the first opening 832 and the third opening 860 and is located at the bottom of the second opening 861. In this embodiment, the material of the pad layer 870 includes one or more of aluminum, titanium, tungsten, gold, and tin-doped indium oxide. As an example, the material of pad layer 870 is aluminum. Aluminum has good conductivity and is a material that is easily etched, thereby easily forming pad layer 870 by patterning.
In this embodiment, the step of forming a pad layer 870 in contact with the interconnect layer 830 in the opening 862 includes: forming a layer of pad material (not shown) on the bottom and sidewalls of the opening 862 and the second surface 802; portions of the pad material layer at the second surface 802 and at the bottom of the opening 862 are removed, and the remaining pad material layer at the bottom of the opening 862 is used as a pad layer 870.
Portions of the pad material layer at the second surface 802 and at the bottom of the opening 862 are removed, thereby advantageously reducing the probability of shorting between the pad layers 870. Specifically, a third photo-etching mask layer (not shown) is formed right above the interconnection layer 830, and the third photo-etching mask layer is used as a mask, so that the bonding pad material layer located at the side portion of the third photo-etching mask layer is removed through an anisotropic dry etching process, which is beneficial to improving the formation of the precise control of the profile of the bonding pad layer 870 and reducing the probability of causing the false etching of the dielectric layer 820 and the second surface 802.
Specifically, in this embodiment, when the material of the pad layer 870 is aluminum, the pad material layer is formed by a physical vapor deposition process, and in other embodiments, when the material of the pad layer is tungsten, the pad material layer is formed by a chemical vapor deposition process.
It should be noted that before forming the pad material layer on the bottom and the side walls of the opening 862 and the second surface 802, forming an adhesion layer (not shown) on the bottom and the side walls of the opening 862 and the second surface 802 is generally further included, so that the pad material layer is formed on the adhesion layer to improve the adhesion of the pad material layer.
Accordingly, after forming the pad layer 870, further includes: the exposed adhesion layer of pad layer 870 is removed.
As an example, the material of the adhesion layer is titanium nitride and the material of the top hard mask layer 855 is titanium nitride, so that the exposed bottom hard mask layer 831 of the pad layer 870 is removed at the same time as the exposed adhesion of the pad layer 870 is removed.
In other embodiments, the top hard mask layer may also be left, depending on the material setting of the top hard mask layer.
In this embodiment, the forming method further includes: the top hard mask material layer 857 is removed.
Specifically, since the top hard mask material layer 857 and the bottom hard mask layer 831 are made of the same material, the bottom hard mask layer 831 exposed by the pad layer 870 is removed, and at the same time, the top hard mask material layer 857 is removed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A photoelectric sensor, comprising:
the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area positioned at the side part of the photosensitive area, and the photosensitive area comprises pixel unit areas which are arranged in an array;
a dielectric layer on the second surface;
the interconnection layer is positioned in the dielectric layer of the lead area and is electrically connected with the pixel unit area to be interconnected;
the bottom hard mask layer is positioned in the dielectric layer, is positioned between the interconnection layer and the second surface and is provided with a first opening;
The second opening is positioned on one side of the first surface and penetrates through the pixel substrate and the dielectric layer on the bottom hard mask layer, and the bottom size of the second opening is larger than that of the first opening;
a third opening penetrating the dielectric layer at the bottom of the first opening and exposing the interconnection layer, wherein the second opening, the first opening and the third opening are communicated and form an opening;
and the welding pad layer is positioned at the bottom of the opening and is contacted with the interconnection layer.
2. The photosensor according to claim 1, wherein the photosensor further comprises: and the logic substrate, the memory chip or the sensor chip is bonded on the dielectric layer of the second surface.
3. The photosensor of claim 1 wherein the bottom hard mask layer has a thickness of 300 angstroms to 500 angstroms.
4. The photosensor of claim 1, wherein the material of the bottom hard mask layer is a metal hard mask material.
5. The photosensor of claim 1, wherein the material of the bottom hard mask layer comprises: one or more of titanium nitride and aluminum nitride.
6. The photosensor of claim 1, wherein the second surface is a front surface of the pixel substrate and the first surface is a back surface of the pixel substrate.
7. A method of forming a photoelectric sensor, comprising:
providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite, the pixel substrate comprises a photosensitive area and a lead area positioned at the side part of the photosensitive area, the photosensitive area comprises pixel unit areas which are arranged in an array, a dielectric layer is formed on the second surface, an interconnection layer and a bottom hard mask layer are formed in the dielectric layer of the lead area, the interconnection layer is electrically connected with the pixel unit areas to be interconnected, a first opening is formed in the bottom hard mask layer, the first opening is filled with the dielectric layer, and the bottom hard mask layer is positioned between the interconnection layer and the second surface;
forming a patterned top hard mask layer on the first surface, wherein a first mask opening positioned in the lead area is formed in the top hard mask layer, and the projection of the first opening on the first surface is positioned inside the projection of the first mask opening on the first surface;
removing the pixel substrate and the dielectric layer at the bottom of the first mask opening by taking the top hard mask layer as a mask, and forming an opening penetrating through the pixel substrate, the bottom hard mask layer and the dielectric layer at the top of the interconnection layer;
And forming a pad layer in contact with the interconnection layer in the opening.
8. The method of forming a photosensor of claim 7, where the method of forming a photosensor further comprises, prior to forming a patterned top hard mask layer on the first surface: and providing a second substrate, and bonding the dielectric layer on the second surface with the second substrate.
9. The method of forming a photosensor of claim 8 where the second substrate includes: a logic substrate, a memory chip, a sensor chip, or a carrier substrate.
10. The method of forming a photosensor of claim 7 where forming the dielectric layer, bottom hard mask layer and interconnect layer includes forming a first dielectric layer on the second surface;
forming a bottom hard mask layer with a first opening on the first dielectric layer;
forming a second dielectric layer covering the first dielectric layer and the bottom hard mask layer, wherein the second dielectric layer is also filled in the first opening;
forming a third dielectric layer on the second dielectric layer;
forming an interconnection layer in the third dielectric layer;
And forming a fourth dielectric layer covering the third dielectric layer and the interconnection layer, wherein the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer form a dielectric layer.
11. The method of forming a photosensor of claim 7 where the step of forming a patterned top hard mask layer on the first surface includes: forming a top hard mask material layer on the first surface;
and patterning the top hard mask material layer to form a patterned top hard mask layer.
12. The method of claim 11, wherein the top hard mask material layer, the pixel substrate and the dielectric layer on the bottom hard mask layer, the dielectric layer within the first opening, and the dielectric layer at the bottom of the first opening are etched sequentially in a same etching process.
13. The method of claim 11, wherein the patterning the top hard mask material layer, removing the pixel substrate and the dielectric layer on the bottom hard mask layer along the mask opening, removing the dielectric layer within the first opening, and removing the dielectric layer at the bottom of the first opening are all anisotropic dry etches.
14. The method of forming a photosensor of claim 11, where patterning the top hard mask material layer includes: forming a first photoetching mask layer with a second mask opening on the top hard mask material layer; and transferring the pattern of the second mask opening into the top hard mask material layer by taking the first photoetching mask layer as a mask.
15. The method of forming a photosensor of claim 7, where forming openings through the pixel substrate, bottom hard mask layer and dielectric layer on top of the interconnect layer includes: removing the pixel substrate and the dielectric layer on the bottom hard mask layer along the first mask opening to form a second opening, wherein the second opening exposes the top of the bottom hard mask layer and the dielectric layer in the first opening;
removing the dielectric layer in the first opening after forming the second opening;
and removing the dielectric layer positioned in the first opening, removing the dielectric layer at the bottom of the first opening, forming a third opening exposing the interconnection layer, and communicating the second opening, the first opening and the third opening to form an opening.
16. The method of forming a photosensor of claim 7, further comprising, prior to forming a patterned top hard mask layer on the first surface: and thinning the first surface of the pixel substrate.
17. The method of claim 16, wherein the thinned pixel substrate has a thickness greater than 1um.
18. The method of forming a photosensor of claim 7 where the step of forming a pad layer in contact with the interconnect layer in the opening includes: forming a bonding pad material layer on the bottom and the side wall of the opening and the second surface; and removing part of the bonding pad material layer positioned on the second surface and at the bottom of the opening, and remaining the bonding pad material layer positioned at the bottom of the opening to serve as a bonding pad layer.
19. The method of claim 7, wherein in the step of forming a patterned top hard mask layer on the first surface, the top hard mask layer has a thickness of 700 angstroms to 1000 angstroms.
20. The method of claim 7, wherein the second surface is a front surface of the pixel substrate and the first surface is a back surface of the pixel substrate.
CN202210433912.2A 2022-04-24 2022-04-24 Photoelectric sensor and forming method thereof Pending CN116978972A (en)

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