CN116130469A - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
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- CN116130469A CN116130469A CN202310415893.5A CN202310415893A CN116130469A CN 116130469 A CN116130469 A CN 116130469A CN 202310415893 A CN202310415893 A CN 202310415893A CN 116130469 A CN116130469 A CN 116130469A
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- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
The invention discloses a power semiconductor device, and relates to the field of power semiconductor device packaging; the device includes: the power circuit comprises a topological structure circuit, a power chip, a power terminal and a signal terminal; the topological structure circuit comprises a plurality of lining plate groups connected in parallel; each lining plate group comprises two lining plates connected in parallel; a plurality of power chips are correspondingly arranged on each lining plate; the cathode area on each lining plate group is symmetrical in position, and the anode area is symmetrical in position; the cathode port of the power chip on each lining plate group is connected with a corresponding cathode terminal, the anode port is connected with a corresponding anode terminal, and the control electrode port is connected with a corresponding signal terminal; the signal terminal introduces a driving control signal input from the outside into the power chip; the power terminals are connected with external buses, so that bus current passes through power chips which are connected in parallel on the lining plate group to form a complete conduction loop, and the current directions of adjacent cathode terminals and anode terminals are opposite; the invention can solve the problems of large stray inductance and long control loop.
Description
Technical Field
The invention relates to the field of power semiconductor device packaging, in particular to a power semiconductor device.
Background
The power semiconductor device is a core device for energy conversion and transmission. At present, due to the huge demand of new energy markets and domestic requirements, enterprises such as power semiconductor design, packaging and the like grow up, and the partial blank of the power semiconductor industry in China is filled. However, in the high-end field, especially the application field of high-power semiconductor devices, the application field is still limited by foreign enterprises such as European America.
A power semiconductor chip is typically formed of N cells in parallel, with the power level generally being proportional to the area of the chip. Because the existing chip manufacturing technology cannot directly manufacture a single high-power chip, a multi-chip parallel connection mode is generally adopted to solve the high-power application requirement. The packaging technology of the power semiconductor device has higher requirements on the consistency and reliability of the packaging technology, and the packaging technology is particularly characterized in heat dissipation performance, electrical performance and mechanical performance of the device. The high-power semiconductor device has compact overall structure due to high power density, and in order to reduce design difficulty, the prior proposal is to additionally install a layer of PCB board auxiliary connection packaging structure in the device to lead out the control electrode of the chip, thus not only having long control loop but also having large stray inductance, and having low reliability. Therefore, it is important to provide a power semiconductor device to solve the problems of large stray inductance and long control loop.
Disclosure of Invention
The invention aims to provide a power semiconductor device to solve the problems of large stray inductance and long control loop.
In order to achieve the above object, the present invention provides the following solutions: a power semiconductor device, the device comprising: topology circuit, power chip, power terminal and signal terminal.
The topological structure circuit comprises a plurality of lining plate groups connected in parallel; each lining plate group comprises two lining plates connected in parallel; a plurality of power chips are correspondingly arranged on each lining plate; the cathode regions on each lining plate group are symmetrical in position, and the anode regions on each lining plate group are symmetrical in position.
Each lining board group is correspondingly provided with two power terminals; the power terminals include a cathode terminal and an anode terminal; the cathode region on each lining plate group is connected with a corresponding cathode terminal, and the anode region on each lining plate group is connected with a corresponding anode terminal; the control region of each lining plate group is connected with a corresponding signal terminal; the signal terminal is used for introducing a driving control signal input from the outside into the power chip through the control region.
The power terminals are used for being connected with external buses, so that bus current passes through the power chips which are mutually connected in parallel on the lining plate group to form a complete conduction loop, and the current directions of the adjacent cathode terminals and the anode terminals are opposite.
Optionally, the power chip includes: a cathode port, a control electrode port, and an anode port;
the cathode port is arranged in the cathode region; the anode port is arranged in the anode region; the control electrode port is arranged in the control electrode region.
Optionally, the device further comprises: a substrate; the topological structure circuit is arranged on the substrate; the substrate is used for bearing and supporting the topological structure circuit.
Optionally, the device further comprises: a housing; an accommodating space is formed between the shell and the substrate; the topological structure circuit and the power chip are arranged in the accommodating space.
Optionally, a plurality of groups of through holes are formed in the shell; each set of through holes includes: a first through hole and a second through hole; the first through hole is used for leading out the cathode terminal; the second through hole is used for leading out the anode terminal; the shell is provided with a group of third through holes; the third through hole is used for leading out the signal terminal.
Optionally, the lining plate comprises a first metal layer, an insulating layer and a second metal layer from top to bottom; a solder mask layer is arranged on the first metal layer; and the corresponding power chip is arranged on the first metal layer.
Optionally, the second metal layer is provided with a hole.
Optionally, the material of the insulating layer is aluminum nitride.
Optionally, a plurality of lining plate groups in the topological structure circuit are connected in parallel through bonding wires; two lining plates in each lining plate group are connected in parallel with the power terminal through bonding wires.
Optionally, the cathode region on each lining plate group is connected with the corresponding cathode terminal in an ultrasonic bonding manner, and the anode region on each lining plate group is connected with the corresponding anode terminal in an ultrasonic bonding manner; and the control region on each lining plate group is connected with the corresponding signal terminal in an ultrasonic bonding mode after being interconnected by adopting bonding wires.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects: the invention provides a power semiconductor device, which is characterized in that the positions of cathode areas on each lining plate group are symmetrical, the positions of anode areas on each lining plate group are symmetrical, and bus current is connected with an external bus through a cathode terminal and an anode terminal, so that a complete conduction loop is formed by power chips which are mutually connected in parallel on the lining plate groups, and the current directions of adjacent cathode terminals and anode terminals are opposite, so that the inductance of a generated space electric field can be mutually offset, and the problem of large stray inductance is solved; and because the invention leads out each port on the power chip by adopting the signal terminal and the power terminal, the length of the control loop of the power semiconductor device is shortened, the delay time of the control signal is reduced, and the stray inductance and the parasitic resistance of the control loop can be further reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a power semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a topology circuit according to an embodiment of the present invention.
Symbol description: a lining board-1, a cathode terminal-2, an anode terminal-3, a signal terminal-4, a substrate-5, a shell-6, a control region-7, a cathode region-8 and an anode region-9.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention aims to provide a power semiconductor device to solve the problems of large stray inductance and long control loop.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Example 1
As shown in fig. 1, an embodiment of the present invention provides a power semiconductor device. Wherein the device comprises: topology circuit, power chip, power terminals and signal terminals 4.
The topological structure circuit comprises a plurality of lining plate groups connected in parallel; each lining board group comprises two lining boards 1 which are connected in parallel; a plurality of power chips are correspondingly arranged on each lining board 1. The power chip includes: a cathode port, a control electrode port, and an anode port.
Specifically, as shown in fig. 2, the board 1 in the topology circuit includes: a cathode region 8, a control region 7, and an anode region 9; the cathode region 8 is used for setting a cathode port of the power chip; the anode region 9 is used for setting an anode port of the power chip; the control region 7 is used for setting a control electrode port of the power chip.
The cathode regions 8 on each liner plate group are symmetrical in position, and the anode regions 9 on each liner plate group are symmetrical in position. Each lining plate group is correspondingly provided with two power terminals. Two lining boards 1 of the same lining board group are connected with a power terminal through a bonding wire; the lining plate groups are connected through bonding wires. The parallel connection is to interconnect the same areas of different liners 1 with bonding wires or power terminals.
The power terminals include a cathode terminal 2 and an anode terminal 3. The cathode region 8 on each liner group is connected to the corresponding cathode terminal 2 and the anode region 9 on each liner group is connected to the corresponding anode terminal 3.
The control region 7 of each liner group is connected with a corresponding signal terminal.
Specifically, the cathode region 8 on each lining plate group is connected with the corresponding cathode terminal 2 in an ultrasonic bonding manner, and the anode region 9 on each lining plate group is connected with the corresponding anode terminal 3 in an ultrasonic bonding manner; the control region 7 on each lining board group is connected with the corresponding signal terminal 4 in an ultrasonic bonding mode after being interconnected by adopting bonding wires.
Wherein the lining board 1 comprises a first metal layer, an insulating layer and a second metal layer from top to bottom; a solder mask layer is arranged on the first metal layer; and a corresponding power chip is arranged on the first metal layer. The second metal layer is provided with pores. The insulating layer is made of aluminum nitride.
Specifically, the backing plate 1 is used for heat dissipation and insulation. Two parallel lining boards form a lining board group, and a plurality of lining board groups are connected in parallel to form a circuit topological structure. The lining board 1 is usually a three-layer structure of metal layer-insulating layer-metal layer, and the lining board 1 is provided with an optimally designed pattern. There are usually a cathode region 8, a control region 7 and an anode region 9, the anode region 9 to set the anode of the power chip, the cathode region 8 to set the cathode of the power chip; the anode of the power chip and the cathode of the power chip correspond to the two ends of the switch.
In addition, a plurality of lining plate groups in the topological structure circuit are connected in parallel through bonding wires; the two liners 1 in each liner group are connected in parallel with the power terminals by bonding wires. The bonding wire can be made of metal with conductivity such as gold, silver, copper, aluminum and the like so as to form a preset circuit topology, namely a topological structure circuit and realize related functions. The topology circuit is not limited to 4 liners 1 in parallel or 6 liners 1 in parallel. The greater the number of parallel connection of the substrate plates 1, the higher the power class of the resulting power semiconductor device.
The signal terminal 4 is used for introducing a driving control signal input from the outside into the power chip through the control terminal port.
Specifically, the corresponding gate port provided on the control region 7 on the substrate 1 is led out of the device through the signal terminal 4. Compared with the prior art, the ultrasonic bonding method has the advantages that the signal terminal 4 is directly welded to the control region 7 on the lining plate 1, the control loop length is greatly shortened, the stray inductance and parasitic resistance of the control loop are effectively reduced, and the delay time of control signals is also reduced.
The power terminals are used for being connected with external buses, so that bus current forms a complete conduction loop through power chips which are mutually connected in parallel on the lining plate group, and the current directions of the adjacent cathode terminals 2 and the adjacent anode terminals 3 are opposite.
As an alternative embodiment, the device further comprises: a substrate 5; a topological structure circuit is arranged on the substrate 5; the substrate 5 is used to carry support topology circuitry.
In one embodiment, the device further comprises: a housing 6; an accommodating space is formed between the housing 6 and the substrate 5; a topological structure circuit and a power chip are arranged in the accommodating space. A plurality of groups of through holes are formed in the shell 6; each set of through holes includes: a first through hole and a second through hole; the first through hole is used for leading out the cathode terminal 2; the second through hole is used for leading out the anode terminal 3; the housing 6 is provided with a set of third through holes for leading out the signal terminals 4.
The housing 6 is used for support and insulation. The shell 6 and the substrate 5 are combined to form a certain accommodating space, and the accommodating space can comprise a lining plate 1, a power chip, a power terminal, a signal terminal 4, a bonding wire and a filling material. The filler is typically filled with an epoxy resin. The filler is used for protecting the power chip to improve the internal insulation level, and can be injected into the post-curing through the filling hole at the top of the shell 6.
Wherein the base plate 5 and the housing 6 are fastened together with bolts and nuts injection molded into the housing 6. The housing 6 needs insulation and sealing for acid, alkali, moisture, oxidation, etc.
In addition, the substrate 5 also has a heat dissipation effect. The substrate 5 is the main heat dissipation part of the power semiconductor device of the present invention, and has a certain warpage to provide better heat dissipation performance.
The heat conduction performance of the base plate 5 is far higher than that of the heat conduction auxiliary materials filled in the gap between the base plate 5 and the radiator. When the periphery of the device is fastened on the radiator by bolts, if the substrate 5 has a certain warpage, for example, the bottom is convex, the substrate 5 is stretched, the warpage is reduced, and the substrate is closer to a plane, so that the combination gap can be reduced, and the heat dissipation performance is improved.
Positioning holes and fixing holes are formed in two sides of the base plate 5, the base plate 5 is provided with the lining plate 1, and the base plate 5 is combined with the back surface of the lining plate 1 through welding flux. The fixing holes are used for fastening the base plate 5 and the housing 6, and the positioning holes are used for fastening the device and the heat sink.
When the power terminal is connected with an external bus, a nut is placed in a nut hole at the top of the shell 6, so that the power terminal and the external bus are assembled conveniently, and then the signal terminal 4 and the power terminal are bent to complete packaging, so that the power semiconductor device is obtained.
The design of the lining plate provided by the embodiment of the invention has the following five beneficial effects.
1. Aluminum nitride is used as an insulating layer of the lining plate, so that the heat dissipation performance, the bending resistance and the product reliability of the product are improved.
2. The lining plate can effectively disperse the heat source and prevent local overheating. Because the anode of the power chip needs to be welded in the anode area, the power chip is a heat source, and the power chip needs to be distributed as uniformly as possible in order to avoid the heat source from concentrating to cause local overheating, so that the heat source is dispersed, the heat distribution range is enlarged, and the heat dissipation efficiency is improved.
3. The anode areas and the cathode areas are symmetrically distributed on the two lining plates in each lining plate group, so that the anode ports of the power chips are symmetrically distributed, the cathode ports of the power chips are symmetrically distributed, finally bus current passes through the power chips which are mutually connected in parallel on the lining plate groups to form a complete conduction loop, and the current directions of the adjacent cathode terminals and the anode terminals are opposite, so that the space electric fields generated by the wires are mutually offset, and the generation of stray inductance on the bus is greatly inhibited.
Due to the magnetic effect of the current, the energized wires generate a concentric magnetic field in space centered about the direction of the current, which can be confirmed by ampere's law. The current direction in the device is from the anode region 9 to the cathode region 8, in order to reduce electromagnetic interference, the power chip arranged on each lining plate group is designed into two conduction loops with opposite current directions, and then magnetic fields in the space are mutually counteracted, so that the influence of stray inductance is reduced. The symmetrical distribution of the anode ports of the power chip is the same as the principle that the current direction of the power terminals is opposite to counteract stray inductances.
4. The second metal layer of the lining plate is provided with holes for releasing stress, so that thermal stress damages such as material fatigue damage, cracks and the like caused by the difference of thermal expansion coefficients of different materials can be effectively relieved, and the service life is prolonged.
5. The first metal layer of the lining plate is provided with the solder mask layer, and the power chip can be effectively prevented from drifting on molten solder through positioning of the solder mask layer.
According to the invention, the power terminals are welded to the cathode region, the anode region and the control region of the lining plate in an ultrasonic bonding mode, so that the bus resistivity is effectively reduced, the welding quality is stable, and the reliability of the product is ensured.
The stacked arrangement of the cathode terminal 2 and the anode terminal 3 counteracts the inductance generated by the opposite currents, and reduces the stray inductance on the bus bar.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present invention and the core ideas thereof; also, it is within the scope of the present invention to be modified by those of ordinary skill in the art in light of the present teachings. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (10)
1. A power semiconductor device, the device comprising: the power circuit comprises a topological structure circuit, a power chip, a power terminal and a signal terminal;
the topological structure circuit comprises a plurality of lining plate groups connected in parallel;
each lining plate group comprises two lining plates connected in parallel; a plurality of power chips are correspondingly arranged on each lining plate; the positions of the cathode areas on each lining plate group are symmetrical, and the positions of the anode areas on each lining plate group are symmetrical;
each lining board group is correspondingly provided with two power terminals;
the power terminals include a cathode terminal and an anode terminal; the cathode region on each lining plate group is connected with a corresponding cathode terminal, and the anode region on each lining plate group is connected with a corresponding anode terminal;
the control region of each lining plate group is connected with a corresponding signal terminal;
the signal terminal is used for introducing a driving control signal input from the outside into the power chip through the control region;
the power terminals are used for being connected with external buses, so that bus current passes through the power chips which are mutually connected in parallel on the lining plate group to form a complete conduction loop, and the current directions of the adjacent cathode terminals and the anode terminals are opposite.
2. The power semiconductor device of claim 1, wherein the power chip comprises: a cathode port, a control electrode port, and an anode port;
the cathode port is arranged in the cathode region; the anode port is arranged in the anode region; the control electrode port is arranged in the control electrode region.
3. The power semiconductor device of claim 1, wherein the device further comprises: a substrate;
the topological structure circuit is arranged on the substrate; the substrate is used for bearing and supporting the topological structure circuit.
4. A power semiconductor device according to claim 3, characterized in that the device further comprises: a housing;
an accommodating space is formed between the shell and the substrate; the topological structure circuit and the power chip are arranged in the accommodating space.
5. The power semiconductor device of claim 4, wherein a plurality of sets of through holes are formed in the housing; each set of through holes includes: a first through hole and a second through hole; the first through hole is used for leading out the cathode terminal; the second through hole is used for leading out the anode terminal; the shell is provided with a group of third through holes; the third through hole is used for leading out the signal terminal.
6. The power semiconductor device of claim 1, wherein the liner comprises a first metal layer, an insulating layer, and a second metal layer from top to bottom; a solder mask layer is arranged on the first metal layer; and the corresponding power chip is arranged on the first metal layer.
7. The power semiconductor device of claim 6, wherein the second metal layer is apertured.
8. The power semiconductor device of claim 6, wherein the insulating layer is made of aluminum nitride.
9. The power semiconductor device of claim 1, wherein a plurality of liner groups in the topology circuit are connected in parallel by bond wires; two lining plates in each lining plate group are connected in parallel with the power terminal through bonding wires.
10. The power semiconductor device of claim 1, wherein the cathode region on each of the liner groups is ultrasonically bonded to the corresponding cathode terminal, and the anode region on each of the liner groups is ultrasonically bonded to the corresponding anode terminal; and the control region on each lining plate group is connected with the corresponding signal terminal in an ultrasonic bonding mode after being interconnected by adopting bonding wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310415893.5A CN116130469A (en) | 2023-04-19 | 2023-04-19 | Power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310415893.5A CN116130469A (en) | 2023-04-19 | 2023-04-19 | Power semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116130469A true CN116130469A (en) | 2023-05-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310415893.5A Pending CN116130469A (en) | 2023-04-19 | 2023-04-19 | Power semiconductor device |
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| CN (1) | CN116130469A (en) |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| JPH1084059A (en) * | 1996-09-09 | 1998-03-31 | Toshiba Corp | Silicon nitride circuit board |
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Application publication date: 20230516 |