CN116068360A

CN116068360A - Dynamic parameter test system

Info

Publication number: CN116068360A
Application number: CN202310292873.3A
Authority: CN
Inventors: 何嘉辉; 何家镖; 陈希辰; 周婉欣
Original assignee: Foshan Linkage Technology Co ltd
Current assignee: Foshan Linkage Technology Co ltd
Priority date: 2023-03-24
Filing date: 2023-03-24
Publication date: 2023-05-05
Anticipated expiration: 2043-03-24
Also published as: CN116068360B

Abstract

The invention provides a dynamic parameter testing system, which comprises a testing machine, an oscilloscope, a semiconductor device to be tested and a grid near-end driving plate, wherein the testing machine is respectively and electrically connected with the oscilloscope and the grid near-end driving plate and is used for providing a trigger signal for level conversion for the oscilloscope, and is also used for forming a large-current loop with the semiconductor device to be tested through the grid near-end driving plate, the grid near-end driving plate is fixed near the semiconductor device to be tested and is used for driving the semiconductor device to be tested to be turned on and off, and the oscilloscope is used for testing the dynamic parameters of the semiconductor device to be tested. According to the invention, the gate near-end driving plate is additionally arranged and is arranged near the semiconductor device to be tested, so that the length between the gate driving loop and the semiconductor device to be tested is shortened, the parasitic parameters of the gate driving loop are reduced, the measuring result and the measuring waveform are optimized, the measuring data are more accurate, and the measuring result is more reliable.

Description

Dynamic parameter test system

Technical Field

The invention relates to the field of testing, in particular to a dynamic parameter testing system.

Background

The third generation semiconductor material devices on the market at present, such as silicon carbide material devices, have too high switching speeds (i.e. di/dt current rising speed and dv/dt voltage rising speed), so that parasitic parameters (such as parasitic inductance) in a test circuit of the third generation semiconductor material devices can influence a test result, and in severe cases, a ringing phenomenon is easily caused on a test waveform, so that test data is unstable, for example, the larger the stray inductance of a gate driving part is, the more unstable a gate voltage oscillation and a test system are caused, and thus test result deviation is caused.

At present, a mature vertical sorting tester is provided, because the testing contact part of the third-generation semiconductor material device is a testing claw, the tester or the tester can only be connected to the tail end of the testing claw through a testing wire with a certain length, meanwhile, the driving of a grid is arranged in the tester, the parasitic inductance of the grid loop is increased due to a long grid loop driving wire, so that a voltage oscillation and testing system is unstable, and the third-generation semiconductor material device is damaged when the voltage oscillation and testing system is serious, so that the testing result is influenced.

Disclosure of Invention

The invention aims to provide a dynamic parameter test system which can reduce parasitic parameters of a grid loop and optimize test results and test waveforms.

In order to solve the above problems, the present invention provides a dynamic parameter testing system, which includes a testing machine, an oscilloscope, a semiconductor device to be tested, and a gate near-end driving board, wherein the testing machine is electrically connected with the oscilloscope and the gate near-end driving board, and is used for providing a trigger signal for level conversion to the oscilloscope, and is also used for forming a high-current loop with the semiconductor device to be tested through the gate near-end driving board, the gate near-end driving board is fixed near the semiconductor device to be tested, and is used for driving the semiconductor device to be tested to be turned on and off, and the oscilloscope is used for testing dynamic parameters of the semiconductor device to be tested.

Optionally, the test machine is provided with a CE external port, a power external port, a gate driving output port, an ICE output port and a trigger signal output port, wherein the CE external port, the power external port and the gate driving output port are all electrically connected with the gate near-end driving board; the ICE output port and the trigger signal output port are both communicated with the oscilloscope and are used for providing trigger signals for the oscilloscope.

Further, the gate near-end driving plate includes a first pad, a second pad, a third pad and a fourth pad, the gate near-end driving plate has a first test port, a second test port and a third test port, the first pad is connected with the first test port, the second pad is connected with the second test port, the third pad is connected with the third test port, and the fourth pad is connected with the ground of the gate near-end driving plate.

Further, the semiconductor device to be tested includes a first port, a second port and a third port, the first port is connected to the fourth pad, the second port is connected to the second pad, and the third port is connected to the first pad and the third pad.

Further, the gate near-end driving board comprises a gate driving chip device, a power input terminal, a gate driving input terminal, a first capacitor bank, a second capacitor bank, a first diode, a second diode, a first resistor and a second resistor, the gate driving chip device comprises an input end, an output end, a positive power end and a negative power end, and the power input terminal is provided with a first input port, a second input port and a third input port;

the power input terminal is connected with the power external port, the grid driving input terminal is connected with the grid driving output port, and the first input port is simultaneously connected with one end of the first capacitor bank and the positive power end of the grid driving chip device; the ground of the grid near-end driving plate is simultaneously connected with the second input port, the other end of the first capacitor group, one end of the second capacitor group, the input end, the grid driving input terminal and the fourth bonding pad; the third input port is connected with the other end of the second capacitor group and the negative power supply end; the positive pole of first diode with the negative pole of second diode is all connected the output, the negative pole of first diode is connected the one end of first resistance, the positive pole of second diode is connected the one end of second resistance, the other end of first resistance with the other end of second resistance is all connected first pad.

Further, the oscilloscope comprises a first connecting end, a second connecting end, a third connecting end and a fourth connecting end, wherein the second connecting end is connected with the second test port, the first connecting end is connected with the third test port, the third connecting end is connected with the ICE output port, and the fourth connecting end is connected with the trigger signal output port and is used for receiving a trigger signal provided by the test machine.

Further, the semiconductor device to be tested and the grid near-end driving plate are relatively fixed on two sides of the connecting part, and the test machine is connected to the connecting part through twisted pairs.

Further, the connecting component comprises a limiting part and a plurality of testing claws, the limiting part is provided with a plurality of limiting grooves, one testing claw is fixed in each limiting groove through a screw, the limiting part is fixed on one side of the grid near-end driving plate, and the testing claws are fixedly arranged on the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad.

Further, a plurality of the test claw is CV preforming, CI preforming, BV preforming, BI preforming, EI preforming and EV preforming respectively, EI preforming, BI preforming and CI preforming are all followed the width direction of test claw is parallel and the interval sets up, EV preforming, BV preforming and CV preforming are all followed the width direction of test claw is parallel and the interval sets up, EI preforming sets up EV preforming below, BI preforming sets up in BV preforming below, CI preforming sets up CV preforming below.

Further, each of the test fingers has a first end and a second end,

the first end of the CI pressing piece is connected with the CE external port through a twisted pair, the first end of the CV pressing piece is welded on the second bonding pad, and the second end of the CI pressing piece and the second end of the CV pressing piece are in pressure equalizing connection on the first port;

the first end of the BI pressing sheet is welded on the first bonding pad, the first end of the BV pressing sheet is welded on the third bonding pad, and the second end of the BI pressing sheet and the second end of the BV pressing sheet are in pressure-equalizing connection on the second port;

the first end of the EI pressing sheet is connected with the CE external port through a twisted pair, the first end of the EV pressing sheet is welded on the fourth bonding pad, and the second end of the EI pressing sheet and the second end of the EV pressing sheet are in pressure-equalizing connection on the third port.

Further, the CE external port has an EI terminal, a CI terminal and an output port, the first end of the CI compression sheet is connected to the CI terminal through a twisted pair and the output port, and the first end of the EI compression sheet is connected to the EI terminal through a twisted pair and the output port.

Compared with the prior art, the invention has the following beneficial effects:

the invention provides a dynamic parameter testing system which comprises a testing machine table, an oscilloscope, a semiconductor device to be tested and a grid near-end driving plate, wherein the testing machine table is electrically connected with the oscilloscope and the grid near-end driving plate respectively and is used for providing a trigger signal for level conversion for the oscilloscope, the dynamic parameter testing system is also used for forming a large current loop with the semiconductor device to be tested through the grid near-end driving plate, the grid near-end driving plate is fixed near the semiconductor device to be tested and is used for driving the semiconductor device to be tested to be turned on and off, and the oscilloscope is used for testing dynamic parameters of the semiconductor device to be tested. According to the invention, the gate near-end driving plate is additionally arranged and is arranged near the semiconductor device to be tested, so that the length between the gate driving loop and the semiconductor device to be tested is shortened, the parasitic parameters of the gate driving loop are reduced, the measuring result and the measuring waveform are optimized, the measuring data are more accurate, and the measuring result is more reliable.

Drawings

FIG. 1 is a schematic diagram of a dynamic parameter testing system according to an embodiment of the present invention;

fig. 2-fig. 4 are schematic perspective views illustrating a connection between a semiconductor device to be tested and a gate near-end driving board according to an embodiment of the present invention;

FIG. 5a is a simulation diagram of test results of an existing dynamic parameter test system using LTspice software;

FIG. 5b is a simulation diagram of a test result of a dynamic parameter test system according to an embodiment of the present invention using LTspice software.

Reference numerals illustrate:

100-testing a machine; 110-a power supply circuit section; 120-a control circuit section; a 111-CE external port; 121-a power external port; 122-gate drive output port; 123-ICE output port; 124-a trigger signal output port; 200-gate proximal drive plate; 211-gate drive chip device; 212-a power input terminal; 213-gate drive input terminals; 214-a first capacitor bank; 215-a second capacitor bank; 300-oscilloscopes; 310-fourth connection; 400-connecting part; 410-a limit part; 421-CV tabletting; tabletting 422-CI; 423-BV tabletting; 424-BI tabletting; 425-EV tabletting; tabletting 426-EI; DUT-semiconductor device under test; d1—a first port; d2—a second port; d3—third port.

Detailed Description

A dynamic parameter testing system of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.

In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.

Fig. 1 is a schematic diagram of a dynamic parameter testing system according to the present embodiment. As shown in fig. 1, the present embodiment provides a dynamic parameter testing system based on a third generation semiconductor device (e.g., a silicon carbide material device) to perform dynamic parameter testing on a semiconductor device DUT to be tested. The dynamic parameter test system meets JEDEC standards. The semiconductor device DUT to be tested comprises a plurality of NPN triodes distributed in an array, the semiconductor device DUT to be tested comprises a first port D1, a second port D2 and a third port D3, an E pole of the NPN triode corresponds to the first port D1, a C pole of the NPN triode corresponds to the second port D2, and a B pole of the NPN triode corresponds to the third port D3.

The dynamic parameter test system comprises a test machine 100, an oscilloscope 300, a semiconductor device DUT to be tested and a grid near-end driving board 200, wherein the test machine 100 is respectively and electrically connected with the oscilloscope 300 and the grid near-end driving board 200 and is used for providing a trigger signal for level conversion for the oscilloscope 300, and is also used for forming a high-current loop with the semiconductor device DUT to be tested through the grid near-end driving board 200, the semiconductor device DUT to be tested is fixed near the grid near-end driving board 200, the grid near-end driving board 200 is used for driving the semiconductor device DUT to be tested to be turned on and off, and the oscilloscope 300 is used for testing dynamic parameters of the semiconductor device DUT to be tested. The test bench 100 may be a vertical sorting tester, and in this embodiment, the test bench is a switching time tester.

The test board 100 includes a power circuit portion 110 and a control circuit portion 120 that are connected to each other, and the test board 100 has a plurality of external ports, which are a CE external port 111, a power external port 121, a gate driving output port 122, an ICE output port 123, and a trigger signal output port 124, respectively. The CE external port 111 has an EI sub-end, a CI sub-end, and an output port. The power external port 121, the gate driving output port 122, and the trigger signal output port 124 are all electrically connected to the control circuit portion 120.

The POWER circuit part 110 comprises a first capacitor C1, a second capacitor C2, a first inductance L, a freewheeling diode D and a current sensor ICE, wherein the positive end of the first capacitor C1, one end of the second capacitor C2, one end of the first inductance L and the negative electrode of the freewheeling diode D are all connected with a POWER supply POWER; the positive electrode of the freewheel diode D and the other end of the first inductor L are connected with the CI terminal; the negative end of the first capacitor C1 and the other end of the second capacitor C2 are both connected to the ground PGND of the test bench 100, meanwhile, the EI sub-end is connected to the ground PGND of the test bench 100 through a wire, the wire is inserted into the current sensor ICE, the current sensor ICE has two output ends, and the two output ends are both connected to the ICE output port 123. The first inductor L is an adjustable inductive load.

The control circuit portion 120 includes an ADC analog-to-digital conversion circuit and a DAC digital-to-analog conversion circuit (not shown in the figure), and is configured to provide a measurement driving signal, an oscilloscope trigger signal, and the like for parameter setting, on-off state setting of each relay, high-voltage output circuit setting, and the like of the DAC digital-to-analog conversion circuit, and to provide the trigger signal to the oscilloscope 300 according to a specific test timing.

The oscilloscope 300 includes a first connection end CH1, a second connection end CH2, a third connection end CH3, and a fourth connection end 310, where the first connection end CH1 and the second connection end CH2 are electrically connected to the gate proximal driving board 200, the third connection end CH3 is connected to the ICE output port 123, and the fourth connection end 310 is electrically connected to the trigger signal output port 124 and is used for receiving a trigger signal provided by the test bench 100. The oscilloscope 300 is a high bandwidth digital oscilloscope.

As shown in fig. 2, referring to fig. 1, the gate near-end driving board 200 includes a gate driving chip device 211, a power input terminal 212, a gate driving input terminal 213, a first capacitor bank 214, a second capacitor bank 215, a first diode DP, a second diode DN, a first resistor RP and a second resistor RN. The gate near-end driving board 200 has a first test port BI, a second test port CV, and a third test port BV. The gate driving chip device 211 is, for example, an operational amplifier, and includes an input terminal IN, an output terminal OUT, a positive power supply terminal v+ and a negative power supply terminal V-, and the first capacitor group 214 and the second capacitor group 215 are each formed by connecting a polarity capacitor and a common capacitor IN parallel.

The gate driving chip device 211 is used for driving the semiconductor device DUT to be tested to be turned on and turned off; the first diode DP, the second diode DN, the first resistor RP and the second resistor RN are all used for adjusting the opening and closing speeds of the semiconductor device DUT to be tested; the first capacitor bank 214 and the second capacitor bank 215 are used to bypass the decoupling effect.

The gate near-end driving board 200 further includes a first pad connected to the first test port BI, a second pad connected to the second test port CV, a third pad connected to the third test port BV, and a fourth pad connected to the first port D1, where the first pad and the third pad are both connected to the third port D3, and the second pad is connected to the second port D2.

The power input terminal 212 is connected to the external power port 121, the gate driving input terminal 213 is connected to the gate driving output port 122, the power input terminal 212 has a first input port 1, a second input port 2 and a third input port 3, and the first input port 1 is connected to one end of the first capacitor bank 214 and the positive power supply end v+ of the gate driving chip device 211 at the same time; the ground VG-GND of the gate near-end driving plate 200 is simultaneously connected to the second input port 2, the other end of the first capacitor bank 214, one end of the second capacitor bank 215, the input terminal IN, the gate driving input terminal 213 and the fourth pad; the third input port 3 is connected to the other end of the second capacitor bank 215 and the negative power supply terminal V-; the positive pole of first diode DP with the negative pole of second diode DN is all connected output OUT, the negative pole of first diode DP is connected the one end of first resistance RP, the positive pole of second diode DN is connected the one end of second resistance RN, the other end of first resistance RP with the other end of second resistance RN is all connected first bonding pad, second test port CV connects the second bonding pad is still through the connection the output port intercommunication CI child end of CE external port 111 simultaneously. The first port D1 communicates with the EI sub-end through an output port connected to the CE external port 111.

The second test port CV is connected to the second connection terminal CH2 of the oscilloscope 300, so as to test the waveform of the C-stage voltage signal of the semiconductor device DUT to be tested; the third test port BV is connected to the first connection end CH1 of the oscilloscope to test waveforms of the B-stage voltage signals of the semiconductor device under test DUT.

Fig. 2 to fig. 4 are schematic perspective views of a connection between a semiconductor device to be tested and a gate near-end driving board according to the present embodiment. As shown in fig. 2 to fig. 4, the dynamic parameter testing system further includes a connection component 400, the DUT and the gate near-end driving board 200 are relatively fixed on two sides of the connection component 400, the test machine 100 is connected to the connection component 400 through twisted pair wires, so that the distance between the gate driving chip device 211 and the DUT is short, so as to shorten the length between the DUT and the gate near-end driving board 200 as much as possible, reduce the parasitic parameters of the gate loop of the DUT, optimize the test result and the test waveform of the dynamic parameter testing system, greatly improve the accuracy of the test data of the dynamic parameters (such as the switching time parameter), provide reliable measurement results for customers, and pave the way for popularization and application.

The connection part 400 includes a limiting part 410 and a plurality of test claws, the limiting part 410 is fixed at one side of the gate proximal driving plate 200, the test claws are fixedly disposed at a plurality of bonding pads (i.e., a first bonding pad, a second bonding pad, a third bonding pad and a fourth bonding pad) of the limiting part 410, and preferably, the test claws are fixed on the limiting part 410 by screws. In detail, the limiting part 410 has a plurality of limiting grooves, and one of the test claws is fixed in each of the limiting grooves by a screw.

A plurality of test claws are CV preforming 421, CI preforming 422, BV preforming 423, BI preforming 424, EI preforming 426 and EV preforming 425 respectively, a plurality of the test claws are rectangular form, EI preforming 426, BI preforming 424 and CI preforming 422 are all followed the width direction parallel and the interval setting of test claw, EV preforming 425, BV preforming 423 and CV preforming 421 are all followed the width direction parallel and the interval setting of test claw, EI preforming 426 sets up EV preforming 425 below, BI preforming 424 sets up in BV preforming 423 below, CI preforming 422 sets up in CV preforming 421 below.

Each test claw has a first end and a second end, the first end of each test claw is welded on the gate near-end driving board 200, the limit part 410 is arranged close to the first end, the gate near-end driving board 200 is a light and small PCBA board due to fewer parts on the gate near-end driving board 200, the test action of the test claw is not affected, and the length between the gate driving circuit and the semiconductor device DUT to be tested is shortened as much as possible due to the arrangement of the gate driving chip device 211 close to the limit part, the parasitic parameters of the gate circuit of the semiconductor device DUT to be tested are reduced, the test result and the test waveform of the dynamic parameter test system are optimized, and the accuracy of the test data of the dynamic parameters (such as the switching time parameters) is greatly improved.

All second ends of the test claws are bent towards the direction perpendicular to the length direction of the test claws, and all second ends are bent on the same side. All the second ends are respectively pressed on a first port D1, a second port D2 and a third port D3 of the semiconductor device DUT to be tested, in detail, a first end of the CI pressing sheet 422 is connected with a CI terminal of the CE external port 111 through a twisted pair, a first end of the CV pressing sheet 421 is welded on the second bonding pad, and a second end of the CI pressing sheet 422 and a second end of the CV pressing sheet 421 are pressure-welded on the first port D1; a first end of the BI pin 424 is welded to the first pad, a first end of the BV pin 423 is welded to the third pad, and a second end of the BI pin 424 and a second end of the BV pin 423 are pressure-bonded to the second port D2; the first end of the EI tabletting 426 is connected with the EI terminal of the CE external port 111 through a twisted pair, the first end of the EV tabletting 425 is welded on the fourth bonding pad, and the second end of the EI tabletting 426 and the second end of the EV tabletting 425 are pressure-welded on the third port D3.

As shown in fig. 5a, under the condition that other parameters are unchanged, LTspice software is used to simulate that the values of parasitic inductances L1 and L2 in the gate driving loop corresponding to the existing dynamic parameter testing system are 100nH. As shown in fig. 5b, under the condition that other parameters are unchanged, LTspice software is used to simulate 10nH of parasitic inductances L1 and L2 in the gate driving loop corresponding to the dynamic parameter testing system provided by the embodiment. Therefore, the dynamic parameter test system provided by the embodiment can reduce parasitic inductance of the gate driving loop (namely, from 100nH to 10 nH), reduce ringing phenomenon of driving waveforms, optimize test waveforms, and enable test data and test results to be more accurate.

In summary, the present invention provides a dynamic parameter testing system, in the application of a vertical sorting tester with a test claw, a gate near-end driving plate is added, and the gate near-end driving plate is placed near a limit portion of the test claw, so that the length between a gate driving loop and a semiconductor device to be tested is shortened, parasitic parameters of the gate driving loop are reduced, and a measurement result and a measurement waveform are optimized, so that test data is more accurate, and the measurement result is more reliable.

Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.

It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. The dynamic parameter testing system is characterized by comprising a testing machine, an oscilloscope, a semiconductor device to be tested and a grid near-end driving plate, wherein the testing machine is respectively and electrically connected with the oscilloscope and the grid near-end driving plate and is used for providing a trigger signal for level conversion for the oscilloscope, and is also used for forming a large-current loop with the semiconductor device to be tested through the grid near-end driving plate, the grid near-end driving plate is fixed near the semiconductor device to be tested and is used for driving the semiconductor device to be tested to be turned on and off, and the oscilloscope is used for testing dynamic parameters of the semiconductor device to be tested.

2. The dynamic parameter testing system of claim 1, wherein the testing machine has a CE external port, a power external port, a gate drive output port, an ICE output port, and a trigger signal output port, all of which are electrically connected to the gate near end drive board; the ICE output port and the trigger signal output port are both communicated with the oscilloscope and are used for providing trigger signals for the oscilloscope.

3. The dynamic parametric test system of claim 2, wherein the gate near-end drive plate comprises a first pad, a second pad, a third pad, and a fourth pad, the gate near-end drive plate having a first test port, a second test port, and a third test port, the first pad being connected to the first test port, the second pad being connected to the second test port, the third pad being connected to the third test port, the fourth pad being connected to ground of the gate near-end drive plate.

4. The dynamic parameter testing system of claim 3, wherein the semiconductor device under test comprises a first port, a second port, and a third port, the first port being coupled to the fourth pad, the second port being coupled to the second pad, the third port being coupled to the first pad and the third pad.

5. The dynamic parameter testing system of claim 3, wherein the gate near-end driver board comprises a gate driver chip device, a power input terminal, a gate driver input terminal, a first capacitor bank, a second capacitor bank, a first diode, a second diode, a first resistor, and a second resistor, the gate driver chip device comprising an input terminal, an output terminal, a positive power terminal, and a negative power terminal, the power input terminal having a first input port, a second input port, and a third input port;

6. The dynamic parameter testing system of claim 5, wherein the oscilloscope comprises a first connection terminal, a second connection terminal, a third connection terminal, and a fourth connection terminal, wherein the second connection terminal is connected to the second test port, the first connection terminal is connected to the third test port, the third connection terminal is connected to the ICE output port, and the fourth connection terminal is connected to the trigger signal output port and is configured to receive a trigger signal provided by the test station.

7. The dynamic parameter testing system of claim 4, further comprising a connection member, wherein the semiconductor device under test and the gate proximal drive board are relatively fixed on both sides of the connection member, and wherein the test machine is connected to the connection member by twisted pair wires.

8. The dynamic parameter testing system of claim 7, wherein the connection member comprises a limiting portion and a plurality of test claws, the limiting portion having a plurality of limiting grooves, one of the test claws being fixed in each of the limiting grooves by a screw, and the limiting portion being fixed on one side of the gate proximal driving plate, the test claws being fixedly disposed on the first pad, the second pad, the third pad and the fourth pad.

9. The dynamic parameter testing system of claim 8, wherein the plurality of test claws are respectively a CV blade, a CI blade, a BV blade, a BI blade, an EI blade, and an EV blade, each of which is disposed in parallel and spaced along a width direction of the test claw, the EI blade being disposed below the EV blade, the BI blade being disposed below the BV blade, and the CI blade being disposed below the CV blade.

10. The dynamic parametric test system of claim 9, wherein each of the test fingers has a first end and a second end,

11. The dynamic parameter testing system of claim 10, wherein the CE external port has an EI sub-end, a CI sub-end, and an output port, the first end of the CI compression sheet being connected to the CI sub-end via a twisted pair and the output port, the first end of the EI compression sheet being connected to the EI sub-end via a twisted pair and the output port.