CN218240297U - Dynamic performance testing device for wide-bandgap power semiconductor device - Google Patents
Dynamic performance testing device for wide-bandgap power semiconductor device Download PDFInfo
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- CN218240297U CN218240297U CN202221919286.XU CN202221919286U CN218240297U CN 218240297 U CN218240297 U CN 218240297U CN 202221919286 U CN202221919286 U CN 202221919286U CN 218240297 U CN218240297 U CN 218240297U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000012360 testing method Methods 0.000 title claims abstract description 41
- 239000003990 capacitor Substances 0.000 claims description 33
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 7
- 239000003985 ceramic capacitor Substances 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011056 performance test Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
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Abstract
The utility model relates to a semiconductor device testing device, and discloses a dynamic performance testing device for a wide bandgap power semiconductor device, which comprises a pulse signal generator, a driving unit and a power supply for providing a power supply for the testing device; the pulse signal generator provides a pulse signal to the driving unit; the driving unit comprises a driving mother board and a driving daughter board which is connected with the driving mother board in a plugging manner; and the wide bandgap power semiconductor device to be tested is arranged on the drive daughter board. The testing device designed by the utility model has flexible testing due to the plug-in connection of the drive daughter board and the drive mother board, and different drive daughter boards can be replaced according to different testing requirements; simultaneously pass through the utility model discloses an its parasitic inductance of testing arrangement is little.
Description
Technical Field
The utility model relates to a semiconductor device testing arrangement has especially related to a wide forbidden band power semiconductor device dynamic behavior testing arrangement.
Background
Third generation semiconductor technology based on SiC and GaN is developing vigorously, and the corresponding performance test requirements of discrete devices are also coming with it. In order to accurately evaluate the switching characteristics and the limiting characteristic parameters of the wide bandgap semiconductor device, a pulse test circuit is usually required to be built to evaluate the dynamic performance of the device. Most of the current power semiconductor device dynamic performance measuring platforms are designed based on Si devices, the loop parasitic inductance is large, and due to the fact that the third-generation semiconductor switching speed is high, the voltage and current change rate is high, and di/dt can reach dozens of kA/us, the requirements on loop parasitic parameters are stricter, and the current driving design scheme cannot meet the requirements.
For example, application No. CN201410320974.8 discloses a bandwidth testing apparatus and method for a wide bandgap semiconductor power device. In the existing scheme, a test device and a pulse test circuit are arranged in a circuit system, and in order to meet the performance verification requirements of different device packages and different drive ICs thereof, a circuit board is generally required to be redesigned, so that the flexibility and convenience of the test are poor, the batch test is not facilitated, the parasitic inductance of a flexible scheme loop is large, the voltage and current oscillation is serious, the device can be damaged when the voltage and current oscillation is serious, and great challenge is brought to the dynamic test.
Disclosure of Invention
The utility model provides a wide forbidden band power semiconductor device dynamic behavior testing arrangement to the not high problem of prior art wide forbidden band power semiconductor device dynamic behavior test flexibility ratio.
In order to solve the technical problem, the utility model discloses a following technical scheme can solve:
a dynamic performance testing device for a wide bandgap power semiconductor device comprises a pulse signal generator, a driving unit and a power supply for providing a power supply for the testing device; the pulse signal generator provides a pulse signal to the driving unit; the driving unit comprises a driving mother board and a driving daughter board which is connected with the driving mother board in a plugging manner; and the wide bandgap power semiconductor device to be tested is arranged on the drive daughter board.
Preferably, the drive sub-board is provided with a drive IC and a buffer capacitor Cs; the driving IC is used for driving the wide bandgap power semiconductor device to be tested; the buffer capacitor Cs is connected with the wide bandgap power semiconductor device to be tested.
Preferably, an inductor is externally connected to the drive motherboard through a wiring terminal; the driving daughter board is also provided with a half-bridge structure matching unit; the half-bridge structure matching unit is connected with the inductor L in parallel and continues current to the inductor L.
Preferably, a power conversion module and a bus capacitor Cbus are further arranged on the drive motherboard; the power supply provides power to the power conversion module; the power supply conversion module generates a driving voltage to the driving daughter board; the bus capacitor Cbus is used to provide an instantaneous current to the inductor L.
Preferably, the wide bandgap power semiconductor device to be tested, the half-bridge structure matching unit and the buffer capacitor Cs are sequentially placed and located on the same PCB, and the wide bandgap power semiconductor device to be tested, the half-bridge structure matching unit and the buffer capacitor Cs form a magnetic field cancellation loop through the PCB to reduce parasitic inductance of the commutation loop.
Preferably, the wide bandgap power semiconductor device to be tested comprises a Si device, a SiC device or a GaN device.
Preferably, the half-bridge structure matching unit comprises a diode or a device of the same type as the wide bandgap power semiconductor device to be tested.
Preferably, a high-voltage direct current source connecting terminal is further arranged on the driving mother board, and the high-voltage direct current source is used for charging the inductor L.
Preferably, the buffer capacitor Cs includes a ceramic capacitor or a thin film capacitor.
Preferably, the bus capacitor Cbus is an electrolytic capacitor or a thin film capacitor.
The utility model discloses owing to adopted above technical scheme, have apparent technological effect:
the utility model discloses a plug of drive mother board and drive daughter board is connected, changes different drive daughter boards to different test devices to can test power device in a flexible way.
The utility model discloses an utilize the PCB board to constitute the magnetic field cancellation return circuit and reduce parasitic inductance.
The utility model discloses buffer capacitor's design has further reduced parasitic inductance to reduce the oscillation.
Drawings
FIG. 1 is a system framework diagram of the present invention;
fig. 2 is a schematic diagram of the driving sub-board of the present invention for optimizing parasitic inductance;
FIG. 3 is a circuit diagram of the dual pulse test of the present invention;
FIG. 4 is a diagram of the dual pulse waveform of the present invention;
FIG. 5 is a flow chart of the double pulse test of the present invention;
FIG. 6 is a circuit diagram of the single pulse test of the present invention;
FIG. 7 is a waveform diagram of a single pulse of the present invention;
fig. 8 is a schematic diagram of a power conversion module of the present invention;
fig. 9 is a waveform diagram of the present invention for processing a wide bandgap power semiconductor device.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Example 1
A dynamic performance testing device for a wide bandgap power semiconductor device is disclosed, wherein FIG. 1 is a general block diagram of the dynamic performance testing device for the wide bandgap power semiconductor device; the power supply provides an input power supply of the power supply conversion module; the power supply conversion module converts input voltage into maximum driving positive voltage and negative voltage meeting the requirements of a power device through a switching power supply module or a linear voltage stabilizing converter, and then adjusts output driving positive and negative voltage through a linear adjustable voltage stabilizer to generate driving voltage required by a wide bandgap power semiconductor device to be detected; the driving voltage of the power semiconductor device can be flexibly adjusted according to the requirements of different wide bandgap power semiconductor devices to be tested.
The pulse signal generator provides a pulse signal to a driving IC of the driving unit; the driving IC is used for driving the wide bandgap power semiconductor device to be tested.
The pulse signal to the pulse generator includes a pulse signal generated by a function generator, a pulse signal generated by a controller, or a pulse signal generated by an MCU.
The driving unit comprises a driving mother board and a driving daughter board which is connected with the driving mother board in a plugging and unplugging manner; the drive daughter board comprises a drive IC, a half-bridge circuit formed by the wide-bandgap power semiconductor device to be tested and a buffer capacitor Cs. The drive mother board mainly comprises a bus capacitor Cbus and a pluggable connector connected with the drive daughter board, and the drive mother board also comprises a voltage conversion module, a wiring terminal connected with a high-voltage direct-current power supply and an external hollow inductor.
Example 2
On the basis of embodiment 1, fig. 2 is a schematic diagram of optimizing parasitic inductance of a driving sub-board; in fig. 2, Q1 is a wide bandgap power semiconductor device to be tested, and the wide bandgap power semiconductor device to be tested includes a SiC device, a GaN device or a Si device; q2 is a matching device of a half-bridge structure, and the matching device of the half-bridge structure comprises a diode or a device with the same type as the wide bandgap power semiconductor device to be tested; cs is a buffer capacitor with low parasitic inductance, and the buffer capacitor comprises a ceramic capacitor or a thin film capacitor. When the device Q1 to be tested is turned off, high-frequency current conversion current flows to the Vbus + end of the buffer capacitor Cs through the Q1 and the Q2, flows back to the Q1 from the other layer of the PCB through the PCB via hole after passing through the Cs, and the directions of the upper layer and the lower layer of the PCB are opposite, so that the magnetic fields are mutually offset, and the parasitic inductance of the current conversion loop can be reduced.
Example 3
On the basis of the above embodiments, the present embodiment is a double-pulse test circuit, and the driving daughter board in fig. 3 mainly includes Q1, Q2, cs and a driving IC; q1 is a wide bandgap power semiconductor device TO be tested, can be a Si, siC or GaN device, and can be a package such as TO220, TOLL, TO247-3, TO247-4, TO263-7, DFN or IC. The wide bandgap power semiconductor device to be tested comprises a SiC device, a GaN device or a Si device; q2 is a matching device of a half-bridge structure, and the matching device of the half-bridge structure comprises a diode or a device with the same type as the wide bandgap power semiconductor device to be tested; cs is a buffer capacitor with low parasitic inductance, and the buffer capacitor comprises a ceramic capacitor or a thin film capacitor. Q1, Q2, cs reduce parasitic inductance through magnetic field cancellation techniques of multilayer PCBs.
A bus capacitor Cbus, which is usually an electrolytic capacitor or a thin-film capacitor, which supplies the inductor with a momentary pulse current, is placed on the motherboard and is connected to a high-voltage direct current source via a positive terminal Vbus +, a negative terminal Vbus-, and L is an air-core inductor.
FIG. 4 is a waveform of a double pulse signal, Q2 always gives a turn-off signal, and time τ 1 is adjusted according to actual current demand IL; and τ 1= l il/Vdc;
and (3) the Q1 tube to be measured is conducted within the time tau 1, the high-voltage direct-current source charges the inductor L, so that the current continuously rises to the required measurement current, then the Q1 tube is turned off to measure the turn-off characteristic under the current, and after Q2 afterflow in a short time, the Q1 tube is turned on to measure the reverse recovery characteristic of the Q2 tube and the turn-on characteristic of the Q1 tube.
The specific measurement process can be seen from fig. 5, which includes:
step 1: replacing the drive daughter board according to the wide bandgap power semiconductor device to be tested;
and 2, step: a high-voltage direct-current power supply and a hollow inductor L are connected;
step 3, adjusting the output voltage of the power conversion module to the driving voltage required by the wide bandgap power semiconductor device to be tested through a power supply;
step 4, setting the pulse width of a pulse generator;
step 5, starting a power supply, setting the output of a high-voltage direct-current power supply, and sending out pulses by a pulse generator;
step 6, reading and measuring the voltage value of the wide bandgap power semiconductor device and the current value of the wide bandgap power semiconductor device through an oscilloscope or a storage unit;
and 7, calculating and processing dynamic characteristic data of the wide bandgap power semiconductor device. As shown in fig. 9, the voltage and current are integrated to obtain the switching losses Eon, eoff when turned on and off; the time interval from the rise of the drive voltage Vgs by 10% to the fall of the drain voltage Vds by 90% is the on time ton, and the time interval from the fall of the drive voltage Vgs by 10% to the rise of Vds by 90% is the off time toff; the voltage current change rate of dv/dt, di/dt can also be obtained from the voltage current and time.
Example 4
On the basis of the foregoing embodiments, the present embodiment is a single-pulse short-circuit test circuit for a wide-bandgap semiconductor device, and in fig. 6, a driving unit includes a driving motherboard and a driving daughter board that is connected to the driving motherboard in a plug-in manner; the wide-bandgap power semiconductor device Q1 to be tested is placed on the drive daughter board, and the Vbus + and Vr wiring terminals are in short circuit. Fig. 7 is a waveform of a single pulse signal, the single pulse width τ is adjusted to perform a single pulse test, and the waveform is continuously adjusted to be increased until the to-be-tested tube is exploded, so that the extreme dynamic characteristics of the to-be-tested device, that is, the maximum short-circuit current tolerance and the short-circuit time of the device, can be obtained.
Claims (9)
1. A dynamic performance testing device for a wide bandgap power semiconductor device comprises a pulse signal generator, a driving unit and a power supply for providing a power supply for the testing device; the pulse signal generator provides a pulse signal to the driving unit; the driving unit comprises a driving mother board and a driving daughter board which is connected with the driving mother board in a plugging manner; and the wide bandgap power semiconductor device to be tested is arranged on the drive daughter board.
2. The dynamic performance testing device of the wide bandgap power semiconductor device as claimed in claim 1, wherein the driving daughter board is provided with a driving IC and a buffer capacitor Cs; the driving IC is used for driving the wide bandgap power semiconductor device to be tested; the buffer capacitor Cs is connected with the wide bandgap power semiconductor device to be tested.
3. The dynamic performance testing device of the wide bandgap power semiconductor device as claimed in claim 1, wherein an inductor L is externally connected to the driving motherboard through a connection terminal; the driving daughter board is also provided with a half-bridge structure matching unit; the half-bridge structure matching unit is connected with the inductor L in parallel and continues current to the inductor L.
4. The dynamic performance testing device of the wide bandgap power semiconductor device as claimed in claim 1, wherein the driving motherboard further comprises a power conversion module and a bus capacitor Cbus; the power supply provides power to the power conversion module; the power supply conversion module generates a driving voltage to the driving daughter board; the bus capacitor Cbus is used to provide an instantaneous current to the inductor L.
5. The device for testing the dynamic performance of the wide bandgap power semiconductor device according to claim 1, wherein the wide bandgap power semiconductor device to be tested comprises a Si device, a SiC device or a GaN device.
6. The apparatus of claim 3, wherein the half-bridge configuration unit comprises a diode or a device of the same type as the wide bandgap power semiconductor device to be tested.
7. The dynamic performance testing device of claim 3, wherein the driving motherboard is externally connected with a high voltage direct current source through a connecting terminal, and the high voltage direct current source is used for charging the inductor L.
8. The apparatus for testing dynamic performance of a wide bandgap power semiconductor device as claimed in claim 2, wherein the buffer capacitor Cs comprises a ceramic capacitor or a thin film capacitor.
9. The device for testing the dynamic performance of the wide bandgap power semiconductor device according to claim 4, wherein the bus capacitor Cbus is an electrolytic capacitor or a thin film capacitor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221919286.XU CN218240297U (en) | 2022-07-21 | 2022-07-21 | Dynamic performance testing device for wide-bandgap power semiconductor device |
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| CN202221919286.XU CN218240297U (en) | 2022-07-21 | 2022-07-21 | Dynamic performance testing device for wide-bandgap power semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115884588A (en) * | 2023-01-16 | 2023-03-31 | 长城电源技术有限公司 | Method for forming switching power converter and switching power converter formed by same |
| CN116068360A (en) * | 2023-03-24 | 2023-05-05 | 佛山市联动科技股份有限公司 | Dynamic parameter test system |
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2022
- 2022-07-21 CN CN202221919286.XU patent/CN218240297U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115884588A (en) * | 2023-01-16 | 2023-03-31 | 长城电源技术有限公司 | Method for forming switching power converter and switching power converter formed by same |
| CN115884588B (en) * | 2023-01-16 | 2023-04-25 | 长城电源技术有限公司 | Method for forming switching power supply converter and switching power supply converter formed by same |
| CN116068360A (en) * | 2023-03-24 | 2023-05-05 | 佛山市联动科技股份有限公司 | Dynamic parameter test system |
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Address after: A160, Building 1, No. 316 Binhai Fourth Road, Qianwan New District, Ningbo City, Zhejiang Province Patentee after: Painjie Semiconductor (Zhejiang) Co.,Ltd. Country or region after: China Address before: Room D3204, 3rd Floor, Building 1 (North), No. 368 Liuhe Road, Puyan Street, Binjiang District, Hangzhou City, Zhejiang Province Patentee before: PN JUNCTION SEMICONDUCTOR (HANGZHOU) Co.,Ltd. Country or region before: China |