CN114189132B

CN114189132B - Control method and circuit for power factor correction

Info

Publication number: CN114189132B
Application number: CN202111572004.3A
Authority: CN
Inventors: 喻尊; 李涅; 李伊珂
Original assignee: Jingyi Semiconductor Co ltd
Current assignee: Jingyi Semiconductor Co ltd
Priority date: 2021-12-21
Filing date: 2021-12-21
Publication date: 2024-05-17
Anticipated expiration: 2041-12-21
Also published as: CN114189132A

Abstract

Embodiments of the present disclosure relate to a control method and circuit of a power factor correction circuit. The method comprises the following steps: when the node voltage on the common node of the main switching tube and the auxiliary switching tube drops to the minimum value, the main switching tube is turned on; generating a compensation time, wherein the compensation time is a time difference between the moment when the node voltage drops to the input voltage of the power factor correction circuit and the moment when the node voltage drops to the minimum value; and controlling the main switching tube to be turned on for a preset fixed on time and a compensation time, and then turning off the main switching tube. The method improves the effect of power factor correction and can effectively reduce the total harmonic distortion value.

Description

Control method and circuit for power factor correction

Technical Field

The present invention relates to electronic circuits, and more particularly to a control method and circuit for reducing total harmonic distortion (Total Harmonics Distortion, THD) in a power factor correction (Power Factor Correction, PFC) circuit.

Background

In recent years, switching power supply devices have been widely used in the related fields of power systems, industry, traffic, and the like. However, due to the nonlinear characteristic of the switching power supply, when the switching power supply is connected with a power grid, the rectifying equipment causes distortion of input current of the power grid, so that the current contains a large amount of harmonic waves, the power factor of the power supply is low, electronic components are misoperation and the like, and the service life and normal functions of the equipment are seriously affected. Meanwhile, a large amount of harmonic waves flow into the power grid, and serious harmonic pollution is caused to the power grid. In order to reduce harmonic pollution of power electronic devices such as a switching power supply to a power grid, some national and international organizations have successively established relevant harmonic standards. To meet these harmonic standards, PFC techniques must be used to bring the input current harmonics of the switching converter to the limit standards.

THD is the ratio of the total effective value of all harmonic current components to the fundamental current effective value. With the development of electronic technology, the requirements on THD are also higher and higher in the power factor correction process, and it is desired to reduce the THD value as much as possible.

A PFC circuit of a BOOST topology is shown in fig. 1. The PFC control circuit controls the on-off switching of the main switching tube MS to enable the input current IAC to be in direct proportion to the input voltage VAC, and further system power factor correction is achieved. When the PFC control circuit adopts a critical on constant on-time control mode, its ideal waveform is shown in fig. 2. However, during actual operation, the circuit will resonate due to the parasitic capacitance of the main switch MS and the stray capacitance on the line, and the actual inductor current waveform is shown in fig. 3. Since the voltage VSW at the node SW starts to decrease after the inductor current IL reverses, the average value of the actual inductor current IL is iavg= (VIN (t_old- Δt)/L-Ineg)/2, and thus the average current Iavg is no longer proportional to VIN. At this time, THD may be deteriorated. In addition, when the input voltage VIN is relatively low, resonance clamps the voltage VSW at node SW to around-1V, at which time Δt is greatly lengthened, ultimately making THD worse.

Therefore, how to further reduce the THD value is an important point of research by those skilled in the art and a problem to be solved.

Disclosure of Invention

The present invention aims to solve the above problems in the prior art, and proposes a control method and a circuit for reducing THD in a PFC circuit.

According to an aspect of the present invention, there is provided a control method for a power factor correction circuit including a master switching tube and a slave switching tube, comprising: sampling node voltages on a common node of the master switching tube and the slave switching tube; judging whether the node voltage is equal to the input voltage of the power factor correction circuit; when the node voltage is equal to the input voltage, starting timing; judging whether the node voltage drops to the lowest value; when the node voltage drops to the minimum value, the main switching tube is turned on, and the timing is stopped, so that compensation time is generated, wherein the compensation time is the time difference between starting timing and ending timing; and after the main switching tube is controlled to be conducted for a preset fixed conduction time and compensation time, the main switching tube is turned off.

According to another aspect of the present invention, there is provided a control method for a power factor correction circuit including a master switching tube and a slave switching tube, comprising: when the node voltage on the common node of the main switching tube and the auxiliary switching tube drops to the minimum value, the main switching tube is turned on; generating a compensation time, wherein the compensation time is a time difference between the moment when the node voltage drops to the input voltage of the power factor correction circuit and the moment when the node voltage drops to the minimum value; and controlling the main switching tube to be turned on for a preset fixed on time and a compensation time, and then turning off the main switching tube.

According to still another aspect of the present invention, there is provided a control circuit for a power factor correction circuit, comprising: the first voltage judging module is used for receiving the node voltage sampling signal and generating a timing start indicating signal according to the node voltage sampling signal, wherein the node voltage sampling signal represents node voltages on a common node of a master switching tube and a slave switching tube in the power factor correction circuit, and the timing start indicating signal is used for indicating whether the node voltage is equal to the input voltage of the power factor correction circuit; the valley voltage judging module is used for receiving the node voltage sampling signals and generating timing end indicating signals according to the node voltage sampling signals, wherein the timing end indicating signals are used for indicating whether the node voltage is reduced to the lowest value or not; the on-time generating circuit receives the timing start indication signal and the timing end indication signal and generates an on-time signal according to the timing start indication signal and the timing end indication signal; the control module receives the timing end indication signal and the on-time signal and generates a main switch tube control signal according to the timing end indication signal and the on-time signal, wherein the main switch control signal is used for controlling the on-off switching of the main switch tube.

By using the embodiments of the present disclosure, corresponding technical effects can be achieved.

Drawings

Fig. 1 shows a PFC circuit of a BOOST topology according to the prior art;

FIG. 2 illustrates an idealized waveform of the circuit of FIG. 1;

FIG. 3 shows actual waveforms of the circuit of FIG. 1;

fig. 4 provides circuitry 100 with PFC control according to one embodiment of the present invention;

Fig. 5 illustrates a PFC control method 200 that may reduce THD according to one embodiment of the present invention;

FIG. 6 is a schematic diagram of waveforms according to one embodiment of the present invention;

fig. 7 is a schematic circuit diagram of an embodiment of the PFC control circuit 10 according to the embodiment of fig. 4;

Fig. 8 is a schematic circuit diagram of another embodiment of the PFC control circuit 10 according to the embodiment of fig. 4;

Fig. 9 is a schematic circuit diagram of an embodiment of the first voltage determination module 101 in the embodiments of fig. 7 and 8;

FIG. 10 is a schematic circuit diagram of an embodiment of the valley voltage determination module 102 in the embodiments of FIGS. 7 and 8;

Fig. 11 is a schematic circuit diagram of an embodiment of the on-time generating circuit 107 in the embodiment of fig. 8.

As shown in the drawings, like reference numerals refer to like parts throughout the different views. The drawings are provided for the purpose of illustrating embodiments, concepts, etc. and are not drawn to scale.

Detailed Description

Specific embodiments of the invention will now be described, without limitation, with reference to the accompanying drawings. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The verbs "comprise" and "have" are used herein as open limits, which neither exclude nor require that there be unrecited features. Features recited in the dependent claims may be freely combined with each other unless explicitly stated otherwise. The use of an element defined as "one" or "one" (i.e., in the singular) throughout this document does not exclude the possibility of a plurality of such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise indicated, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct or may be via one or more other elements. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. When referring to the voltage of a node or terminal, unless indicated otherwise, the voltage is considered to be the voltage between that node and a reference potential (typically ground). Further, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to a reference potential. The voltages and potentials of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal. The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of the logic signal may correspond to voltages or currents that may not be entirely constant in the high or low states.

Fig. 4 provides a circuit system 100 with PFC control. As shown in fig. 4, in the circuit system 100, the ac voltage VAC is rectified by a rectifier and filtered by a capacitor CIN to become the input voltage VIN. The input voltage VIN is converted into the output voltage VOUT through power factor correction by a PFC circuit of a BOOST topological structure. Wherein the common node of the main switching tube MS and the diode D is denoted SW. The PFC control circuit receives a node voltage sampling signal vsw_sen of the node voltage VSW at the node SW, and generates a control signal CTL for controlling the on and off of the main switching tube MS according to the node voltage sampling signal vsw_sen. It will be appreciated by those skilled in the art that in this BOOST topology, the slave switching tube is illustrated as a diode D, and in other embodiments, the slave switching tube may be a controllable semiconductor power switching device as well as the master switching tube MS. In the embodiment shown in fig. 4, the main switching tube MS is illustrated as an N-type metal semiconductor field effect Transistor (NMOSFET), but those skilled in the art will appreciate that the main switching tube MS may be any other suitable controllable semiconductor power switching device.

Fig. 5 illustrates a PFC control method 200 that may reduce THD according to one embodiment of the present invention. PFC control method 200 may be used in the embodiment previously described with respect to fig. 4. As shown in fig. 5, the PFC control method 200 includes steps S1-S6.

The step S1 comprises the following steps: the node voltage VSW at the node SW is sampled.

The step S2 comprises the following steps: it is determined whether the node voltage VSW is equal to the input voltage VIN. When the node voltage VSW is equal to the input voltage VIN, go to step S3; otherwise, the step S2 is continued.

The step S3 comprises the following steps: a timer is started. It should be noted that "counting" herein does not merely refer to starting counting by the timer. But rather to record the point in time at which the node voltage VSW is equal to the input voltage VIN. Methods of recording this point in time are numerous, including analog methods, and may also include digital methods. In one embodiment, recording the time point includes generating a pulse signal at the time point.

The step S4 includes: it is determined whether the node voltage VSW falls to a minimum value, i.e., a valley bottom value. When the node voltage VSW falls to the valley value, go to step S5; otherwise, the step S4 is continued.

The step S5 comprises the following steps: stopping timing, generating compensation time delta t, and turning on the main switch tube MS. In one embodiment, the compensation time Δt represents: the node voltage VSW is equal to the time difference between the time when the input voltage VIN and the time when the node voltage VSW drops to the valley. Likewise, the term "stop counting" herein does not merely refer to a timer stopping counting. But rather to record the point in time at which the node voltage VSW reaches the minimum value. In one embodiment, recording the time point includes generating a pulse signal at the time point.

The step S6 comprises the following steps: after the main switching tube MS is conducted for a preset fixed conduction time and compensation time, the main switching tube MS is turned off. It should be noted that the preset fixed on time is determined by the circuit parameters, and is set by the technician according to the related circuit parameters and requirements.

Fig. 6 is a schematic waveform diagram according to one embodiment of the present invention. As can be seen in connection with the PFC control method of fig. 5 and the waveforms of fig. 6: determining a time a when the node voltage VSW is equal to the input voltage VIN; time b is determined when node voltage VSW drops to a valley. The time between the two moments is Δt. In the embodiment provided by the invention, in order to reduce the value of THD, in a new period, the main switch tube MS is conducted at the moment b, and meanwhile, the conducting time is changed to t_old+deltat, so that the average current error caused by negative current is compensated. As shown in fig. 6, in the embodiment of the present invention, the average current iavg= (VIN (t_old+Δt)/L-Ineg)/2. Due toWhen VIN > VOUT/2, ineg < < VIN (t_old+Δt)/L is found by calculation, and Δt time is also shorter because Ineg is smaller. Iavg is approximately VIN t_old/(2*L). When VIN < VOUT/2, the valley will be clamped to-1V due to the larger resonance amplitude of the node SW, and Ineg is about VIN is about Δt/L, so Iavg is about VIN is about t_old/(2*L). By compensation, iavg is in direct proportion to the input voltage VIN, thereby ensuring that excellent THD values, i.e. low THD values, are exhibited under different input voltages and different load currents.

Fig. 7 is a schematic circuit diagram of an embodiment of the PFC control circuit 10 according to the embodiment of fig. 4. In the embodiment shown in fig. 7, the PFC control circuit 10 includes a first voltage determination module 101, a valley voltage determination module 102, a compensation time generation module 103, a constant on time generation module 104, a time superimposing circuit 105, and a control module 106.

The first voltage determination module 101 receives the node voltage sampling signal vsw_sen of the node voltage VSW, and generates a timing start instruction signal Tstart according to the node voltage sampling signal vsw_sen. In one embodiment, the first voltage determining module 101 determines the magnitudes of the node voltage VSW and the input voltage VIN according to the node voltage sampling signal vsw_sen, and the timing start indication signal Tstart is used for indicating whether the node voltage VSW is equal to the input voltage VIN. In one embodiment, the timing start indication signal Tstart is a high and low logic level signal, having an active state and an inactive state. In one embodiment, the logic low level is the active state of the timing start indication signal Tstart. For example, when the timing start indication signal Tstar changes from an inactive state (e.g., a logic high level) to an active state (e.g., a logic low level), it indicates that the node voltage VSW is equal to the input voltage VIN.

The valley voltage determination module 102 receives the node voltage sampling signal vsw_sen and generates a timing end indication signal Tend according to the node voltage sampling signal vsw_sen. In one embodiment, the valley voltage determining module 102 determines whether the node voltage VSW reaches the lowest valley according to the node voltage sampling signal vsw_sen, and the end-of-timer indication signal Tend is used to indicate that the node voltage VSW reaches the lowest valley. In one embodiment, the end of timing indication signal Tend is a high and low logic level signal having an active state and an inactive state. In one embodiment, the logic high level is the active state of the end of timing indication signal Tend. For example, when the end-of-timing indication signal Tend changes from an inactive state (e.g., a logic low level) to an active state (e.g., a logic high level), it indicates that the node voltage VSW reaches the lowest valley.

The compensation time generation module 103 receives the timing start instruction signal Tstar and the timing end instruction signal Tend, and generates a compensation time signal Δt according to the timing start instruction signal Tstar and the timing end instruction signal Tend. In one embodiment, the compensation time signal Δt represents a period from a time point when the timing start instruction signal Tstar becomes active to a time point when the timing end instruction signal Tend becomes active from the inactive to the time point (a period Δt as shown in fig. 6) as the THD compensation period. In one embodiment, the compensation time generation module 103 includes a timer that starts counting at the time when the count start indication signal Tstar changes from inactive to active and ends counting at the time when the count end indication signal Tend changes from inactive to active. In one embodiment, the compensation time signal Δt includes a high-low logic level signal having an active state and an inactive state, and the logic high level is the active state of the compensation time signal Δt.

The constant on-time generation module 104 generates a constant on-time signal t_old. In one embodiment, the constant on-time signal t_old represents a constant on-time of the main switch MS (time t_old as shown in fig. 6) preset by the system according to the parameter. In one embodiment, the constant on-time signal T_old includes a high and low logic level signal, having an active state and an inactive state. In one embodiment, the logic high level is the active state of the constant on-time signal T_old. In one embodiment, the main switching tube MS is turned off when the constant on-time signal t_old changes from an inactive state (e.g., a logic low level) to an active state (e.g., a logic high level).

The time superimposing circuit 105 receives the compensation time signal Δt and the constant on time signal t_old, and superimposes the compensation time signal Δt and the constant on time signal t_old to generate the on time signal TON. In one embodiment, the on-time signal TON represents the sum of a preset constant on-time t_old and THD compensation time Δt of the main switching tube MS. In one embodiment, the time superimposing circuit 105 includes a logic circuit.

The control module 106 receives the timing end indication signal Tend and the on-time signal TON, and generates the main switching tube control signal CTL according to the timing end indication signal Tend and the on-time signal TON to control the on-off switching of the main switching tube MS. In one embodiment, the control module 106 includes an RS flip-flop, a set terminal S of the RS flip-flop receives the end-of-timing indication signal Tend, a reset terminal R of the RS flip-flop receives the on-time signal TON, and the RS flip-flop outputs the control signal CTL at an output terminal Q. When the timing end indication signal Tend changes from invalid to valid, the control signal CTL controls the main switching tube MS to be conducted; when the on-time signal TON changes from inactive to active, the control signal CTL controls the main switching tube MS to turn off.

Fig. 8 is a circuit diagram of another embodiment of the PFC control circuit 10 according to the embodiment of fig. 4. In the embodiment shown in fig. 8, the first voltage determination module 101, the valley voltage determination module 102, and the control module 106 are unchanged, and the compensation time generation module 103, the constant on time generation module 104, and the time superimposing circuit 105 are replaced with the on time generation circuit 107. That is, the on-time generating circuit 107 receives the timing start instruction signal Tstar and the timing end instruction signal Tend, and generates an on-time signal TON according to the timing start instruction signal Tstar and the timing end instruction signal Tend.

Fig. 9 is a schematic circuit diagram of an embodiment of the first voltage determination module 101 in the embodiments of fig. 7 and 8. In the embodiment shown in fig. 9, the first voltage determination module 101 includes a filter circuit 1011 and a comparison circuit 1012.

The filter circuit 1011 receives the node voltage sampling signal vsw_sen and filters the node voltage sampling signal vsw_sen to generate an input voltage sampling signal vin_sen. In one embodiment, the input voltage sample signal vin_sen represents a sample value of the input voltage VIN. In one embodiment, filter circuit 1011 includes a resistor R1 and a capacitor C1. Resistor R1 and capacitor C1 are coupled in series between the output of the node voltage sampling circuit and ground. The common node of resistor R1 and capacitor C1 provides an input voltage sample signal vin_sen.

The comparison circuit 1012 receives the node voltage sampling signal vsw_sen and the input voltage sampling signal vin_sen, and compares the node voltage sampling signal vsw_sen and the input voltage sampling signal vin_sen to generate a timing start indication signal Tstar. In one embodiment, the comparison circuit 1012 includes a voltage comparator COM1 having a non-inverting input terminal receiving the node voltage sample signal vsw_sen and an inverting input terminal receiving the input voltage sample signal vin_sen. When the node voltage sampling signal vsw_sen decreases to the input voltage sampling signal vin_sen, the timing start indication signal Tstar changes from a logic high level to a logic low level.

Fig. 10 is a schematic circuit diagram of an embodiment of the valley voltage determination module 102 in the embodiments of fig. 7 and 8. In the embodiment shown in fig. 10, the valley voltage determining module 102 includes a switch tube M1, a resistor R2, a capacitor C2, and a comparing circuit 1021.

The switching tube M1 has a first end, a second end and a control end. The first end of the switch tube M1 is coupled with a common node of the resistor R1 and the capacitor C1; the second end of the switch tube M1 is coupled with the reference ground; the control terminal of the switching tube M1 receives the main switching tube control signal CTL. Resistor R2 and capacitor C2 are coupled in series between the output of the node voltage sampling circuit and ground. The common node of resistor R2 and capacitor C2 provides the valley bottom voltage signal Vvalley. In the embodiment shown in fig. 10, the switching transistor M1 is illustrated as an NMOS transistor, and in other embodiments, the switching transistor M1 may be illustrated as another type of controllable semiconductor device.

The comparison circuit 1021 has a first terminal receiving the valley voltage signal Vvalley, a second terminal electrically connected to the ground, and an output terminal, and the comparison circuit 1021 compares the voltage of the valley voltage signal Vvalley and the reference ground to generate the end-of-time indication signal Tend. In one embodiment, the comparison circuit 1021 includes a voltage comparator COM2 having a non-inverting input and an inverting input, the non-inverting input of which receives the valley bottom voltage signal Vvalley, the inverting input being electrically connected to ground. When the valley voltage signal Vvalley is positive, it indicates that the node voltage VSW has reached the valley value, and the end-of-timing indication signal Tend changes from a logic low level to a logic high level.

Fig. 11 is a schematic circuit diagram of an embodiment of the on-time generating circuit 107 in the embodiment of fig. 8. In the embodiment shown in fig. 11, the on-time generation circuit 107 includes a switching transistor M2, a switching transistor M3, a switching transistor M4, a switching transistor M5, a capacitor C3, a capacitor C4, a capacitor C5, a current source I1, a current source I2, a current source I3, an inverter 1071, a comparison circuit 1072, and a comparison circuit 1073.

As shown in fig. 11, a current source I1 and a capacitor C3 are coupled in series between a power supply VCC and a reference ground.

The switching tube M2 has a first end, a second end and a control end. A first end of the switch tube M2 is coupled with a common node of the current source I1 and the capacitor C3; the second end of the switch tube M2 is coupled with the reference ground; the control terminal of the switching transistor M2 receives the end-of-time indication signal Tend through the inverter 1071.

The switching tube M3 has a first end, a second end and a control end. The first end of the switch tube M3 is coupled with the current source I1; the second end of the switch tube M3 is coupled with one end of the capacitor C4; the control end of the switching tube M3 receives a timing end indication signal Tend; the other end of the capacitor C4 is connected to the reference ground.

The switching tube M4 has a first end, a second end and a control end. The first end of the switch tube M4 is coupled with the second end of the switch tube M3; a second end of the switching tube M4 is connected to the reference ground; the control terminal of the switching tube M4 receives the timing start indication signal Tstar.

The comparison circuit 1072 has a first end, a second end and an output end, the first end of which receives the voltage signal V3 on the first end of the switching tube M2, the second end of which receives the voltage signal V4 on the first end of the switching tube M4, and the comparison circuit 1072 compares the voltage signal V3 with the voltage signal V4 to generate a comparison signal CT. In one embodiment, the comparison circuit 1072 includes a voltage comparator COM3 having a non-inverting input and an inverting input, the non-inverting input of which receives the voltage signal V4 and the inverting input of which receives the voltage signal V3.

The current source I3 and the capacitor C5 are coupled in series between the supply source VCC and the reference ground. The switching tube M5 has a first end, a second end and a control end. A first end of the switch tube M5 is coupled with a common node of the current source I3 and the capacitor C5; a second end of the switch tube M5 is coupled with the reference ground; the control end of the switching tube M5 receives the comparison signal CT.

The comparison circuit 1073 has a first end, a second end and an output end, wherein the first end receives the voltage signal V5 at the first end of the switching tube M5, the second end receives the fixed voltage signal VD, and the comparison circuit 1073 compares the voltage signal V5 with the fixed voltage signal VD to generate the on-time signal TON. In one embodiment, the comparison circuit 1073 includes a voltage comparator COM4 having a non-inverting input and an inverting input, the non-inverting input of which receives the voltage signal V5 and the inverting input of which receives the fixed voltage signal VD.

In the embodiment shown in fig. 11, when the timing start indication signal Tstar is in the high level period, the switch tube M4 is turned on, the comparison signal CT is logic high, the switch tube M5 is turned on, and the on-time signal TON is kept logic low. When the falling edge of the timing start indication signal Tstar comes, the switching tube M4 is turned off, and the current source I2 charges the capacitor C4 through the switching tube M3. When the rising edge of the timing end indication signal Tend is timed, the switching tube M3 is turned off, and the voltage signal V4 remains unchanged. At the same time, the switching tube M2 is turned off, the current source I1 starts charging the capacitor C3, and the voltage signal V3 increases stepwise. When the voltage signal V3 rises to the value of the voltage signal V4, the comparison signal CT becomes logic low, the switching tube M5 is turned off, the current source I3 starts to charge the capacitor C5, and the voltage signal V5 rises stepwise. When the voltage signal V5 rises to the value of the fixed voltage signal VD, the on-time signal TON becomes logic high and the main switch MS will be turned off.

In the embodiment shown in fig. 11, the switching transistors M2, M4 and M5 are illustrated as NMOS transistors, the switching transistor M3 is illustrated as PMOS transistor, and in other embodiments, the switching transistors M2-M5 may be illustrated as other suitable types of controllable semiconductor devices.

While the application has been described above with reference to several exemplary embodiments, it should be understood by those of ordinary skill in the relevant art that fig. 9-11 are only symbolically illustrating one particular embodiment of the first voltage determination module 101, the valley voltage determination module 102, and the on-time generation circuit 107, respectively, and that the terminology employed in the disclosed embodiments is for the purpose of illustration and example only and is not intended to be limiting of the application. Furthermore, various modifications in the form and details of the disclosed embodiments may be made by those skilled in the art without departing from the principles and concepts of the application, which modifications may be in the form and details within the scope of the application as defined in the claims and their equivalents.

Claims

1. A control method for a power factor correction circuit, wherein the power factor correction circuit includes a master switching tube and a slave switching tube, the control method comprising:

sampling node voltages on a common node of the master switching tube and the slave switching tube;

Judging whether the node voltage is equal to the input voltage of the power factor correction circuit;

when the node voltage is equal to the input voltage, starting timing;

Judging whether the node voltage drops to the lowest value;

when the node voltage drops to the minimum value, the main switching tube is turned on, and the timing is stopped, so that compensation time is generated, wherein the compensation time is the time difference between starting timing and ending timing; and

And after the main switching tube is controlled to be conducted for a preset fixed conduction time and compensation time, the main switching tube is turned off.

2. A control method for a power factor correction circuit, wherein the power factor correction circuit includes a master switching tube and a slave switching tube, the control method comprising:

when the node voltage on the common node of the main switching tube and the auxiliary switching tube drops to the minimum value, the main switching tube is turned on;

generating a compensation time, wherein the compensation time is a time difference between the moment when the node voltage drops to the input voltage of the power factor correction circuit and the moment when the node voltage drops to the minimum value; and

And controlling the main switching tube to be conducted for a preset fixed conduction time and a compensation time, and then turning off the main switching tube.

3. A control circuit for a power factor correction circuit, comprising:

The first voltage judging module is used for receiving the node voltage sampling signal and generating a timing start indicating signal according to the node voltage sampling signal, wherein the node voltage sampling signal represents node voltages on a common node of a master switching tube and a slave switching tube in the power factor correction circuit, and the timing start indicating signal is used for indicating whether the node voltage is equal to the input voltage of the power factor correction circuit;

The valley voltage judging module is used for receiving the node voltage sampling signals and generating timing end indicating signals according to the node voltage sampling signals, wherein the timing end indicating signals are used for indicating whether the node voltage is reduced to the lowest value or not;

The on-time generating circuit receives the timing start indication signal and the timing end indication signal and generates an on-time signal according to the timing start indication signal and the timing end indication signal;

the control module receives the timing end indication signal and the on-time signal and generates a main switch tube control signal according to the timing end indication signal and the on-time signal, wherein the main switch control signal is used for controlling the on-off switching of the main switch tube.

4. The control circuit of claim 3, wherein the first voltage determination module comprises:

the filter circuit receives the node voltage sampling signal and filters the node voltage sampling signal to generate an input voltage sampling signal, wherein the input voltage sampling signal represents an input voltage; and

And the first comparison circuit is used for receiving the node voltage sampling signal and the input voltage sampling signal, comparing the node voltage sampling signal with the input voltage sampling signal and generating the timing start indication signal.

5. The control circuit of claim 3, wherein the valley voltage determination module comprises:

The first end of the first capacitor receives the node voltage sampling signal;

The first end of the first resistor is coupled with the second end of the first capacitor, the second end of the first resistor is electrically connected to the reference ground, and a common node of the first resistor and the first capacitor provides a valley voltage signal;

The first end of the first switch tube is coupled with a common node of the first resistor and the first capacitor, the second end of the first switch tube is electrically connected with the reference ground, and the control end of the first switch tube receives a control signal of the main switch tube; and

The first end of the second comparison circuit receives the valley voltage signal, the second end of the second comparison circuit is electrically connected with the reference ground, and the second comparison circuit compares the potential of the valley voltage signal with the potential of the reference ground to generate a timing end indication signal.

6. The control circuit of claim 3, wherein the on-time generation circuit comprises a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, a second capacitor, a third capacitor, a fourth capacitor, a first current source, a second current source, a third comparison circuit, and a fourth comparison circuit, wherein,

The first current source and the second capacitor are coupled in series between the power supply and the reference ground;

the second current source and the third capacitor are coupled in series between the power supply and the reference ground through a third switching tube, and a control end of the third switching tube receives a timing end indication signal;

the third current source and the fourth capacitor are coupled in series between the power supply and the reference ground;

The first end of the second switching tube is coupled with the common end of the second capacitor and the first current source, the second end of the second switching tube is electrically connected with the reference ground, and the control end of the second switching tube receives a timing end indication signal through the inverter;

the first end of the fourth switching tube is coupled with the common end of the third capacitor and the second current source, the second end of the fourth switching tube is electrically connected with the reference ground, and the control end of the fourth switching tube receives a timing start indication signal;

The first end of the third comparison circuit is coupled with the first end of the second switching tube, the second end of the second comparison circuit is coupled with the first end of the fourth switching tube, and a comparison signal is generated at the output end;

the first end of the fifth switching tube is coupled with the common end of the fourth capacitor and the third current source, the second end of the fifth switching tube is electrically connected with the reference ground, and the control end of the fifth switching tube receives the comparison signal; and

The first end of the fourth comparison circuit is coupled to the first end of the fifth switch tube, and the second end of the fourth comparison circuit receives the fixed voltage signal and generates a conduction time signal at the output end.

7. A control circuit as claimed in claim 3, wherein the control module comprises:

The RS trigger is provided with a set end for receiving a timing end indication signal, a reset end for receiving a conduction time signal and an output end for generating a main switching tube control signal.

8. The control circuit of claim 3, wherein the on-time generation circuit comprises:

the compensation time generation module receives the timing start indication signal and the timing end indication signal and generates a compensation time signal according to the timing start indication signal and the timing end indication signal;

The constant on-time generation module is used for generating a constant on-time signal; and

And the time superposition circuit is used for receiving the compensation time signal and the constant conduction time signal, and superposing the compensation time signal and the constant conduction time signal to generate the conduction time signal.

9. The control circuit according to claim 8, wherein the compensation time signal represents a time period between a time when the timing start instruction signal changes from invalid to valid and a time when the timing end instruction signal changes from invalid to valid.

10. A control circuit as claimed in claim 3, further comprising a sampling circuit for sampling a node voltage on a common node of the master and slave switching tubes and generating a node voltage sampling signal.