CN114189132A - Control method and circuit for power factor correction - Google Patents
Control method and circuit for power factor correction Download PDFInfo
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- CN114189132A CN114189132A CN202111572004.3A CN202111572004A CN114189132A CN 114189132 A CN114189132 A CN 114189132A CN 202111572004 A CN202111572004 A CN 202111572004A CN 114189132 A CN114189132 A CN 114189132A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
Embodiments of the present disclosure relate to a control method and circuit of a power factor correction circuit. The method comprises the following steps: when the node voltage on the common node of the main switch tube and the slave switch tube is reduced to the lowest value, the main switch tube is conducted; generating a compensation time, wherein the compensation time is a time difference between a moment when the node voltage drops to the input voltage of the power factor correction circuit and a moment when the node voltage drops to a lowest value; and controlling the main switching tube to be switched on for preset fixed switching-on time and compensation time and then switching off the main switching tube. The method improves the effect of power factor correction and can effectively reduce the total harmonic distortion value.
Description
Technical Field
The present invention relates to electronic circuits, and more particularly, to a control method and circuit for reducing Total Harmonic Distortion (THD) in a Power Factor Correction (PFC) circuit.
Background
In recent years, switching power supply devices have been widely used in the fields related to power systems, industry, and transportation. However, due to the non-linear characteristic of the switching power supply, when the switching power supply is connected with a power grid, the input current of the power grid is distorted by the rectifying equipment, so that the current contains a large amount of harmonic waves, the power factor of the power supply is low, the electronic components are operated by mistake, and the service life and the normal function of the equipment are seriously influenced. Meanwhile, a large amount of harmonic waves flow into the power grid, and serious harmonic pollution is caused to the power grid. In order to reduce harmonic pollution of power electronic devices such as switching power supplies to the power grid, some national and international organizations have set relevant harmonic standards one after another. To meet these harmonic standards, PFC techniques must be used to bring the input current harmonics of the switching converter to the limiting standards.
THD is the ratio of the total effective value of all harmonic current components to the effective value of the fundamental current. With the development of electronic technology, the requirement for THD is higher and higher in the process of power factor correction, and it is desirable to reduce the THD value as much as possible.
Fig. 1 shows a PFC circuit with BOOST topology. The PFC control circuit controls the on-off switching of the main switching tube MS to enable the input current IAC and the input voltage VAC to be in a direct proportion relation, and therefore system power factor correction is achieved. When the PFC control circuit adopts the critical conduction constant on time control mode, the ideal waveform is shown in fig. 2. However, in actual operation, the circuit will resonate due to the parasitic capacitance of the main switch tube MS and the stray capacitance on the line, and the actual inductor current waveform is as shown in fig. 3. Since the voltage VSW at the node SW can start to decrease after the inductor current IL is reversed, the average value of the actual inductor current IL is Iavg ═ (VIN — (t _ old- Δ t)/L-Ineg)/2, and thus the average current Iavg is no longer proportional to VIN. At this time, THD may be deteriorated. Furthermore, when the input voltage VIN is relatively low, the resonance will clamp the voltage VSW at node SW to around-1V, at which time the time at will be greatly lengthened, eventually making THD worse.
Therefore, how to further reduce the THD value is the focus of research by those skilled in the art and is also a problem to be solved.
Disclosure of Invention
The present invention is directed to solving the above problems in the prior art, and provides a control method and circuit for reducing THD in a PFC circuit.
According to an aspect of the present invention, there is provided a control method for a power factor correction circuit, wherein the power factor correction circuit includes a master switch tube and a slave switch tube, and the control method includes: sampling node voltages on common nodes of a main switching tube and a slave switching tube; judging whether the node voltage is equal to the input voltage of the power factor correction circuit or not; when the node voltage is equal to the input voltage, starting timing; judging whether the node voltage is reduced to a minimum value; when the node voltage is reduced to the minimum value, the main switching tube is conducted, timing is stopped, and compensation time is generated, wherein the compensation time is the time difference between the start timing and the end timing; and after controlling the main switching tube to be conducted for preset fixed conduction time and compensation time, turning off the main switching tube.
According to another aspect of the present invention, there is provided a control method for a power factor correction circuit, wherein the power factor correction circuit includes a master switch tube and a slave switch tube, and the control method includes: when the node voltage on the common node of the main switch tube and the slave switch tube is reduced to the lowest value, the main switch tube is conducted; generating a compensation time, wherein the compensation time is a time difference between a moment when the node voltage drops to the input voltage of the power factor correction circuit and a moment when the node voltage drops to a lowest value; and controlling the main switching tube to be switched on for preset fixed switching-on time and compensation time and then switching off the main switching tube.
According to yet another aspect of the present invention, there is provided a control circuit for a power factor correction circuit, comprising: the first voltage judging module receives a node voltage sampling signal and generates a timing start indicating signal according to the node voltage sampling signal, wherein the node voltage sampling signal represents the node voltage on a common node of a main switching tube and a slave switching tube in the power factor correction circuit, and the timing start indicating signal is used for indicating whether the node voltage is equal to the input voltage of the power factor correction circuit or not; the valley voltage judging module is used for receiving the node voltage sampling signal and generating a timing end indicating signal according to the node voltage sampling signal, wherein the timing end indicating signal is used for indicating whether the node voltage is reduced to the lowest value or not; the on-time generating circuit receives the timing start indicating signal and the timing end indicating signal and generates an on-time signal according to the timing start indicating signal and the timing end indicating signal; and the control module receives the timing end indication signal and the conduction time signal and generates a main switching tube control signal according to the timing end indication signal and the conduction time signal, wherein the main switching tube control signal is used for controlling the on-off switching of the main switching tube.
By using the embodiments of the present disclosure, corresponding technical effects can be achieved.
Drawings
Fig. 1 shows a PFC circuit with a BOOST topology in the prior art;
FIG. 2 shows idealized waveforms of the circuit of FIG. 1;
FIG. 3 shows the actual waveforms of the circuit of FIG. 1;
fig. 4 provides circuitry 100 with PFC control according to one embodiment of the present invention;
fig. 5 illustrates a PFC control method 200 that may reduce THD according to one embodiment of the present invention;
FIG. 6 is a schematic diagram of waveforms according to one embodiment of the present invention;
fig. 7 is a circuit diagram of an embodiment of the PFC control circuit 10 of fig. 4;
fig. 8 is a circuit diagram of another embodiment of the PFC control circuit 10 of the embodiment of fig. 4;
FIG. 9 is a schematic circuit diagram of one embodiment of the first voltage determining module 101 in the embodiments of FIGS. 7 and 8;
FIG. 10 is a circuit schematic of one embodiment of the valley voltage determination module 102 of the embodiments of FIGS. 7 and 8;
fig. 11 is a schematic circuit diagram of an embodiment of the on-time generation circuit 107 of the embodiment of fig. 8.
As shown in the drawings, like reference numerals refer to like parts throughout the different views. The drawings presented herein are for purposes of illustrating the embodiments, principles, concepts and the like and are not necessarily drawn to scale.
Detailed Description
Specific embodiments of the present invention will now be described without limitation in conjunction with the accompanying drawings. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The verbs "comprising" and "having" are used herein as open-ended limitations that neither exclude nor require the presence of unrecited features. The features recited in the dependent claims may be freely combined with each other, unless explicitly stated otherwise. The use of the terms "a" or "an" (i.e., singular forms) in defining an element throughout this document does not exclude the possibility of a plurality of such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connected" is used to designate a direct electrical connection between circuit elements, while the term "coupled" is used to designate an electrical connection between circuit elements that may be direct or may be via one or more other elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When referring to a voltage of a node or terminal, the voltage is considered to be the voltage between the node and a reference potential (typically ground) unless otherwise indicated. Further, when referring to the potential of a node or a terminal, the potential is considered to refer to a reference potential unless otherwise indicated. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of the logic signal may correspond to voltages or currents that may not be completely constant in the high or low states.
Fig. 4 provides a circuit system 100 with PFC control. As shown in fig. 4, in the circuit system 100, the ac voltage VAC is rectified by the rectifier and filtered by the capacitor CIN to become the input voltage VIN. The input voltage VIN is converted into the output voltage VOUT through power factor correction by a PFC circuit of the BOOST topology. Wherein, the common node of the main switch tube MS and the diode D is marked as SW. The PFC control circuit receives a node voltage sampling signal VSW _ sen of the node voltage VSW at the node SW, and generates a control signal CTL for controlling the on and off of the main switching tube MS according to the node voltage sampling signal VSW _ sen. It will be appreciated by those skilled in the art that in the BOOST topology, the slave switch is illustrated as a diode D, and in other embodiments, the slave switch may be a controllable semiconductor power switch device, as well as the master switch MS. In the embodiment shown in fig. 4, the main switch MS is illustrated as an N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET), but it will be understood by those skilled in the art that the main switch MS may also be other suitable controllable Semiconductor power switch devices.
Fig. 5 illustrates a PFC control method 200 that may reduce THD according to one embodiment of the present invention. The PFC control method 200 may be used in the embodiment previously illustrated in fig. 4. As shown in FIG. 5, the PFC control method 200 includes steps S1-S6.
Step S1 includes: the node voltage VSW at node SW is sampled.
Step S2 includes: it is determined whether the node voltage VSW is equal to the input voltage VIN. When the node voltage VSW is equal to the input voltage VIN, go to step S3; otherwise, execution continues with step S2.
Step S3 includes: and starting timing. It should be noted that "counting" herein does not merely refer to starting the timer. But rather refers to the point in time at which it is necessary to record that node voltage VSW is equal to input voltage VIN. The method of recording the time point is many, including analog method, and also including digital method. In one embodiment, recording the point in time includes generating a pulse signal at the point in time.
Step S4 includes: it is determined whether the node voltage VSW has dropped to a minimum value, i.e., a valley value. When the node voltage VSW decreases to the valley value, go to step S5; otherwise, execution continues with step S4.
Step S5 includes: and stopping timing, generating compensation time delta t, and switching on the main switching tube MS. In one embodiment, the compensation time Δ t represents: the time difference between the time when the node voltage VSW is equal to the input voltage VIN and the time when the node voltage VSW drops to the valley value. Similarly, the term "stop timing" herein does not merely refer to the stop timing of the timer. But rather to the point in time at which it is necessary to note that the node voltage VSW has reached a minimum value. In one embodiment, recording the point in time includes generating a pulse signal at the point in time.
Step S6 includes: and after the main switching tube MS is conducted for preset fixed conduction time and compensation time, the main switching tube MS is switched off. It should be noted that the preset fixed on-time is determined by circuit parameters, and is set by a technician according to the related circuit parameters and requirements.
FIG. 6 is a waveform diagram according to an embodiment of the present invention. As can be seen from the PFC control method shown in fig. 5 and the waveform shown in fig. 6: determining a time a when the node voltage VSW is equal to the input voltage VIN; time b is determined when node voltage VSW falls to the valley. The time between the two moments is deltat. In the embodiment provided by the invention, in order to reduce the value of THD, in a new period, the main switching tube MS is turned on at the time b, and the on time becomes t _ old + Δ t, so as to compensate for the average current error caused by the negative current. As shown in fig. 6, in the embodiment of the present invention, the average current Iavg ═ (VIN ═ old + Δ t)/L-Ineg)/2. Due to the fact thatWhen VIN>At VOUT/2, Ineg is found by calculation<<VIN (t _ old + Δ t)/L, and since Ineg is small, Δ t time is also short. Therefore Iavg ≈ VIN ≈ t _ old/(2 ≈ L). When VIN<At VOUT/2, the valley is clamped to-1V due to the large resonance amplitude of the node SW, where Ineg is approximately equal to VIN Δ t/L, and Iavg is approximately equal to VIN t old/(2L). Through compensation, Iavg is in direct proportion to the input voltage VIN, thereby ensuring that the voltage Iavg is different from the input voltage VINThe THD value is excellent under the conditions of input voltage and different load currents, namely the THD value is low.
Fig. 7 is a circuit diagram of an embodiment of the PFC control circuit 10 in fig. 4. In the embodiment shown in fig. 7, the PFC control circuit 10 includes a first voltage determination module 101, a valley voltage determination module 102, a compensation time generation module 103, a constant on-time generation module 104, a time superposition circuit 105, and a control module 106.
The first voltage determining module 101 receives a node voltage sampling signal VSW _ sen of the node voltage VSW, and generates a timing start indication signal Tstart according to the node voltage sampling signal VSW _ sen. In one embodiment, the first voltage determining module 101 determines the magnitudes of the node voltage VSW and the input voltage VIN according to the node voltage sampling signal VSW _ sen, and the start timing indication signal Tstart is used to indicate whether the node voltage VSW is equal to the input voltage VIN. In one embodiment, the start timing indication signal Tstart is a high-low logic level signal having an active state and an inactive state. In one embodiment, the logic low level is an active state of the start timing indicator signal Tstart. For example, when the start timing indication signal Tstar changes from an inactive state (e.g., a logic high level) to an active state (e.g., a logic low level), it indicates that the node voltage VSW is equal to the input voltage VIN.
The valley voltage determining module 102 receives the node voltage sampling signal VSW _ sen and generates a timing end indication signal Tend according to the node voltage sampling signal VSW _ sen. In one embodiment, the valley voltage determining module 102 determines whether the node voltage VSW reaches the lowest valley value according to the node voltage sampling signal VSW _ sen, and the end-of-timing indication signal Tend is used to indicate that the node voltage VSW reaches the lowest valley value. In one embodiment, the end-of-timing indication signal Tend is a high-low logic level signal having an active state and an inactive state. In one embodiment, the logic high level is an active state of the end-of-timing indication signal Tend. For example, when the end-of-timing indication signal Tend changes from an inactive state (e.g., a logic low level) to an active state (e.g., a logic high level), it indicates that the node voltage VSW reaches the lowest valley value.
The compensation time generation module 103 receives the timing start indication signal Tstar and the timing end indication signal Tend, and generates a compensation time signal Δ T according to the timing start indication signal Tstar and the timing end indication signal Tend. In one embodiment, the compensation time signal Δ T represents a time period (a time period Δ T shown in fig. 6) from a time when the chronograph start instruction signal Tstar becomes active from inactive to a time when the chronograph end instruction signal Tend becomes active from inactive, as the THD compensation time period. In one embodiment, the compensation time generation module 103 includes a timer that starts counting at the time when the timing start indication signal Tstar changes from inactive to active and ends counting at the time when the timing end indication signal Tend changes from inactive to active. In one embodiment, the compensated time signal Δ T includes a high-low logic level signal having an active state and an inactive state, and the logic high level is the active state of the compensated time signal Δ T.
The constant on-time generation module 104 generates a constant on-time signal T _ old. In one embodiment, the constant on-time signal T _ old represents a constant on-time of the main switch tube MS preset by the system according to the parameters (as shown in fig. 6, time T _ old). In one embodiment, the constant on-time signal T _ old comprises a high-low logic level signal having an active state and an inactive state. In one embodiment, the logic high level is the active state of the constant on-time signal T _ old. In one embodiment, the main switch tube MS is turned off when the constant on-time signal T _ old changes from an inactive state (e.g., logic low level) to an active state (e.g., logic high level).
The time superposition circuit 105 receives the compensated time signal Δ T and the constant on-time signal T _ old, and superposes the compensated time signal Δ T and the constant on-time signal T _ old to generate the on-time signal TON. In one embodiment, the on-time signal TON represents the sum of the preset constant on-time t _ old of the main switch tube MS and the THD compensation time Δ t. In one embodiment, the time superimposing circuit 105 includes a logic circuit.
The control module 106 receives the timing end indication signal Tend and the on-time signal TON, and generates a main switching tube control signal CTL to control on and off switching of the main switching tube MS according to the timing end indication signal Tend and the on-time signal TON. In one embodiment, the control module 106 includes an RS flip-flop, a set terminal S of which receives the timing end indication signal Tend, a reset terminal R of which receives the on-time signal TON, and the RS flip-flop outputs the control signal CTL at an output terminal Q. When the timing end indication signal Tend is changed from invalid to valid, the control signal CTL controls the main switching tube MS to be conducted; when the on-time signal TON changes from invalid to valid, the control signal CTL controls the main switching tube MS to turn off.
Fig. 8 is a circuit diagram of another embodiment of the PFC control circuit 10 of fig. 4. In the embodiment shown in fig. 8, the first voltage judging module 101, the valley voltage judging module 102 and the control module 106 are unchanged, and the compensation time generating module 103, the constant on-time generating module 104 and the time superimposing circuit 105 are replaced with the on-time generating circuit 107. That is, the on-time generation circuit 107 receives the timing start instruction signal Tstar and the timing end instruction signal Tend, and generates an on-time signal TON based on the timing start instruction signal Tstar and the timing end instruction signal Tend.
Fig. 9 is a schematic circuit diagram of an embodiment of the first voltage determining module 101 in the embodiments of fig. 7 and 8. In the embodiment shown in fig. 9, the first voltage determining module 101 includes a filter circuit 1011 and a comparator circuit 1012.
The filtering circuit 1011 receives the node voltage sampling signal VSW _ sen and filters the node voltage sampling signal VSW _ sen to generate the input voltage sampling signal VIN _ sen. In one embodiment, the input voltage sampling signal VIN _ sen represents a sampled value of the input voltage VIN. In one embodiment, the filter circuit 1011 includes a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are coupled in series between the output of the node voltage sampling circuit and the reference ground. The common node of the resistor R1 and the capacitor C1 provides the input voltage sampling signal VIN _ sen.
The comparing circuit 1012 receives the node voltage sampling signal VSW _ sen and the input voltage sampling signal VIN _ sen, and compares the node voltage sampling signal VSW _ sen with the input voltage sampling signal VIN _ sen to generate the timing start indication signal Tstar. In one embodiment, the comparison circuit 1012 includes a voltage comparator COM1 having a non-inverting input receiving the node voltage sampling signal VSW sen and an inverting input receiving the input voltage sampling signal VIN sen. When the node voltage sampling signal VSW _ sen decreases to the input voltage sampling signal VIN _ sen, the start timing indication signal Tstar changes from a logic high level to a logic low level.
Fig. 10 is a schematic circuit diagram of an embodiment of the valley voltage determining module 102 in the embodiments of fig. 7 and 8. In the embodiment shown in fig. 10, the valley voltage determining module 102 includes a switch M1, a resistor R2, a capacitor C2, and a comparator 1021.
The switch tube M1 has a first end, a second end and a control end. A first end of the switch tube M1 is coupled to a common node of the resistor R1 and the capacitor C1; the second end of the switch tube M1 is coupled to the reference ground; the control terminal of the switch transistor M1 receives the main switch transistor control signal CTL. The resistor R2 and the capacitor C2 are coupled in series between the output of the node voltage sampling circuit and the reference ground. The common node of resistor R2 and capacitor C2 provides the valley voltage signal Vvalley. In the embodiment shown in fig. 10, the switch transistor M1 is illustrated as an NMOS transistor, and in other embodiments, the switch transistor M1 may be illustrated as other types of controllable semiconductor devices.
The comparator circuit 1021 has a first terminal receiving the valley bottom voltage signal Vvalley, a second terminal electrically connected to a reference ground, and an output terminal, and the comparator circuit 1021 compares the potentials of the valley bottom voltage signal Vvalley and the reference ground to generate an end-of-timing indication signal Tend. In one embodiment, the comparison circuit 1021 comprises a voltage comparator COM2 having a non-inverting input that receives the valley voltage signal Vvalley and an inverting input that is electrically connected to a ground reference. When the valley voltage signal Vvalley is positive, indicating that the node voltage VSW has reached the valley value, the end-of-timing indication signal Tend changes from a logic low level to a logic high level.
Fig. 11 is a schematic circuit diagram of an embodiment of the on-time generation circuit 107 of the embodiment of fig. 8. In the embodiment shown in fig. 11, the on-time generating circuit 107 includes a switching tube M2, a switching tube M3, a switching tube M4, a switching tube M5, a capacitor C3, a capacitor C4, a capacitor C5, a current source I1, a current source I2, a current source I3, an inverter 1071, a comparing circuit 1072, and a comparing circuit 1073.
As shown in fig. 11, a current source I1 and a capacitor C3 are coupled in series between the power supply VCC and ground.
The switch tube M2 has a first end, a second end and a control end. A first terminal of the switch tube M2 is coupled to a common node of the current source I1 and the capacitor C3; the second end of the switch tube M2 is coupled to the reference ground; the control terminal of the switch transistor M2 receives the end-of-timing indication signal Tend through the inverter 1071.
The switch tube M3 has a first end, a second end and a control end. A first terminal of the switching tube M3 is coupled to the current source I1; the second end of the switch tube M3 is coupled to one end of the capacitor C4; the control end of the switch tube M3 receives a timing end indicating signal Tend; the other end of the capacitor C4 is connected to a reference ground.
The switch tube M4 has a first end, a second end and a control end. The first end of the switch tube M4 is coupled to the second end of the switch tube M3; the second end of the switching tube M4 is connected to the reference ground; the control terminal of the switching tube M4 receives the timing start indication signal Tstar.
The comparison circuit 1072 has a first terminal receiving the voltage signal V3 at the first terminal of the switch transistor M2, a second terminal receiving the voltage signal V4 at the first terminal of the switch transistor M4, and an output terminal, and the comparison circuit 1072 compares the voltage signal V3 with the voltage signal V4 to generate the comparison signal CT. In one embodiment, the comparison circuit 1072 includes a voltage comparator COM3 having a non-inverting input receiving the voltage signal V4 and an inverting input receiving the voltage signal V3.
The current source I3 and the capacitor C5 are coupled in series between the power supply VCC and the ground reference. The switch tube M5 has a first end, a second end and a control end. A first terminal of the switch tube M5 is coupled to a common node of the current source I3 and the capacitor C5; the second end of the switch tube M5 is coupled to the reference ground; the control terminal of the switching tube M5 receives the comparison signal CT.
The comparison circuit 1073 has a first terminal receiving the voltage signal V5 at the first terminal of the switch transistor M5, a second terminal receiving the constant voltage signal VD, and an output terminal, wherein the comparison circuit 1073 compares the voltage signal V5 with the constant voltage signal VD to generate the on-time signal TON. In one embodiment, the comparison circuit 1073 includes a voltage comparator COM4 having a non-inverting input receiving the voltage signal V5 and an inverting input receiving the fixed voltage signal VD.
In the embodiment shown in fig. 11, during the time when the start timing indication signal Tstar is high, the switch M4 is turned on, the comparison signal CT is logic high, the switch M5 is turned on, and the on-time signal TON is kept logic low. When the falling edge of the timing start indication signal Tstar approaches, the switch M4 is turned off, and the current source I2 charges the capacitor C4 through the switch M3. When the timing of the rising edge of the end-of-timer indication signal Tend comes, the switching tube M3 is turned off, and the voltage signal V4 remains unchanged. At the same time, the switch M2 is turned off, the current source I1 starts to charge the capacitor C3, and the voltage signal V3 is stepped up. When the voltage signal V3 rises to the value of the voltage signal V4, the comparison signal CT changes to logic low, the switching tube M5 is turned off, the current source I3 starts to charge the capacitor C5, and the voltage signal V5 increases gradually. When the voltage signal V5 rises to the value of the fixed voltage signal VD, the on-time signal TON becomes logic high and the main switching tube MS will be turned off.
In the embodiment shown in fig. 11, the switching transistors M2, M4 and M5 are illustrated as NMOS transistors, the switching transistor M3 is illustrated as PMOS transistors, and in other embodiments, the switching transistors M2-M5 can be illustrated as other suitable types of controllable semiconductor devices.
While the present invention has been described with reference to several exemplary embodiments, those skilled in the relevant art will appreciate that fig. 9-11 symbolically illustrate one specific embodiment of the first voltage determining module 101, the valley voltage determining module 102, and the on-time generating circuit 107, respectively, and that the terms used in the disclosed embodiments are illustrative and exemplary, not limiting, and are used only to describe particular embodiments and not to limit the present invention. Furthermore, various modifications in form and detail of the disclosed embodiments of the invention may occur to those skilled in the art without departing from the spirit and concept of the invention and, therefore, such modifications are intended to be included within the scope of the present invention as defined in the appended claims and their equivalents.
Claims (10)
1. A control method for a power factor correction circuit, wherein the power factor correction circuit comprises a master switch tube and a slave switch tube, the control method comprises the following steps:
sampling node voltages on common nodes of a main switching tube and a slave switching tube;
judging whether the node voltage is equal to the input voltage of the power factor correction circuit or not;
when the node voltage is equal to the input voltage, starting timing;
judging whether the node voltage is reduced to a minimum value;
when the node voltage is reduced to the minimum value, the main switching tube is conducted, timing is stopped, and compensation time is generated, wherein the compensation time is the time difference between the start timing and the end timing; and
and after the main switching tube is controlled to be conducted for preset fixed conduction time and compensation time, the main switching tube is turned off.
2. A control method for a power factor correction circuit, wherein the power factor correction circuit comprises a master switch tube and a slave switch tube, the control method comprises the following steps:
when the node voltage on the common node of the main switch tube and the slave switch tube is reduced to the lowest value, the main switch tube is conducted;
generating a compensation time, wherein the compensation time is a time difference between a moment when the node voltage drops to the input voltage of the power factor correction circuit and a moment when the node voltage drops to a lowest value; and
and the main switching tube is switched off after the main switching tube is controlled to be switched on for preset fixed on-time and compensation time.
3. A control circuit for a power factor correction circuit, comprising:
the first voltage judging module receives a node voltage sampling signal and generates a timing start indicating signal according to the node voltage sampling signal, wherein the node voltage sampling signal represents the node voltage on a common node of a main switching tube and a slave switching tube in the power factor correction circuit, and the timing start indicating signal is used for indicating whether the node voltage is equal to the input voltage of the power factor correction circuit or not;
the valley voltage judging module is used for receiving the node voltage sampling signal and generating a timing end indicating signal according to the node voltage sampling signal, wherein the timing end indicating signal is used for indicating whether the node voltage is reduced to the lowest value or not;
the on-time generating circuit receives the timing start indicating signal and the timing end indicating signal and generates an on-time signal according to the timing start indicating signal and the timing end indicating signal;
and the control module receives the timing end indication signal and the conduction time signal and generates a main switching tube control signal according to the timing end indication signal and the conduction time signal, wherein the main switching tube control signal is used for controlling the on-off switching of the main switching tube.
4. The control circuit of claim 3, wherein the first voltage determining module comprises:
the filter circuit receives the node voltage sampling signal and filters the node voltage sampling signal to generate an input voltage sampling signal, wherein the input voltage sampling signal represents input voltage; and
and the first comparison circuit receives the node voltage sampling signal and the input voltage sampling signal, compares the node voltage sampling signal with the input voltage sampling signal and generates the timing starting indication signal.
5. The control circuit of claim 3, wherein the valley voltage determining module comprises:
a first end of the first capacitor receives the node voltage sampling signal;
a first resistor, a first end of the first resistor being coupled to a second end of the first capacitor, a second end of the first resistor being electrically connected to a reference ground, wherein a common node of the first resistor and the first capacitor provides a valley bottom voltage signal;
the first end of the first switch tube is coupled with a common node of the first resistor and the first capacitor, the second end of the first switch tube is electrically connected with the reference ground, and the control end of the first switch tube receives a control signal of the main switch tube; and
and the first end of the second comparison circuit receives the valley voltage signal, the second end of the second comparison circuit is electrically connected with a reference ground, and the second comparison circuit compares the valley voltage signal with the potential of the reference ground to generate a timing end indication signal.
6. The control circuit of claim 3, wherein the on-time generating circuit comprises a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a second capacitor, a third capacitor, a fourth capacitor, a first current source, a second current source, a third comparing circuit and a fourth comparing circuit, wherein,
the first current source and the second capacitor are coupled between the power supply and the reference ground in series;
the second current source and the third capacitor are coupled in series between the power supply and the reference ground through a third switching tube, and the control end of the third switching tube receives a timing end indication signal;
the third current source and the fourth capacitor are coupled between the power supply and the reference ground in series;
a first end of the second switch tube is coupled with a common end of the second capacitor and the first current source, a second end of the second switch tube is electrically connected with a reference ground, and a control end of the second switch tube receives a timing end indication signal through the phase inverter;
a first end of the fourth switching tube is coupled with a common end of the third capacitor and the second current source, a second end of the fourth switching tube is electrically connected with the reference ground, and a control end of the fourth switching tube receives a timing start indication signal;
the first end of the third comparison circuit is coupled with the first end of the second switch tube, the second end of the second comparison circuit is coupled with the first end of the fourth switch tube, and a comparison signal is generated at the output end;
a first end of the fifth switching tube is coupled to a common end of the fourth capacitor and the third current source, a second end of the fifth switching tube is electrically connected to the reference ground, and a control end of the fifth switching tube receives the comparison signal; and
the first end of the fourth comparison circuit is coupled to the first end of the fifth switch tube, and the second end of the fourth comparison circuit receives the fixed voltage signal and generates a conduction time signal at the output end.
7. The control circuit of claim 3, wherein the control module comprises:
and the RS trigger is provided with a set end for receiving the timing start indication signal, a reset end for receiving the conduction time signal and an output end for generating a main switching tube control signal.
8. The control circuit of claim 3, wherein the on-time generating circuit comprises:
the compensation time generation module receives the timing start indication signal and the timing end indication signal and generates a compensation time signal according to the timing start indication signal and the timing end indication signal;
the constant conduction time generation module generates a constant conduction time signal; and
and the time superposition circuit receives the compensation time signal and the constant conduction time signal, and superposes the compensation time signal and the constant conduction time signal to generate a conduction time signal.
9. The control circuit of claim 8, wherein the compensated time signal represents a time period between a time when the timing start indication signal becomes active from inactive to a time when the timing end indication signal becomes active from inactive.
10. The control circuit of claim 3, further comprising a sampling circuit for sampling a node voltage at a common node of the master and slave switching tubes and generating a node voltage sampling signal.
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