CN114636912A - High-speed switch protection circuit for dynamic test of power device - Google Patents
High-speed switch protection circuit for dynamic test of power device Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2608—Circuits therefor for testing bipolar transistors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
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Abstract
The invention relates to a high-speed switch protection circuit for dynamically testing a power device, which comprises a first device to be tested Q1, a first diode to be tested D1, a load inductor L, a bus power supply Vbus, a test pulse generator P2 and a digital storage oscilloscope DSO, wherein the first diode to be tested D1 is connected with the bus power supply Vbus; the bus power supply Vbus is grounded through a high-speed switch module, a load inductor L and a first device to be tested Q1 which are connected in series, the load inductor L is connected with a first diode to be tested D1 in parallel, the positive electrode of the first diode to be tested D1 is connected with the collector of the first device to be tested Q1, the grid and the emitter of the first device to be tested Q1 are connected with a test pulse generator P2, and a digital storage oscilloscope DSO detects the voltage and the current of the first device to be tested Q1; the high-speed switch module is used for controlling connection or microsecond level disconnection of the power supply of the bus power supply Vbus before and after the test double pulse of the test pulse generator P2. The invention removes the high-voltage power supply of the bus within microsecond time after the test pulse is finished, and ensures that the power module is not over-current burnt.
Description
Technical Field
The invention relates to the technical field of semiconductor testing, in particular to a high-speed switch protection circuit for dynamic testing of a power device.
Background
In the testing stage of the power semiconductor product, a double-pulse testing method is generally adopted to realize dynamic electrical parameter testing of the product, such as switch delay, reverse recovery, safe working area and other various performances.
The common dynamic test configuration comprises a measuring instrument (mainly comprising a digital storage oscilloscope, a pulse generator and a digital direct current power supply) and a product test circuit board, wherein a product pin connector, a power supply, a DC capacitor wiring terminal, a load inductor, a pulse signal input terminal, an oscilloscope measuring terminal, a current measuring coil and the like are arranged on the test circuit board, and the dynamic parameter test process is completed through manual triggering or program control.
The specific test circuit is shown in fig. 1, a large-capacity charge-discharge capacitor Cap is used as a high-voltage test power supply to provide a bus voltage Vbus, a load inductor L and a device to be tested DUT are connected in series at two ends of the high-voltage test power supply, a diode to be tested D is connected in parallel at two ends of the load inductor L, a Pulse generator is connected to a gate and a emitter of the device to be tested DUT, an input end of a digital storage oscilloscope DSO is connected to an oscilloscope measurement terminal and a current measurement coil of the device to be tested DUT, and the oscilloscope measurement terminal and the current measurement coil are respectively connected to a measurement conduction voltage Vce and a conduction current Ice.
During testing, referring to the waveform timing chart of fig. 2, Vbus is continuously supplied to the high-voltage test power supply collecting point TP, and a first Pulse 1st Pulse and a second Pulse 2nd Pulse are shown on a double-Pulse waveform Vge of the Pulse generator. When the pulse is not driven, the DUT (device under test) is cut off, Vce is in a high-voltage cut-off state, and the Ice has no current passing through. When the first pulse 1st pulse occurs, the device to be tested DUT is turned on, Vce is turned on to form a low-voltage state, Ice has a current generated, and under the action of the load inductor L, Ice is increased in a linear state and continues until the first pulse 1st pulse ends. The first pulse 1st pulse allows Ice to increase to the current condition required for testing, then turns off, and returns to the original off state, at which time the turn-off characteristic of the DUT under a specific current-voltage condition can be measured. Since the low-resistance on state of the first pulse 1st pulse is turned off, the current of the load inductor L freewheels through the diode D to be measured. When the second pulse 2nd pulse occurs, the device to be tested DUT is turned on again to form low-voltage conduction, Vce is conducted to form a low-voltage state, Ice includes the load inductor L current and the reverse recovery current of the diode to be tested D, and Ice continues to increase in a linear state. At this time, the turn-on characteristic of the device under test DUT at a specific voltage and current and the reverse recovery characteristic of the diode under test D at a specific voltage and current can be measured. After the last two pulses are finished, the high-voltage bus voltage Vbus is continuously provided at the point TP, Vce is kept in a high-voltage cut-off state, and the Ice has no current passing through.
The pulse duration (dynamic power duration) of the dynamic test of the power device is mostly tens of microseconds to tens of microseconds, and a few products can reach one hundred microseconds. The failure process of the power device usually occurs in a time range of about ten microseconds before and after the end of the pulse. About ten microseconds after failure occurs, as the high voltage Vbus provided on the bus is always maintained, the power device is subjected to rapid overcurrent breakdown and accompanied by sound of explosion, and a large-area fusion burn area is formed on the surface of the power device, which is a common phenomenon in the current dynamic test. As shown in FIG. 3, A is the test double pulse waveform, B is the Vce waveform of the device under test DUT, and C is the Ice waveform of the device under test DUT. After the second pulse 2nd pulse is finished, the power device breaks down, Vce fluctuates abnormally, the Ice waveform grows abnormally, and the power device is burnt out due to overcurrent. The device structure in the melting area is seriously damaged, the defect problem of the device is melted, and effective failure analysis can not be carried out.
Therefore, in order to solve the above technical problems, it is necessary to provide a high-speed switch protection circuit for dynamic testing of a power module, so as to overcome the defects in the prior art.
Disclosure of Invention
The invention aims to provide a high-speed switch protection circuit for dynamic testing of a power device, which can remove high-voltage power supply of a bus within microsecond time before and after the end of a test pulse and ensure that a power module cannot be burnt out due to overcurrent caused by parameter failure.
In order to achieve the purpose, the invention adopts the following technical scheme:
a high-speed switch protection circuit for dynamically testing a power device comprises a first device to be tested Q1, a first diode to be tested D1, a load inductor L, a bus power supply Vbus, a test pulse generator P2 and a digital storage oscilloscope DSO;
the bus power supply Vbus is grounded through a high-speed switch module, a load inductor L and a first device to be tested Q1 which are connected in series, the load inductor L is connected with a first diode to be tested D1 in parallel, the positive electrode of the first diode to be tested D1 is connected with the collector of the first device to be tested Q1, the grid and the emitter of the first device to be tested Q1 are connected with a test pulse generator P2, and a digital storage oscilloscope DSO detects the voltage and the current of the first device to be tested Q1;
the high-speed switch module controls the power supply of the bus power supply Vbus to be connected before the test double pulse of the test pulse generator P2 is generated, and the power supply of the bus power supply Vbus is cut off in microsecond level after the test double pulse is completed.
The high-speed switch module comprises an off-line switch unit, wherein the off-line switch unit comprises a switch pulse generator P1, an off-line power device Q3, an off-line floating power supply, an off-line coupler OC1 and an off-line amplifier A1; a collector of the off-line power device Q3 is connected with a bus power supply Vbus, and an emitter of the off-line power device Q3 is connected with a load inductor L; the input end of the off-line coupler is connected with a direct-current power supply Vdd and the switching pulse generator P1, and the output end of the off-line coupler OC1 is connected with the off-line floating power supply and the emitter of the off-line power device Q3; while the offline floating power supply is connected to the gate of offline power device Q3 through offline amplifier a 1.
The high-speed switch module further comprises a bypass switch unit, wherein the bypass switch unit comprises a bypass power device Q4, a bypass direct-current power supply, a bypass coupler OC2, a trigger delay controller T and a bypass amplifier A2; the collector of the bypass power device Q4 is connected to the emitter of the offline power device Q3, and the emitter of the bypass power device Q4 is grounded; the input end of the bypass coupler OC2 is connected with a direct-current power supply Vdd and the switching pulse generator P1, and the output end of the bypass coupler OC2 is connected with the bypass direct-current power supply and the emitter of the bypass power device Q4; meanwhile, the bypass direct current power supply is connected to the gate of the bypass power device Q4 through a series connection triggering delay controller T and a bypass amplifier A2 in sequence.
And the bus power supply Vbus is grounded through a plurality of filter capacitors connected in parallel.
The test pulse generator P2 is triggered by the switching pulse generator P1.
The device comprises a first device to be tested Q2, a first diode D1 to be tested is connected with a second device to be tested Q2 in parallel, a collector of the second device to be tested Q2 is connected with the cathode of the first diode D1, an emitter of the second device to be tested Q2 is connected with the anode of the first diode D1, and a grid electrode and the emitter of the second device to be tested Q2 are in short circuit.
The first device to be tested Q1 is connected in parallel with the second diode to be tested D2, the anode of the second diode to be tested D2 is connected with the emitter of the first device to be tested Q1, and the cathode of the second diode to be tested D2 is connected with the collector of the first device to be tested Q1.
And the power supply capacitor Cap is connected with the bus power supply Vbus in parallel.
The first device to be tested Q1 is one of an insulated gate bipolar transistor IGBT, a field effect transistor MOSFET, a silicon carbide field effect transistor SiC-MOSFET and a gallium nitride field effect transistor GaN-MOSFET.
The second device to be tested Q2 is one of an insulated gate bipolar transistor IGBT, a field effect transistor MOSFET, a silicon carbide field effect transistor SiC-MOSFET and a gallium nitride field effect transistor GaN-MOSFET.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, the high-speed switch module is inserted into the double-pulse test circuit of the power device, and the power supply removal of the microsecond bus power supply Vbus is realized through the synchronization of the driving pulse time sequence, so that the overcurrent burning of the tested power device caused by abnormal parameters is effectively avoided, and the method is very suitable for the analysis test of power products.
The test pulse can be triggered by the switch pulse, the pulse time sequence can be synchronously aligned, the bus power supply can be removed at any time point of the test pulse duration, and the power supply can be quickly cut off at the position where the waveform is abnormal.
Furthermore, the high-speed switch module comprises an off-line switch unit and a bypass switch unit, and when the off-line switch unit cuts off the power supply of the bus power supply Vbus, the bypass switch unit is used for forcibly grounding the test power supplies at two ends of the first to-be-tested device Q1 and the first to-be-tested diode D1, so that the evacuation of high-voltage test voltage is further ensured.
The invention is also suitable for overcurrent protection in the batch test process, and avoids the measurement device and the product from being impacted by overcurrent.
Drawings
FIG. 1 is a schematic diagram of a prior art circuit;
FIG. 2 is a waveform timing diagram of the prior art;
fig. 3 is a prior art digital storage oscilloscope display.
FIG. 4 is a schematic circuit diagram of a preferred embodiment of the present invention;
FIG. 5 is a circuit diagram of a high speed switch module according to a preferred embodiment of the present invention;
FIG. 6 is a waveform timing diagram of the preferred embodiment of the present invention;
fig. 7 is a digital storage oscilloscope display screen according to another embodiment of the present invention.
FIG. 8 is a circuit diagram illustrating two sets of power devices after being switched according to a preferred embodiment of the present invention.
Detailed Description
The technical solution of the present invention is explained in further detail with reference to the accompanying figures 4-7 of the specification.
The preferred embodiment of the present invention is exemplified by an insulated gate bipolar transistor IGBT. Meanwhile, due to the production and manufacturing specifications, two groups of power devices are often integrated in one semiconductor finished product, and each of the two groups of power devices is an IGBT and is connected with a diode D in parallel, such as the first group of power devices DUT1 and the second group of power devices DUT2 in fig. 4. Therefore, the test circuit is designed by using two sets of arrangement characteristics in the embodiment. In each test, the first device under test Q1 of the first group of power devices DUT1 and the first diode under test D1 of the second group of power devices DUT2 are actually tested, and after the lines are switched, the second device under test Q2 of the second group of power devices DUT2 and the second diode under test D2 of the first group of power devices DUT1 can be tested, so that the test flexibility is high. One of the test states is described below as an example.
A high-speed switch protection circuit for dynamic testing of a power device relates to a high-speed switch module 1, a first device Q1 to be tested, a first diode D1 to be tested, a load inductor L, a bus power supply Vbus, a test pulse generator P2, a switch pulse generator P1 and a digital storage oscilloscope DSO. The components not actually participating in the test operation include the second device under test Q2 and the second diode under test D2. In the package, the first device to be tested Q1 and the second diode to be tested D2 form a group of power devices, and the second device to be tested Q2 and the first diode to be tested D1 form a second group of power devices.
And a bus power supply Vbus provides high-voltage test power supply, and a power supply capacitor Cap with larger capacity is adopted. As shown in fig. 4, the bus power Vbus is grounded through the high-speed switch module 1, the load inductor L, and the first device to be tested Q1 connected in series. The first diode D1 to be tested is connected in parallel with the load inductor L, specifically, the positive electrode of the first diode D1 is connected to the collector of the first device Q1 to be tested, and the negative electrode of the first diode D1 is connected to the high-speed switch module 1. When the current in the load inductor L flows from the high-speed switch module 1 to the first dut Q1, the first dut D1 is turned off and not turned on. Meanwhile, the grid electrode and the emitter electrode of the first device to be tested Q1 are connected with the test pulse generator P2, the test pulse generator P2 sends pulses to provide grid electrode turn-on voltage for the first device to be tested Q1, and the first device to be tested Q1 works. After the pulse of the test pulse generator P2 is removed, the gate and the emitter of the first device to be tested Q1 are not pressed, and the first device to be tested Q1 is turned off. The DSO collects data and waveforms of each test point in the test process and displays the data and waveforms. A voltage measurement terminal is usually designed directly on the product of the first device Q1 to read and observe the turn-on voltage Vce at the gate and emitter of the first device Q1 after being connected to the DSO input terminal of the digital storage oscilloscope. And current measuring coils are arranged on the grid electrode and the emitter electrode of the first device to be tested Q1, and signals of the current measuring coils are also connected to the input end of the digital storage oscilloscope DSO to detect the conduction current Ice of the first device to be tested Q1.
The high-speed switch module 1 is a switch module, and realizes flexible switching of two states of power supply connection and disconnection of a control bus power supply Vbus. In the scheme of the invention, a high-speed switch module 1 is a microsecond switch device, the microsecond switch device is used for instantly controlling on-off within 2-3 microseconds, and the response time of about 1 microsecond can be usually achieved. The high speed switch module 1 in this embodiment comprises an offline switch unit 11 and a bypass switch unit 12, as shown in fig. 4. The main core components in the two units generally adopt power devices, the power devices with the same specification as the device to be tested can be selected, and the power devices with the specification higher than that of the device to be tested can also be adopted.
The offline switching unit 11 includes a switching pulse generator P1, an offline power device Q3, a ± 15V offline floating power supply, an offline coupler OC1, and an offline amplifier a 1. The bypass switching cell 12 includes a bypass power device Q4, a 15V dc voltage, a bypass coupler OC2, a trigger delay controller T, and a bypass amplifier a 2. Referring to fig. 5, the collector of the offline power device Q3 is connected to the bus power supply Vbus, and the emitter is connected to the load inductor L, so that the offline power device Q3 is connected between the bus power supply Vbus and the load inductor L. The control of the off-line power device Q3 is implemented by the switching pulse generator P1. The input end of the off-line coupler OC1 is connected with the direct current power supply Vdd and the switching pulse generator P1, and the output end of the off-line coupler OC1 is connected with the +/-15V off-line floating power supply and the emitter of the off-line power device Q3. While a 15V offline floating power supply is connected to the gate of offline power device Q3 through offline amplifier a 1. Since the emitter of the off-line power device Q3, i.e. the voltage at the point TP in the figure, provides the test supply voltage, and is not grounded, the control terminal of the off-line power device Q3 needs to be coupled with the ± 15V off-line floating power source through the switch pulse generator P1 to form a floating pulse, so as to drive the off-line power device Q3 to be turned on. After the off-line power device Q3 is conducted, a bus power supply Vbus is obtained at a TP point to supply power for test work. When the test is finished, the pulse of the switching pulse generator P1 is removed, the off-line power device Q3 is disconnected, and no power supply voltage is arranged at a TP point, so that the first device to be tested Q1 is separated from a high-voltage state, and the breakdown of the device is effectively prevented.
In the present embodiment, the bypass switch unit 12 assists the offline switch unit 11, and further grounds the voltage at the TP point to zero when the offline switch unit 11 turns off the power supply at the TP point. The collector of bypass power device Q4 is connected to the emitter of offline power device Q3, i.e., the TP point where the test voltage is provided, and the emitter of bypass power device Q4 is grounded, thus connecting bypass power device Q4 between the TP point and ground. As long as the bypass power device Q4 is conducted, the TP point is forcibly grounded, the high-voltage power supply is completely lost, and the first device to be tested Q1 in the test circuit is further protected from being separated from the high-voltage state. The control terminal of the bypass power device Q4 is also driven by a switching pulse generator P1. The input end of the bypass coupler OC2 is connected with the direct current power supply Vdd and the switching pulse generator P1, and the output end of the bypass coupler OC2 is connected with the 15V bypass direct current power supply and the emitter of the bypass power device Q4. Meanwhile, a 15V bypass direct-current power supply is connected to the grid electrode of a bypass power device Q4 through a trigger delay controller T and a bypass amplifier A2 which are connected in series, and the collector electrode of a bypass power device Q4 is connected to the emitter electrode of an off-line power device Q3.
The operation state of the bypass switching unit 12 is opposite to that of the offline switching unit 11. When the off-line power device Q3 is turned on, the bypass power device Q4 needs to be turned off and does not work, so that power is normally supplied at the TP point, and the test circuit performs a test. When the off-line power device Q3 is cut off, the power supply of the bus power supply Vbus is lost at the TP point, the bypass power device Q4 is conducted at the moment, the TP point is further grounded, and the first device to be tested Q1 is effectively protected. Therefore, in the opposite working state, under the driving of the same switching pulse generator P1, a trigger delay controller T is added to implement delay control of the two unit pulses, thereby implementing pulse synchronization.
And the bus power supply Vbus is grounded through a plurality of filter capacitors connected in parallel and then connected to the off-line switch unit 11 to dry the bus voltage. In order to achieve timing synchronization of the whole test circuit, the test pulse generator P2 is triggered by the on edge of the switching pulse generator P1 in this embodiment.
As mentioned above, two sets of power devices are usually integrated on the semiconductor product, so that the first dut D1 is connected in parallel with the second dut Q2, and the first dut Q1 is connected in parallel with the second dut D2 in the actual circuit. The collector of the second device under test Q2 is connected to the cathode of the first diode under test D1, and the emitter of the second device under test Q2 is connected to the anode of the first diode under test D1. The emitter of the first device to be tested Q1 is connected to the anode of the second diode to be tested D2, and the collector of the first device to be tested Q1 is connected to the cathode of the second diode to be tested D2. That is, the diodes and the power devices in the same group are connected in parallel in an inverse manner, and then the two power devices are connected in series. In this embodiment, the emitter of the second dut Q2 is connected to the collector of the first dut Q1. The second device under test Q2 does not play a role in this test, thus shorting the gate and emitter of the second device under test Q2. The second dut D2 connected in parallel with the first dut Q1 does not affect the testing operation and therefore does not perform any processing.
At the beginning of actual test, referring to fig. 6, when there is no test pulse, the high-speed switch module 1 is initially in an off state, the TP point voltage is zero, the first device under test Q1 does not operate, Vce is zero, and there is no Ice passing through at the same time. Before the first pulse 1st pulse comes, the switching pulse generator P1 in the high-speed switching module 1 generates a driving pulse, the offline power device Q3 in the offline switching unit 12 is turned on, and at this time, the power is supplied to the bus power Vbus at the point TP, and the off state is a high voltage state, and the first device to be tested Q1 is called a high voltage off state because the first pulse 1st pulse is not yet driven, and is not turned on and is not provided with Ice. When the first pulse 1st pulse occurs, the first device under test Q1 is turned on, Vce is at a low voltage, and at this time, the first device under test Q1 starts to have a current flowing through, and the on-current Ice increases linearly under the action of the load inductor L. After the first pulse 1st pulse continues for a while, the first device to be tested Q1 is turned off again, Vce is at high voltage, and there is no Ice. And the current in the load inductor L freewheels to the first diode D1 to be tested. Then, a second pulse 2nd pulse occurs, the first dut Q1 is turned on, Vce is at a low voltage, Ice simultaneously passes through the reverse current of the first dut D1 and the current of the load inductor L, and the linear state of Ice continues to increase on the basis that the previous state slightly falls back. When the second pulse 2nd pulse is finished, the first device to be tested Q1 is cut off, Vce is in high voltage and does not have Ice, the process is controlled to be 1-2 microseconds, the pulse of a switch pulse generator P1 in the high-speed switch module 1 is evacuated, the off-line power device Q3 is cut off at the moment, the TP point is disconnected with a bus power supply Vbus, and power supply is lost, so that the high voltage is not applied to the test circuit, the Vce on the first device to be tested Q1 is in low voltage, the Ice is also zero, and the first device to be tested Q1 enters a rest protection state to prevent the high-current breakdown phenomenon after the test pulse is evacuated.
It can be seen from the timing diagram that, under the protection of the high-speed switch module 1, the TP point is supplied with power by the bus power Vbus only during the double-pulse generation period (the front and rear time points can be controlled by themselves, and the pulse width of the switch pulse generator P1 and the trigger time point of the test pulse generator P2 are adjusted), and in other states, the TP point is separated from the bus power Vbus, so that the safety of the device to be tested is fully protected.
Referring to fig. 7, in this embodiment, the first device under test Q1 is abnormal during the test process, where B is the Vce waveform of the first device under test Q1, C is the Ice waveform of the first device under test Q1, and D is the driving waveform of the offline switching unit 11. E represents the duration of the first pulse 1st pulse, F represents the duration of the second pulse 2nd pulse, the Vce voltage of the Q1 does not return to the position B after the first pulse is ended, the Q1 is abnormal, the Ice current continuously rises, and the voltage resistance of the Q1 at the ending edge of the first pulse 1st pulse is failed. Ice continues to rise for the duration of the second pulse 2nd pulse Q1, and the current continues to ramp after the end of the second pulse 2nd pulse. At this time, the high-speed switch module 1 of the invention responds instantaneously, the bus power supply Vbus is evacuated at 1.31 microseconds after the second pulse 2nd pulse is turned off, the first device to be tested Q1 is not burnt out by overcurrent, and the testing device is effectively protected. The time point when the high-speed switch module 1 is turned off can be flexibly adjusted by the pulse width and the triggering time point of the switch pulse generator P1.
Meanwhile, the mode of combining the off-line switch unit 11 and the bypass switch unit 12 is arranged in the high-speed switch module 1, so that the reliability of the switch is improved.
When the second device under test Q2 and the second diode under test D2 are tested, the positions of the first group of independent power devices DUT1 and the second group of independent power devices DUT2 can be exchanged in a circuit wiring mode only by switching the circuit connection position. After switching, the second dut Q2 replaces the position of the original first dut Q1, the second dut D2 replaces the position of the first dut D1, the gate and the emitter of the first dut Q1 are short-circuited, and the first dut D1 does not affect the test operation and does not perform processing, and the specific connection circuit is shown in fig. 8. The testing principle and process are the same as those described before, and thus are not described in detail.
In the invention, an insulated gate bipolar transistor IGBT, a field effect transistor MOSFET, a fast recovery diode FRD, a silicon carbide Schottky diode SiC-SBD, a silicon carbide field effect transistor SiC-MOSFET, a gallium nitride field effect transistor GaN-MOSFET and the like can be used as devices to be tested, and the universality is strong.
The above embodiments are merely preferred embodiments of the present disclosure, which are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like, which are within the spirit and principle of the present disclosure, should be included in the scope of the present disclosure.
Claims (10)
1. A high-speed switch protection circuit for dynamic testing of power devices, characterized by: the device comprises a first device to be tested Q1, a first diode to be tested D1, a load inductor L, a bus power supply Vbus, a test pulse generator P2 and a digital storage oscilloscope DSO;
the bus power supply Vbus is grounded through a high-speed switch module, a load inductor L and a first device to be tested Q1 which are connected in series, the load inductor L is connected with a first diode to be tested D1 in parallel, the positive electrode of the first diode to be tested D1 is connected with the collector of the first device to be tested Q1, the grid and the emitter of the first device to be tested Q1 are connected with a test pulse generator P2, and a digital storage oscilloscope DSO detects the voltage and the current of the first device to be tested Q1;
the high-speed switch module controls the power supply of the connected bus power supply Vbus before the test double pulse of the test pulse generator P2 is generated, and realizes microsecond-level disconnection of the power supply of the bus power supply Vbus after the test double pulse is completed.
2. A high speed switch protection circuit for dynamic testing of power devices, as recited in claim 1, wherein: the high-speed switch module comprises an off-line switch unit, wherein the off-line switch unit comprises a switch pulse generator P1, an off-line power device Q3, an off-line floating power supply, an off-line coupler OC1 and an off-line amplifier A1; a collector of the off-line power device Q3 is connected with a bus power supply Vbus, and an emitter of the off-line power device Q3 is connected with a load inductor L; the input end of the offline coupler is connected with a direct-current power supply Vdd and the switching pulse generator P1, and the output end of the offline coupler OC1 is connected with the offline floating power supply and the emitter of the offline power device Q3; while the offline floating power supply is connected to the gate of offline power device Q3 through offline amplifier a 1.
3. A high speed switch protection circuit for dynamic testing of power devices as claimed in claim 2, wherein: the high-speed switch module further comprises a bypass switch unit, wherein the bypass switch unit comprises a bypass power device Q4, a bypass direct-current power supply, a bypass coupler OC2, a trigger delay controller T and a bypass amplifier A2; the collector of the bypass power device Q4 is connected to the emitter of the offline power device Q3, and the emitter of the bypass power device Q4 is grounded; the input end of the bypass coupler OC2 is connected with a direct-current power supply Vdd and the switching pulse generator P1, and the output end of the bypass coupler OC2 is connected with the bypass direct-current power supply and the emitter of the bypass power device Q4; meanwhile, the bypass direct current power supply is connected to the gate of the bypass power device Q4 through a series connection triggering delay controller T and a bypass amplifier A2 in sequence.
4. A high speed switch protection circuit for dynamic testing of power devices, as recited in claim 1, wherein: and the bus power supply Vbus is grounded through a plurality of filter capacitors connected in parallel.
5. A high speed switch protection circuit for dynamic testing of power devices according to claim 2 or 3, wherein: the test pulse generator P2 is triggered by the switching pulse generator P1.
6. A high speed switch protection circuit for dynamic testing of power devices, as recited in claim 1, wherein: still include second device under test Q2, first device under test D1 and second device under test Q2 are parallelly connected, the negative pole of first diode under test D1 is connected to the collector of second device under test Q2, the positive pole of first diode under test D1 is connected to the projecting pole of second device under test Q2, the grid and the projecting pole short circuit of second device under test Q2.
7. A high speed switch protection circuit for dynamic testing of power devices, as recited in claim 1, wherein: the first device to be tested Q1 is connected in parallel with the second diode to be tested D2, the anode of the second diode to be tested D2 is connected with the emitter of the first device to be tested Q1, and the cathode of the second diode to be tested D2 is connected with the collector of the first device to be tested Q1.
8. A high speed switch protection circuit for dynamic testing of power devices, as recited in claim 1, wherein: and the power supply capacitor Cap is connected with the bus power supply Vbus in parallel.
9. A high speed switch protection circuit for dynamic testing of power devices as claimed in claim 1, wherein: the first device to be tested Q1 is one of an insulated gate bipolar transistor IGBT, a field effect transistor MOSFET, a silicon carbide field effect transistor SiC-MOSFET and a gallium nitride field effect transistor GaN-MOSFET.
10. A high speed switch protection circuit for dynamic testing of power devices, as recited in claim 6, wherein: the second device to be tested Q2 is one of an insulated gate bipolar transistor IGBT, a field effect transistor MOSFET, a silicon carbide field effect transistor SiC-MOSFET and a gallium nitride field effect transistor GaN-MOSFET.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115032518A (en) * | 2022-08-11 | 2022-09-09 | 佛山市联动科技股份有限公司 | Dynamic threshold voltage testing device and method |
| CN116068360A (en) * | 2023-03-24 | 2023-05-05 | 佛山市联动科技股份有限公司 | Dynamic parameter test system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115032518A (en) * | 2022-08-11 | 2022-09-09 | 佛山市联动科技股份有限公司 | Dynamic threshold voltage testing device and method |
| CN115032518B (en) * | 2022-08-11 | 2022-11-15 | 佛山市联动科技股份有限公司 | Dynamic threshold voltage testing device and method |
| CN116068360A (en) * | 2023-03-24 | 2023-05-05 | 佛山市联动科技股份有限公司 | Dynamic parameter test system |
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