CN212649096U - Transient interlocking protection circuit - Google Patents
Transient interlocking protection circuit Download PDFInfo
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- CN212649096U CN212649096U CN202021284325.4U CN202021284325U CN212649096U CN 212649096 U CN212649096 U CN 212649096U CN 202021284325 U CN202021284325 U CN 202021284325U CN 212649096 U CN212649096 U CN 212649096U
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Abstract
The utility model discloses an interlocking protection circuit of transient state, its characterized in that: the fault signal collection circuit collects transient fault signals, the output end of the fault signal collection circuit is connected with the falling edge delay circuit, the falling edge delay circuit is used for changing narrow pulses of the fault signals into wide pulses, the output end of the falling edge delay circuit is connected with the high-speed driver, and the output end of the high-speed driver is connected with a drive enabling terminal of a driver of load equipment and used for outputting low-level signals to the enabling terminal after receiving the fault signals. The invention has the advantages that: the circuit is simple, effective, relatively low in cost and accurate in realizing transient interlocking protection, can accurately detect a transient fault signal and timely protect the transient fault signal, so that the voltage of the enabling terminal is reduced, the enabling terminal cannot work, and meanwhile, the self-locking protection after the voltage of the enabling terminal is reduced can be carried out through the circuit; furthermore, functions such as reset control and the like can be realized, the method is simple and reliable, and the method has good effects on detection and protection of transient faults.
Description
Technical Field
The invention relates to the technical field of pulse power electronics and switching power supplies, in particular to a transient interlocking protection circuit, which is particularly suitable for a solid-state switching modulator power supply and various pulse power supplies.
Background
With the continuous update and rapid development of switching power supply technology, and the miniaturization, high frequency and high reliability of high power semiconductor devices, high frequency and high voltage switching power supplies have been involved in multiple lines and industries, in a pulse power electronic system, such as a pulse modulator, a pulse laser, an electromagnetic rail gun and the like, along with the continuous improvement of the operating frequency and the power of a circuit, the circuit is inevitably provided with some transient faults, if the continuous transient faults are not timely processed and protected, the control circuit cannot work if the continuous transient faults are not timely processed and protected, a power element or load equipment is damaged if the continuous transient faults are not timely processed and protected, even a fire disaster is caused if the continuous transient faults are serious, so the transient faults are accurately detected and judged, effective protection requirements are higher and higher, designers often adopt a high-speed chip FPGA (or CPLD) to solve the problem of transient fault detection, but the FPGA (or CPLD) is high in cost, needs additional programming, is complex in circuit and is not suitable for low-cost application. Simple, efficient, relatively low cost, and accurate transient interlock protection circuits are therefore important in solid state switching modulator power supplies and various pulse power supplies.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a transient interlocking protection circuit which is simple and reliable, has low cost and can quickly realize the detection interlocking protection of transient faults.
In order to achieve the purpose, the invention adopts the technical scheme that:
the utility model provides a transient state chain protection circuit, includes fault signal collection circuit, falling edge delay circuit, high speed drive, fault signal collection circuit collects transient state fault signal, and falling edge delay circuit is connected to its output, falling edge delay circuit is used for becoming fault signal's narrow pulse wide pulse, and high speed drive is connected to its output, the drive enable terminal of load device's driver is connected to high speed drive's output for in time output low level signal to enable terminal after receiving fault signal.
The protection circuit further comprises a rising edge delay circuit and a silicon controlled self-locking circuit, the output end of the high-speed driver is connected with the rising edge delay circuit, the output end of the rising edge delay circuit is connected with the input end of the silicon controlled self-locking circuit, the output end of the silicon controlled self-locking circuit is connected with the enabling terminal, and the enabling terminal is kept in a low-level state through the silicon controlled self-locking circuit.
The output end of the silicon controlled self-locking signal is further connected to an optical coupling isolation circuit, the output end of the optical coupling isolation circuit is connected with a control circuit, and the control circuit detects a fault signal through the output end of the optical coupling isolation circuit.
The output end of the control circuit is connected with the silicon controlled self-locking circuit through the reset circuit and is used for controlling the silicon controlled self-locking circuit to reset.
The fault signal collecting circuit comprises an input end which outputs the transient fault signal collected by the collecting circuit to an OR gate N1-A.
The falling edge delay circuit comprises a resistor R1, a diode V1 and a capacitor C1, the output end of the fault signal acquisition circuit is connected with the anode of the diode V1, and the cathode of the diode V1 is connected with the input end of the high-speed driver; the resistor R1 is connected in parallel with two ends of the diode V1; the cathode of the diode V1 is connected to ground through a capacitor C1.
The output end of the high-speed driver is connected with the cathode of a diode V2, and the anode lead-out LUCK terminal of V2 is connected with an enable terminal.
The rising edge delay circuit comprises an AND gate N3-C and an AND gate N3-B, wherein the input end of the AND gate N3-C is connected with the output end of the high-speed driver, the output end of the AND gate N3-C is connected with the cathode of a diode V4, the anode of the V4 is connected with the input end of the AND gate N3-B, a resistor R2 is connected with two ends of the diode V4 in parallel, and the anode of a diode V4 is grounded through a capacitor C3; the output end of the AND gate N3-B is connected with the silicon controlled rectifier self-locking circuit.
The silicon controlled self-locking circuit comprises a silicon controlled V7 and a triode V5, the output end of the rising edge delay circuit is connected with the base electrode of the triode V5 after passing through a resistor R3, a +5V power supply is connected with the collector electrode of the V5 through a resistor, the collector electrode of the V5 is connected with the anode of a diode V6, and the cathode of the diode V6 is connected with the G electrode of the silicon controlled V7; the emitter of V5 is grounded, and the collector is grounded through a capacitor C4; the negative electrode of the diode V6 is grounded through the resistor R5, and the capacitor C5 is connected in parallel at two ends of the resistor R5; the C pole of the controllable silicon V7 is grounded, the A pole of the controllable silicon V7 is connected with the negative pole of the diode V3, and the positive pole of the V3 is connected with the enabling terminal.
The A pole of the controllable silicon V7 is connected with the anode of the diode V8, and the cathode of the V8 is connected with the +5V power supply.
The optical coupler isolation circuit comprises an optical coupler V11, wherein the 1 st pin of the optical coupler V11 is connected with a power supply +5V through a resistor R6; a 2 nd pin of the optocoupler V11 is connected with the anode of the diode V10, and the cathode of the V10 is connected with the A pole of the thyristor V7; no. 3 pin of the optical coupler V11 is grounded, and the No. 4 pin is led out of an F-LUCK terminal and connected to a control circuit, and the control circuit collects fault signals through the F-LUCK terminal.
The reset circuit comprises an optical coupler V9, a pin No. 1 of a V9 leads out a terminal OV-RST through a resistor R7, the terminal OV-RST is connected with a reset output end of the control circuit, pins No. 2 and No. 3 of a V9 are grounded, a pin No. 4 of the V9 is connected to a pin No. 2 of a V11, and a pin No. 2 of a V11 is grounded through a capacitor C6.
The invention has the advantages that: the circuit is simple, effective, relatively low in cost and accurate in realizing transient interlocking protection, can accurately detect a transient fault signal and timely protect the transient fault signal, so that the voltage of the enabling terminal is reduced, the enabling terminal cannot work, and meanwhile, the self-locking protection after the voltage of the enabling terminal is reduced can be carried out through the circuit; furthermore, functions such as reset control and the like can be realized, the method is simple and reliable, and the method has good effects on detection and protection of transient faults.
Drawings
The contents of the expressions in the various figures of the present specification and the labels in the figures are briefly described as follows:
FIG. 1 is a schematic block diagram of a protection circuit of the present invention;
FIG. 2 is a circuit diagram of the transient interlock protection circuit of the present invention;
FIG. 3 is a timing diagram of the transient interlock protection circuit according to the present invention;
FIG. 4 is a LOCK connection diagram according to the present invention.
Detailed Description
The following description of preferred embodiments of the invention will be made in further detail with reference to the accompanying drawings.
The invention provides a transient interlocking protection circuit, which is simple and reliable, collects a fault signal by using an OR gate, changes a narrow pulse into a wide pulse by passing through a falling edge delay circuit formed by RDC (remote data center), then passes through a high-speed driver to pull down a protected signal so as to achieve the synchronous protection effect of the transient fault, in addition, the wide pulse signal output by the high-speed driver passes through a rising edge delay circuit formed by the AND gate and the RDC again, controls a triode to control the passing of a silicon controlled rectifier by controlling the triode so that the protected signal is pulled down, and simultaneously utilizes the self-locking characteristic of the silicon controlled rectifier to enable the protected signal to be always in a pulled down state, the self-locking signal is isolated and output by an optical coupler so as to be convenient to be detected by other control circuits, and provides a reset number to enable the silicon controlled rectifier to be self-locked and reset by the optical coupler after other control circuits detect the, thus, a transient chain protection action process can be completed. The transient interlocking protection circuit mainly comprises an OR gate pair fault signal collection circuit, a front edge delay and a rear edge delay which are composed of an RDC and an AND gate, a high-speed driver, a silicon controlled self-locking control circuit, and a fault signal optical coupling isolation output and reset signal optical coupling isolation input circuit. The circuit accurately converts the transient fault signal (narrow pulse signal) into a stably existing low level signal, is convenient for other control circuits to detect and control the transient fault, and simply and effectively realizes transient interlocking protection.
As shown in fig. 1, a transient interlock protection circuit includes a fault signal collection circuit, a falling edge delay circuit, and a high-speed driver, where the fault signal collection circuit collects a transient fault signal, an output end of the fault signal collection circuit is connected to the falling edge delay circuit, the falling edge delay circuit is used to change a narrow pulse of the fault signal into a wide pulse, an output end of the falling edge delay circuit is connected to the high-speed driver, and an output end of the high-speed driver is connected to a drive enable terminal of a driver of a load device, and is used to output a low-level signal to the enable terminal in time after receiving the fault signal. Of course, the enable terminal may be a control terminal of the driver, and the operation of the driver is controlled by inputting a control signal through the terminal.
The protection circuit further comprises a rising edge delay circuit and a silicon controlled self-locking circuit, the output end of the high-speed driver is connected with the rising edge delay circuit, the output end of the rising edge delay circuit is connected with the input end of the silicon controlled self-locking circuit, the output end of the silicon controlled self-locking circuit is connected with the enabling terminal, and the enabling terminal is enabled to be kept in a low-level state through the silicon controlled self-locking circuit.
The output end of the silicon controlled self-locking signal is further connected to the optical coupling isolation circuit, the output end of the optical coupling isolation circuit is connected with the control circuit, and the control circuit detects a fault signal through the output end of the optical coupling isolation circuit. The output end of the control circuit is connected with the silicon controlled self-locking circuit through the reset circuit and is used for controlling the silicon controlled self-locking circuit to reset. The fault signal collection circuit comprises an input end which outputs the transient fault signal collected by the collection circuit to an OR gate N1-A.
Fig. 2 shows a specific circuit diagram of the protection circuit, wherein the falling edge delay circuit includes a resistor R1, a diode V1 and a capacitor C1, an output terminal of the fault signal acquisition circuit is connected to an anode of the diode V1, and a cathode of the diode V1 is connected to an input terminal of the high-speed driver; the resistor R1 is connected in parallel with two ends of the diode V1; the cathode of the diode V1 is connected to ground through a capacitor C1.
The output terminal of the high-speed driver is connected to the cathode of the diode V2, and the positive lead-out LUCK terminal of V2 is connected to the enable terminal. The high speed driver may be a mos tube driver, and MIC4429, FAN3121, etc. chips may be employed.
The rising edge delay circuit comprises an AND gate N3-C and an AND gate N3-B, wherein the input end of the AND gate N3-C is connected with the output end of the high-speed driver, the output end of the AND gate N3-C is connected with the cathode of a diode V4, the anode of the V4 is connected with the input end of the AND gate N3-B, a resistor R2 is connected with two ends of the diode V4 in parallel, and the anode of a diode V4 is grounded through a capacitor C3; the output end of the AND gate N3-B is connected with the silicon controlled rectifier self-locking circuit.
The silicon controlled self-locking circuit comprises a silicon controlled V7 and a triode V5, the output end of the rising edge delay circuit is connected with the base electrode of the triode V5 after passing through a resistor R3, a +5V power supply is connected with the collector electrode of the V5 through a resistor, the collector electrode of the V5 is connected with the anode of a diode V6, and the cathode of the diode V6 is connected with the G electrode of the silicon controlled V7; the emitter of V5 is grounded, and the collector is grounded through a capacitor C4; the negative electrode of the diode V6 is grounded through the resistor R5, and the capacitor C5 is connected in parallel at two ends of the resistor R5; the C pole of the controllable silicon V7 is grounded, the A pole of the controllable silicon V7 is connected with the negative pole of the diode V3, and the positive pole of the V3 is connected with the enabling terminal. The A pole of the controllable silicon V7 is connected with the anode of the diode V8, and the cathode of the V8 is connected with the +5V power supply.
The optical coupler isolation circuit comprises an optical coupler V11, and a 1 st pin of an optical coupler V11 is connected with a +5V power supply through a resistor R6; a 2 nd pin of the optocoupler V11 is connected with the anode of the diode V10, and the cathode of the V10 is connected with the A pole of the thyristor V7; no. 3 pin of the optical coupler V11 is grounded, and the No. 4 pin is led out of an F-LUCK terminal and connected to a control circuit, and the control circuit collects fault signals through the F-LUCK terminal. The reset circuit comprises an optical coupler V9, a pin No. 1 of a V9 leads out a terminal OV-RST through a resistor R7, the terminal OV-RST is connected with a reset output end of the control circuit, pins No. 2 and No. 3 of a V9 are grounded, a pin No. 4 of the V9 is connected to a pin No. 2 of the V11, and a pin No. 2 of the V11 is grounded through a capacitor C6.
The main principle of the application is to realize the detection of transient fault signals through a transient protection circuit, namely, after a narrow pulse is changed into a wide pulse, the narrow pulse is sent into a high-speed driver, and then an output terminal LOCK terminal is pulled down, as shown in fig. 4, the LOCK terminal is connected to an enabling terminal of a driver of a specific circuit, and after the LOCK terminal is pulled down to a low level, the enabling terminal of a load driver can not work for the low level, so that the purpose of timely work protection shutdown is achieved. The drive control is performed by a drive signal of its controller when in a normal state. Taking switching power supply as an example, switching power supply's driver is used for driving the full-bridge circuit, and normally, the LOCK terminal does not have the output and can not influence drive signal to the control of the enable end of driver, after transient fault appears, draws down the LOCK and makes the enable terminal low level, thereby the drive can't work and realize protect function. The self-locking circuit can also realize the function of keeping low level, and the control circuit is used as a controller in a specific application field, can acquire a fault signal through the F-LOCK, and can acquire the fault signal in time and further utilize the signal to perform alarm lamp; and can reset through OV-RST, thus realize the function of the auto-lock protection completely.
Fig. 2 shows a circuit diagram of the transient interlock protection circuit, and fig. 3 shows a timing diagram of the transient interlock protection circuit. Wherein, the transient FAULT signal F _ IN fig. 2 and 3 is inputted to the 1 st pin/2 nd pin of the or gate N1-a through the FAULT1/FAULT2 of the present circuit, the N1-a 3 rd pin is inputted to the 2 nd pin of the high speed driver N2 after being delayed by the rising edge delay network formed by the resistor R1, the diode V1 and the capacitor C1, the P1 protection signal IN fig. 3 is outputted by the 7 th and 6 th pins of N2 after being processed by N2, the protected signal LOCK is pulled down by the diode V2, and the signal is inputted to the 8 th pin and the 9 th pin of the and gate N3_ C, the N3_ C10 th pin is inputted to the 5 th pin and the 6 th pin of the and gate N3_ C after being delayed by the falling edge delay network formed by the resistor R2, the diode V4 and the capacitor C3, the triode is turned off by the output pin N3_ C, the and the output pin of the and gate N3_ C is shaped by the resistor R5 and the triode is turned off at the time of the triode 57324, the +5V voltage is loaded to the G pin of the controlled silicon V7 through the R4, the capacitor C4, the diode V6, the resistor R5 and the capacitor C5, so that the controlled silicon V7 is conducted, a P2 protection signal in FIG. 3 is formed, the signal passes through the diode V3 to pull down the protected signal LOCK, due to the conduction of the controlled silicon V7, the +5V voltage passes through the resistor R6, the 1 st pin of the optical coupler V11 is input into the 2 nd pin for output, and passes through the capacitor C6, the diode V10 and the controlled silicon V7 to GND, so that a conduction current is formed, the current enables the controlled silicon V7 to be in a conducting state all the time, namely, the transient chain protection function is completed, wherein the P2 signal in FIG. 3 is clamped to the +5V voltage through the V8, so that the controlled silicon V7 is not broken down, and the P2 signal in FIG. 3 is isolated and output to the F _ LOCK end through the optical coupler V11 to provide a transient fault reliable detection signal RST in the control circuit, and reset signal OV, load 1 st foot and 2 nd foot end to opto-coupler V9 through resistance R7, make 3 rd foot and the 4 th foot of opto-coupler V9 between be through-state, the 2 nd foot of opto-coupler V11 is pulled to GND promptly, this moment owing to make +5V voltage pass through resistance R6, 2 nd foot input output by opto-coupler V11 1 st foot, pass through electric capacity C6 again, diode V10, silicon controlled rectifier V7 to GND, current channel is cut off on maintaining silicon controlled rectifier V7, silicon controlled rectifier V7 resumes the turn-off state, and accomplish the fault reset function, and then realized the purpose of the chain protection of utility model transient state.
It is clear that the specific implementation of the invention is not restricted to the above-described embodiments, but that various insubstantial modifications of the inventive process concept and technical solutions are within the scope of protection of the invention.
Claims (10)
1. A transient interlock protection circuit, comprising: the fault signal collection circuit collects transient fault signals, the output end of the fault signal collection circuit is connected with the falling edge delay circuit, the falling edge delay circuit is used for changing narrow pulses of the fault signals into wide pulses, the output end of the falling edge delay circuit is connected with the high-speed driver, and the output end of the high-speed driver is connected with a drive enabling terminal of a driver of load equipment and used for outputting low-level signals to the enabling terminal after receiving the fault signals.
2. The transient interlock protection circuit of claim 1, wherein: the protection circuit further comprises a rising edge delay circuit and a silicon controlled self-locking circuit, the output end of the high-speed driver is connected with the rising edge delay circuit, the output end of the rising edge delay circuit is connected with the input end of the silicon controlled self-locking circuit, the output end of the silicon controlled self-locking circuit is connected with the enabling terminal, and the enabling terminal is kept in a low-level state through the silicon controlled self-locking circuit.
3. The transient interlock protection circuit of claim 2, wherein: the output end of the silicon controlled self-locking circuit is further connected to an optical coupling isolation circuit, the output end of the optical coupling isolation circuit is connected with a control circuit, and the control circuit detects fault signals through the output end of the optical coupling isolation circuit.
4. The transient interlock protection circuit of claim 3, wherein: the output end of the control circuit is connected with the silicon controlled self-locking circuit through the reset circuit and is used for controlling the silicon controlled self-locking circuit to reset.
5. The transient interlock protection circuit of any of claims 1-4, wherein: the fault signal collecting circuit comprises an input end which outputs the transient fault signal collected by the collecting circuit to an OR gate N1-A.
6. The transient interlock protection circuit of any of claims 1-4, wherein: the falling edge delay circuit comprises a resistor R1, a diode V1 and a capacitor C1, the output end of the fault signal acquisition circuit is connected with the anode of the diode V1, and the cathode of the diode V1 is connected with the input end of the high-speed driver; the resistor R1 is connected in parallel with two ends of the diode V1; the cathode of the diode V1 is connected to ground through a capacitor C1.
7. The transient interlock protection circuit of any of claims 1-4, wherein: the output end of the high-speed driver is connected with the cathode of a diode V2, and the anode of the V2 leads out a LOCK terminal to be connected with an enabling terminal.
8. The transient interlock protection circuit of any of claims 2-4, wherein: the rising edge delay circuit comprises an AND gate N3-C and an AND gate N3-B, wherein the input end of the AND gate N3-C is connected with the output end of the high-speed driver, the output end of the AND gate N3-C is connected with the cathode of a diode V4, the anode of the V4 is connected with the input end of the AND gate N3-B, a resistor R2 is connected with two ends of the diode V4 in parallel, and the anode of a diode V4 is grounded through a capacitor C3; the output end of the AND gate N3-B is connected with the silicon controlled rectifier self-locking circuit.
9. The transient interlock protection circuit of any of claims 2-4, wherein: the silicon controlled self-locking circuit comprises a silicon controlled V7 and a triode V5, the output end of the rising edge delay circuit is connected with the base electrode of the triode V5 after passing through a resistor R3, a +5V power supply is connected with the collector electrode of the V5 through a resistor, the collector electrode of the V5 is connected with the anode of a diode V6, and the cathode of the diode V6 is connected with the G electrode of the silicon controlled V7; the emitter of V5 is grounded, and the collector is grounded through a capacitor C4; the negative electrode of the diode V6 is grounded through the resistor R5, and the capacitor C5 is connected in parallel at two ends of the resistor R5; the C pole of the controllable silicon V7 is grounded, the A pole of the controllable silicon V7 is connected with the negative pole of the diode V3, and the positive pole of the V3 is connected with the enabling terminal.
10. The transient interlock protection circuit of claim 3 or 4, wherein: the optical coupler isolation circuit comprises an optical coupler V11, wherein the 1 st pin of the optical coupler V11 is connected with a power supply +5V through a resistor R6; a 2 nd pin of the optocoupler V11 is connected with the anode of the diode V10, and the cathode of the V10 is connected with the A pole of the thyristor V7; no. 3 pin of opto-coupler V11 ground connection, and F-LOCK terminal is drawn forth to No. 4 pin and is connected to control circuit, control circuit gathers the fault signal through the F-LOCK terminal.
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| CN202021284325.4U CN212649096U (en) | 2020-07-03 | 2020-07-03 | Transient interlocking protection circuit |
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| CN202021284325.4U CN212649096U (en) | 2020-07-03 | 2020-07-03 | Transient interlocking protection circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116915021A (en) * | 2023-07-12 | 2023-10-20 | 北京市科通电子继电器总厂有限公司 | Solid-state power controller |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116915021A (en) * | 2023-07-12 | 2023-10-20 | 北京市科通电子继电器总厂有限公司 | Solid-state power controller |
| CN116915021B (en) * | 2023-07-12 | 2024-04-26 | 北京市科通电子继电器总厂有限公司 | Solid-state power controller |
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