CN218584889U - Dynamic resistance testing device - Google Patents
Dynamic resistance testing device Download PDFInfo
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- CN218584889U CN218584889U CN202221935146.1U CN202221935146U CN218584889U CN 218584889 U CN218584889 U CN 218584889U CN 202221935146 U CN202221935146 U CN 202221935146U CN 218584889 U CN218584889 U CN 218584889U
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Abstract
The utility model discloses a dynamic resistance testing device, which comprises a circuit substrate, wherein the circuit substrate is provided with a power circuit, a PWM control circuit, a driving chip and a sampling circuit, the power circuit supplies power to the PWM control circuit and the driving chip, and the PWM control circuit outputs control signals to the driving chip; the circuit board is provided with a test mother seat, a test daughter card is detachably inserted into the test mother seat, and the sampling circuit is electrically connected with the mother seat; the test mother seat is provided with a plurality of first contacts, the test daughter card is provided with a plurality of second contacts, and the first contacts are electrically connected with the second contacts. The utility model discloses can conveniently test gallium nitride power device's dynamic resistance, can also test the static electrical characteristic of gallium nitride power device after the test daughter card takes off.
Description
Technical Field
The utility model relates to an electronic device's electrical characteristic test's technical field especially relates to a gallium nitride power device's dynamic resistance testing arrangement.
Background
With the development of electronic technology, people have higher and higher requirements on the performance of electronic devices, for example, the electronic devices are expected to have higher computing power. At present, most of power devices used in electronic devices are silicon power devices, such as widely used MOSFET silicon power devices. In recent years, gallium nitride power devices are widely used, and compared with silicon power devices, the gallium nitride power devices have higher efficiency and can meet the requirements of high-power-consumption and high-density systems, servers and computer systems.
After the gallium nitride power device is produced, the electrical characteristics of the gallium nitride power device need to be detected to ensure that the produced gallium nitride power device meets the preset requirements. Since the gan power device is prone to dynamic drift of on-resistance due to current collapse effect under high voltage condition, it is commonly called the dynamic resistance of gan power device. This phenomenon causes a dynamic increase in the switching loss of the circuit, and the drift amount of the dynamic resistance is not easy to calculate, and it is usually necessary to test the gan power device to detect the drift amount of the dynamic resistance.
There are many test circuits for Dynamic resistance under continuous switching, which are used to test the drift amount of the resistance of the gan power device, and are usually tested in reliability tests such as Dynamic High Temperature Operating Life (DHTOL).
However, the current DHTOL test can only monitor the dynamic resistance of the gan power device, and the drift amount of the dynamic resistance is used as the basis for determining whether the gan power device is failed. However, in the DHTOL test and the related life evaluation test, the drift amount of the dynamic resistor is not the only failure judgment basis, and the static electrical characteristics of the device under test, such as the threshold voltage Vth, the drain-source resistance Rds (on), the drain-source current Idss, and the gate-source current Igss, are also included, and there is a case where the dynamic resistor is normal and the static electrical characteristics have seriously drifted and failed.
As shown in fig. 1, a conventional testing circuit for a DHTOL test includes a low-voltage output power supply 10, a PWM control circuit 11, a gate driving circuit 12, a bus high-voltage power supply module 13, a voltage sampling circuit 14, and a current sampling circuit 15, where a device 18 to be tested is soldered on a circuit board to be tested, for example, the device is soldered on the same circuit board together with the gate driving circuit 12.
The low-voltage output power supply 10 supplies power to the PWM control circuit 11 and the gate drive circuit 12, the gate drive circuit 12 outputs a drive signal to the tested device 18, the bus high-voltage power supply module 13 outputs a high-voltage signal to the tested device 18, and when the tested device 18 is in switching operation, the voltage sampling circuit 14 and the current sampling circuit 15 sample a voltage signal and a current signal of the tested device 18, and accordingly the drift amount of the dynamic resistance of the tested device 18 is calculated.
However, since the device under test 18 is soldered to the gate driving circuit 12, the static electrical characteristics of the device under test 18 cannot be tested, and the reliability of the device under test 18 cannot be accurately evaluated, especially when a lifetime model is established for the gan power device, there is a great risk.
Disclosure of Invention
The utility model aims at providing a can test the dynamic resistance of gallium nitride power device and do not influence the dynamic resistance testing arrangement that its static electrical characteristics detected.
In order to achieve the above object, the present invention provides a dynamic resistance testing device, which comprises a circuit substrate, wherein the circuit substrate is provided with a power circuit, a PWM control circuit, a driving chip and a sampling circuit, the power circuit supplies power to the PWM control circuit and the driving chip, and the PWM control circuit outputs a control signal to the driving chip; the circuit board is provided with a test mother seat, the test daughter card is detachably inserted into the test mother seat, and the sampling circuit is electrically connected with the mother seat; the test mother seat is provided with a plurality of first contacts, the test daughter card is provided with a plurality of second contacts, and the first contacts are electrically connected with the second contacts.
According to the scheme, the circuit substrate is provided with the test mother seat, the tested gallium nitride power device can be installed on the test daughter card, and when the dynamic resistance of the gallium nitride power device needs to be tested, the test daughter card is inserted into the test mother seat to test the dynamic resistance of the gallium nitride power device. When the static electrical characteristics of the gallium nitride power device need to be tested, the test daughter card is taken down from the test mother seat, and the static electrical characteristics of the gallium nitride power device can be tested without being influenced by the driving circuit.
Preferably, the test daughter card comprises at least two circuit layers, each of which is provided with at least one second contact arrangement.
Therefore, the test daughter card is provided with a plurality of layers of circuit layers, and the second contact is arranged on each layer of circuit layer, so that the problem that the area of the test daughter card is large due to the fact that one layer of circuit layer is arranged is avoided, and on the other hand, through reasonable arrangement of the second contact, a magnetic field can be formed to offset, parasitic inductance is reduced, and the accuracy of dynamic resistance detection is improved.
The further scheme is that the number of the circuit layers is two, and the number of the second contacts of each circuit layer is equal.
Therefore, the number of the second contacts of each circuit layer is the same, so that the areas of the two circuit layers are fully utilized, and the area of the test daughter card can be effectively reduced.
The further scheme is that the multilayer circuit layer comprises a first circuit layer and a second circuit layer, the first circuit layer is provided with a first power connecting wire and a first signal connecting wire, and the first power connecting wire and the first signal connecting wire are perpendicular to each other at the intersection.
Because the first power connecting line and the first signal connecting line are perpendicular to each other at the intersection, if the first power connecting line is connected to the drain electrode of the gallium nitride power device, the magnetic interference can be reduced by the connecting mode, the voltage and current offset phase amplitude caused by the magnetic interference can also be reduced, and the detection accuracy can be improved.
In a further aspect, the second circuit layer is provided with a second power connection line and a second signal connection line, and the second power connection line and the second signal connection line are perpendicular to each other at an intersection.
It can be seen that the power connection lines and the signal connection lines connected to the source electrodes of the gallium nitride power devices, which are arranged on the second wiring layer, can also reduce magnetic interference and the voltage current offset phase amplitude caused by the magnetic interference by being vertically arranged at the intersection.
In a further aspect, the first power connection line and the second power connection line are parallel to each other and stacked.
Because the current on the drain electrode and the source electrode of the gallium nitride power device is large, the power connecting wires connected to the drain electrode and the source electrode are respectively arranged on the first circuit layer and the second circuit layer, and the magnetic fields formed by the first power connecting wire and the second power connecting wire can be mutually offset by adopting a mode of mutually parallel and laminated arrangement, so that the parasitic inductance is reduced.
In a further aspect, the second contact includes a first power contact, a third power contact and a first signal contact disposed on the first circuit layer; the first power connection line is connected to the first power contact, the first signal connection line is connected to the first signal contact, and the third power contact is disposed between the first power contact and the first signal contact.
Therefore, the first power contact and the first signal contact are not adjacently arranged, but a third power contact, such as a power contact of a grid, is arranged at intervals, so that the problem of magnetic interference can be further reduced.
In a further aspect, the second contacts include a second power contact and two second signal contacts disposed on the second circuit layer; the second power connection line is connected to the second power contacts, and the second signal connection line is connected to the two second signal contacts.
Specifically, two source signal contacts are arranged, and the source signal connecting wire can be connected to the two source signal contacts, so that the working requirement of the gallium nitride power device can be met.
A third power connecting wire is further arranged on the first circuit layer and electrically connected with the third power contact; the third power connecting line is parallel to the second power connecting line.
The third power connecting line is connected to the grid of the gallium nitride power device, and the third power connecting line is parallel to the second power connecting line due to the fact that the current of the grid is small, and the effect of reducing parasitic capacitance can be achieved.
Still further, the third power connection line is stacked on a portion of the second signal connection line.
In this way, the power connection line of the gate and a part of the signal connection line of the source are stacked, and the currents of the two are small, so that the circuit area can be reduced, and the parasitic capacitance can be reduced.
Drawings
Fig. 1 is an electrical schematic block diagram of a dynamic resistance testing apparatus of a conventional gallium nitride power device.
Fig. 2 is an electrical schematic block diagram of an embodiment of the dynamic resistance testing apparatus of the present invention.
Fig. 3 is a schematic structural diagram of a front side of a test daughter card in an embodiment of the dynamic resistance test apparatus of the present invention.
Fig. 4 is a schematic structural diagram of a back side of a test daughter card in an embodiment of the dynamic resistance testing apparatus of the present invention.
Fig. 5 is a circuit diagram of a first test scenario of an embodiment of the dynamic resistance testing apparatus of the present invention.
Fig. 6 is a circuit diagram of a second test scenario of an embodiment of the dynamic resistance testing apparatus of the present invention.
Fig. 7 is a circuit diagram of a third test scenario of the embodiment of the dynamic resistance testing apparatus of the present invention.
The present invention will be further explained with reference to the drawings and examples.
Detailed Description
The utility model discloses a dynamic resistance testing arrangement is used for testing the dynamic resistance of gallium nitride power device to can also be convenient take off gallium nitride power device from circuit substrate, conveniently test the static electrical characteristic of gallium nitride power device from this.
Referring to fig. 2, the dynamic resistance testing apparatus for the gallium nitride power device includes a circuit substrate, on which a low-voltage output power supply 20, a PWM control circuit 21, a gate driving circuit 22, a bus high-voltage power supply module 23, a voltage sampling circuit 24, and a current sampling circuit 25 are disposed, and in addition, a testing mother socket 28 is further disposed, where the testing mother socket 28 includes a plurality of first contacts, in this embodiment, the number of the first contacts is six. In addition, the dynamic resistance testing device for the gallium nitride power device further comprises a test daughter card 30, and the test daughter card 30 is pluggable and insertable into the test mother seat 28.
The low-voltage output power supply 20 outputs a low-voltage to the PWM control circuit 21 and the gate drive circuit 22 to maintain the PWM control circuit 21 and the gate drive circuit 22 in operation. The PWM control circuit 21 outputs a control signal, such as a PWM control signal, to the gate driving circuit 22, and the gate driving circuit 22 receives the PWM control signal and outputs a driving signal to the test socket 28 to drive the gan power device under test to operate.
The bus high-voltage power supply module 23 is connected with the test mother seat 28 and is used for providing a high-voltage signal for a tested gallium nitride power device. The voltage sampling circuit 24 is a Vds clamp sampling circuit for sampling a clamp voltage between the drain and the source of the gallium nitride power device. The current sampling circuit 25 is an Ids sampling circuit for sampling a current between the drain and the source of the gallium nitride power device. The drift amount of the dynamic resistance of the gallium nitride power device can be calculated according to the voltage signal and the current signal obtained by sampling by the voltage sampling circuit 24 and the current sampling circuit 25.
Referring to fig. 3 and 4, the test daughter card 30 includes a plurality of circuit layers, for example, in the embodiment, the test daughter card 30 includes two circuit layers, namely a first circuit layer 31 and a second circuit layer 32. The first circuit layer 31 is located on a first side, such as a front side, of the test daughter card 30, and the second circuit layer 32 is located on a second side, such as a back side, of the test daughter card 30.
Specifically, fig. 3 shows a structure of a front surface of the test daughter card 30, a mounting site of the gallium nitride power device to be tested is provided on the front surface of the test daughter card 30, and a pad 61 is provided, where the pad 61 is a contact for welding a drain of the gallium nitride power device 60. Three second contacts, namely a first power contact 41, a third power contact 43 and a first signal contact 46, are provided on the lower front side of the test daughter card 30. The first power contact 41 is electrically connected to the drain of the gan power device 60, and for this purpose, a first power connection line 51 is disposed on the first circuit layer 31 and connected between the pad 61 and the first power contact 41. Since the first signal contact 46 is a drain signal contact, the first circuit layer 31 is provided with a first signal connection line 56 connected between the pad 61 and the first signal contact 46.
As can be seen from fig. 3, the first signal connection line 56 is bent, and a section connected to the pad 61 is an intersection portion 59, in fig. 3, the intersection portion 59 intersects the first power connection line 51 at the pad 61, and the intersection portion 59 is perpendicular to the first power connection line 51. Since the drain of the gan power device 60 usually has a large current flowing through it, the first power connection line 51 also has a large current flowing through it, and a magnetic field is generated. If the first signal connection line 56 and the first power connection line 51 are parallel and very close to each other, the first signal connection line 56 will be disturbed by a magnetic field. Therefore, the intersecting portion 59 perpendicular to the first power connection line 51 is provided in this embodiment, so that a larger gap exists between the portion of the first signal connection line 56 parallel to the first power connection line 51 and the first power connection line 51, thereby preventing the first signal connection line 56 from being interfered by the magnetic field and affecting the operation of the gan power device 60.
In addition, a third power contact 43 is arranged between the first power contact 41 and the first signal contact 46, in this embodiment, the third power contact 43 is connected to the gate of the gallium nitride power device 60, and since the current flowing through the gate is small, magnetic field interference on the first signal connection line 56 is not caused, in this embodiment, by reasonably arranging the positions of the plurality of second contacts, the magnetic interference on the first signal connection line 56 can be effectively reduced, and further, the voltage current offset phase amplitude caused by the magnetic field interference can be reduced, which is beneficial to improving the accuracy of the dynamic resistance test on the gallium nitride power device 60.
Of course, a pad (not shown) for bonding a gate may be further provided on the front surface of the test daughter card 30, and the third power connection line 53 is connected between the pad and the third power contact 43.
Referring to fig. 4, a mounting site of a gallium nitride power device to be tested is provided on the back side of the test daughter card 30, and a pad 62 is provided, the pad 62 being a contact for source bonding of the gallium nitride power device 60. Three second contacts, a second power contact 42 and two second signal contacts 47, 48, are provided on the lower rear side of the test daughter card 30. The second power contact 42 is electrically connected to the source of the gan power device 60, and for this purpose, the second circuit layer 32 is provided with a second power connection line 52 connected between the pad 62 and the second power contact 42. Since the second signal contact 46 is a source signal contact, the second wiring layer 32 is provided with a second signal connection line 57 connected between the pad 65 and the two second signal contacts 47 and 48.
As can be seen from fig. 4, the second signal connection line 57 is bent, and a section connected to the pad 62 is an intersection portion 58, in fig. 3, the intersection portion 58 intersects the second power connection line 52 at the pad 62, and the intersection portion 58 and the second power connection line 52 are perpendicular to each other. Since the source of the gan power device 60 usually has a large current flowing through it, the second power connection line 52 also has a large current flowing through it and generates a magnetic field. If the second signal connection line 57 and the second power connection line 52 are parallel to each other and very close to each other, the second signal connection line 57 is disturbed by a magnetic field. Therefore, the intersecting portion 58 perpendicular to the second power connection line 52 is provided in this embodiment, so that a larger gap exists between the portion of the second signal connection line 57 parallel to the second power connection line 52 and the second power connection line 52, thereby preventing the second signal connection line 57 from being interfered by the magnetic field to affect the operation of the gan power device 60.
In this embodiment, the two second signal contacts 47 and 48 are both connected to the pad 62, and the current flowing through the second signal connection line 57 is small.
As can be seen from fig. 3 and 4, the first power connection line 51 and the second power connection line 52 are stacked, that is, the first power connection line 51 is disposed on the front side of the test daughter card 30, the second power connection line 52 is disposed on the back side of the test daughter card 30, and in the normal direction of the test daughter card 30, the first power connection line 51 and the second power connection line 52 are parallel and overlap with each other. On one hand, since the first power connection line 51 and the second power connection line 52 both have a large current flowing therethrough, and the current direction on the first power connection line 51 is opposite to the current direction on the second power connection line 52, the wiring structure of the embodiment is adopted, so that the magnetic fields formed by the first power connection line 51 and the second power connection line 52 are mutually offset, and further the parasitic inductance is reduced. On the other hand, since the first power connection line 51 and the second power connection line 52 are connected to the pad and the corresponding power contact at the shortest distance, the loop area can be minimized, which is beneficial to reducing the area of the test daughter card 30. In addition, since the number of the second contacts arranged on the front surface and the back surface of the test daughter card 30 is the same, and the arrangement is also the same, the area of the test daughter card 30 can be effectively reduced.
Further, the third power connection line 53 is stacked on a portion of the second signal connection line 57, specifically, a portion connected to the second signal contact 47, and thus, the power connection line of the gate is stacked on a portion of the signal connection line of the source. Since the currents of the third power connection line 53 and the second signal connection line 57 are small, the signal transmission of the source is not affected, and the area of the test daughter card 30 can be reduced.
The six first contacts of the female test socket 28 correspond to the six second contacts of the daughter card 30 one by one, and the arrangement of the six first contacts of the female test socket 28 is completely the same as that of the six second contacts, so that after the daughter card 30 is inserted into the female test socket 28, each first contact can be electrically connected to the corresponding second contact.
The present embodiment can be applied to testing in various scenarios, referring to fig. 5, when the present embodiment is applied to an in-phase Buck circuit, the bus high-voltage power supply module 23 includes a DC power supply DC and a capacitor C11, and supplies power to the gallium nitride power device Q12 under test, and the gate driving circuit 22 can receive a PWM signal and can output a driving signal to the gate of the gallium nitride power device Q12 under test. The clamp circuit 75 is connected between the drain and source of the gan power device Q12 for sampling the clamp voltage of the gan power device Q12. The gallium nitride power device Q12 is further connected to a load R11, and to an inductor L11 and a capacitor C12.
Referring to fig. 6, when the present embodiment is applied to an in-phase Buck boost circuit, the bus high-voltage power supply module 23 includes a DC power supply DC and a capacitor C21, and supplies power to the gallium nitride power device Q22 to be tested, and the current output by the bus high-voltage power supply module 23 is output to the gallium nitride power device Q22 through an inductor L21. The gate drive circuit 22 receives the PWM signal and outputs a drive signal to the gate of the gallium nitride power device Q22 under test. The clamp circuit 76 is connected between the drain and source of the gallium nitride power device Q22 for sampling the clamp voltage of the gallium nitride power device Q22. The gallium nitride power device Q12 is also connected to a load R21 and a capacitor C22.
Referring to fig. 7, when the present embodiment is applied to a resistive load circuit, the bus high-voltage power supply module 23 includes a DC power supply DC and a capacitor C31, and supplies power to a gallium nitride power device Q32 to be tested. The gate drive circuit 22 receives the PWM signal and outputs a drive signal to the gate of the gallium nitride power device under test Q32. The clamp circuit 77 is connected between the drain and source of the gallium nitride power device Q32 for sampling the clamp voltage of the gallium nitride power device Q32. The gan power device Q32 is also connected in series with a resistor R31.
It will be appreciated that different clamping circuits may be provided for different test scenarios, i.e. the specific circuitry on the circuit substrate is different. Because the test daughter card 30 can be inserted into the test mother socket 28, after the gan power device to be tested is welded to the test daughter card 30, the test daughter card 30 is inserted into different test mother sockets 28, so that the dynamic resistance test can be performed under different scenarios. After the test daughter card 30 is removed from the test mother socket 28, the static electrical characteristics of the gan power device can be tested independently.
It should be noted that, in practical applications, more second contacts may be disposed on the test daughter card, for example, four or five second contacts may be disposed on each circuit layer of the test daughter card. Or, the number of the second contacts of the two circuit layers is different, for example, the first circuit layer is provided with four second contacts, and the second circuit layer is provided with two second contacts.
Of course, the above-mentioned solution is only the preferred embodiment of the present invention, and there may be more changes in practical applications, for example, the number of the second contacts on the test daughter card and the change of the arrangement manner, or the change of the specific circuit structure of the clamping circuit, etc., which do not affect the implementation of the present invention, and should be included in the protection scope of the present invention.
Claims (10)
1. Dynamic resistance testing arrangement includes:
the circuit comprises a circuit substrate, wherein a power supply circuit, a PWM control circuit, a driving chip and a sampling circuit are arranged on the circuit substrate, the power supply circuit supplies power to the PWM control circuit and the driving chip, and the PWM control circuit outputs a control signal to the driving chip;
the method is characterized in that:
the circuit substrate is provided with a test mother seat, the test daughter card is detachably inserted into the test mother seat, and the sampling circuit is electrically connected with the mother seat;
the test mother seat is provided with a plurality of first contacts, the test daughter card is provided with a plurality of second contacts, and the first contacts are electrically connected with the second contacts.
2. The dynamic resistance testing device of claim 1, wherein:
the test daughter card comprises at least two layers of circuit layers, and each layer of circuit layer is provided with at least one second contact.
3. The dynamic resistance testing device of claim 2, wherein:
the number of the circuit layers is two, and the number of the second contacts of each circuit layer is equal.
4. The dynamic resistance testing device of claim 2, wherein:
the multilayer circuit layer comprises a first circuit layer and a second circuit layer, the first circuit layer is provided with a first power connecting wire and a first signal connecting wire, and the first power connecting wire and the first signal connecting wire are perpendicular to each other at the intersection.
5. The dynamic resistance testing device of claim 4, wherein:
the second circuit layer is provided with a second power connecting wire and a second signal connecting wire, and the second power connecting wire and the second signal connecting wire are perpendicular to each other at the intersection.
6. The dynamic resistance testing device of claim 5, wherein:
the first power connecting line and the second power connecting line are parallel to each other and are arranged in a stacked mode.
7. The dynamic resistance testing device according to claim 5 or 6, wherein:
the second contact comprises a first power contact, a third power contact and a first signal contact which are arranged on the first circuit layer;
the first power connection line is connected to the first power contact, the first signal connection line is connected to the first signal contact, and the third power contact is disposed between the first power contact and the first signal contact.
8. The dynamic resistance testing device of claim 7, wherein:
the second contacts comprise a second power contact and two second signal contacts arranged on the second circuit layer;
the second power connection line is connected to the second power contact, and the second signal connection line is connected to the two second signal contacts.
9. The dynamic resistance testing device of claim 8, wherein:
the first circuit layer is also provided with a third power connecting wire which is electrically connected with the third power contact;
the third power connection line is parallel to the second power connection line.
10. The dynamic resistance testing device of claim 9, wherein:
the third power connection line is stacked with a portion of the second signal connection line.
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| CN202221935146.1U CN218584889U (en) | 2022-07-25 | 2022-07-25 | Dynamic resistance testing device |
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| CN202221935146.1U CN218584889U (en) | 2022-07-25 | 2022-07-25 | Dynamic resistance testing device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116068360A (en) * | 2023-03-24 | 2023-05-05 | 佛山市联动科技股份有限公司 | Dynamic parameter test system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116068360A (en) * | 2023-03-24 | 2023-05-05 | 佛山市联动科技股份有限公司 | Dynamic parameter test system |
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