CN105277864B - Experimental rig, test method and the hookup of semiconductor chip - Google Patents
Experimental rig, test method and the hookup of semiconductor chip Download PDFInfo
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- CN105277864B CN105277864B CN201510187825.3A CN201510187825A CN105277864B CN 105277864 B CN105277864 B CN 105277864B CN 201510187825 A CN201510187825 A CN 201510187825A CN 105277864 B CN105277864 B CN 105277864B
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Abstract
The present invention provides experimental rig, test method and the hookup for being able to suppress the semiconductor chip of damage of test electrode.By the way that round about circuit (G) is arranged, makes on back flow current (IF4) turn of tidal stream to round about circuit (G), the damage of test electrode (13) can be prevented by the electric current that test electrode (13) is flowed through in reduction.
Description
Technical field
The present invention relates to the experimental rig of semiconductor chip, test method and hookups, more particularly to diode core
The experimental rig and test method of the reverse recovery characteristic of piece.
Background technique
Figure 13 is the test schematic and test waveform figure of the reverse recovery characteristic of existing diode chip for backlight unit, and (a) is examination
Circuit diagram is tested, is (b) test waveform figure.Here, diode chip for backlight unit is such as FWD (freewheeling diode) chip 4.
The reverse recovery characteristic test of FWD chip 4 refers to by making the IGBT3 conducting for constituting hookup 500a and closing
It is disconnected, so that FWD chip 4 is carried out Reverse recovery movement, confirmation FWD chip 4 does not damage under predetermined circumstances.In addition, above-mentioned anti-
To recovery characteristics test be measurement reverse recovery characteristic (reverse recovery current and/or reverse recovery time etc.) and with standard value ratio
Relatively come determine FWD chip 4 superiority and inferiority test.Manufacturing cost can be reduced by removing rejected product in chip stage.
In Figure 13, on the power capacitor 2 to be charged by power supply 1 connect IGBT 3 and with 3 differential concatenation of IGBT
FWD 4 (indicates symbol identical with chip), wherein FWD 4 is connected between the emitter and power supply 1 of IGBT 3 with cathode
The mode of the emitter of IGBT 3 connects.Make electric current in the loading coil being connected in parallel with FWD 4 by, off IGBT 3
It is flowed on 5.In the first time shutdown of the IGBT 3, back flow current IF4 is flowed by loading coil 5 and FWD 4.Second
When secondary conducting, short circuit current I1 flowing offsets back flow current IF4 by short circuit current I1, and it is dynamic that FWD 4 enters Reverse recovery
Make.If Reverse recovery movement terminates, the supply electric current provided by power capacitor 2 is as electric current I2 by IGBT 3 and load
Coil 5 returns to power capacitor 2.Then, capacitor 2 of cutting off the power is turned off by second, back flow current IF4 flows again.
When secondary back flow current IF4 becomes zero, reverse recovery characteristic off-test.
The experimental condition (- di/dt etc. of reverse recovery current) of aforementioned reverse recovery characteristic test is by connection capacitor
2, the influence of the inductance of the primary circuit route F of switch IGBT 3, FWD 4.If the inductance is big, it is difficult to be applied for obtaining
The reverse recovery characteristic test of-di/dt of the power consumption for the standard of obtaining.
In Figure 13 (b), IGBT 3 is connected in t1, flows back flow current IF4 in t2 shutdown TGBT 3.It is led again in t3
Logical IGBT 3 carries out reverse recovery characteristic test.IGBT 3 is turned off again in t4, flows back flow current IF4 on FWD 4.It should
The die-away time of back flow current IF4 needs to spend the extremely long time.Damping time constant τ is to remove the inductance of loading coil 5
Value obtained from the routing resistance of access is flowed through with back flow current IF4, because routing resistance is small τ value becomes larger.
Following content is described in patent document 1, i.e., on a semiconductor die to implement high-precision, stable characteristic examination
The low induction structure of chip contact portion is realized for the purpose of testing.
Figure 14 is the composition figure of the characteristic test apparatus of chip C described in Patent Document 1.Inspection holding member has can
Carry the base station 30 of chip C, the pin 42 for the determination chip location of C being mounted on base station 30 and throughout the pickup zone for carrying chip C
Domain and do not carry the exposed region of chip C and the metal film 40 that is formed.In the inspection of chip C, chip C is fixed on inspection and is used
The carrying region of holding member contacts probe 10a with the upper surface terminal C1 of chip C, makes other probes 10c and exposed region
Metal film 40 contact.Hereby it is achieved that the reduction of the resistance and inductance of hookup.It should be noted that for the symbol in figure, 31
It is metal film for chip carrying portion, 41,43 be suction port, 44 is that bypass suction port, 44a are opening portion, 60 are test circuit, 61
It is switching circuit for fusion circuit, 62.
Figure 15 is the major part composition figure of the experimental rig 500 of the reverse recovery characteristic of existing FWD chip.The test
Device 500 has the test electrode 13 for carrying FWD chip 4, contact probe 10, the main electricity for pressing FWD chip 4 and making current flow through
Road is routed F, IGBT 3, loading coil 5, power capacitor 2 and power supply 1.Primary circuit route F is constituted by being routed 11a.
In the Reverse recovery test of FWD chip 4, reverse recovery characteristic after the test test current turn of tidal stream to FWD core
On piece 4 and loading coil 5, become back flow current IF4, and flow for a long time on FWD chip 4.FWD chip 4 is visited by contact
Needle 10 is crimped onto test electrode 13.But the contact resistance at the contact portion of test electrode 13 and contact probe 10 is big, then exists
Power consumption at the contact portion is big.If generating above-mentioned big power consumption for a long time, damage can be brought to test electrode 13.
In addition, the reverse recovery characteristic about FWD chip 4 is tested, it is intended to apply-di/dt to generate predetermined loss, if only
It is the inductance for reducing chip contact portion described in Patent Document 1, then can only reduces the inductance between the anode-cathode of FWD, be inadequate
's.
Existing technical literature
Patent document
Patent document 1: Japanese Unexamined Patent Publication 2008-101944 bulletin
Summary of the invention
Technical problem
The purpose of the present invention is to provide the experimental rigs of the semiconductor chip for the damage for being able to suppress test electrode, test
Method and hookup.
Technical solution
In order to realize that foregoing purpose, first embodiment of the invention are as follows:
Test has power supply, hot end by the experimental rig for the chip for testing the reverse recovery characteristic with diode chip for backlight unit
The low electricity that son is connected to the first switching element of the anode of aforementioned power source, one end passes through the first wiring and aforementioned first switching element
Position terminal connection the load containing inductance, connect with one end of aforementioned load and be used to contact carrying it is aforementioned by tested two poles
The test electrode of the cathode of pipe connects the second of the other end of aforementioned load and the cathode of aforementioned power source via second switch element
It is routed, for contacting aforementioned first for being tested the contact probe of the anode with diode, having support aforementioned contact probe
It holds portion and supports the second support sector for making the other end of aforementioned contact probe and the contact of aforementioned second wiring contact
Support part, cathode are connected to two poles of circuit diode and low potential terminal and aforementioned circuit of one end of aforementioned load
The anode of pipe connects and high potential terminal be connected to aforementioned load the other end third switch element, wherein aforementioned second opens
The potential side terminal for closing element is connected to aforementioned load, and the low potential terminal of aforementioned second switch element is connected to aforementioned second
Wiring.
Technical effect
In accordance with the invention it is possible to provide the experimental rig that can inhibit the semiconductor chip of damage of test electrode and test side
Method.
Detailed description of the invention
Fig. 1 is the major part composition figure of the experimental rig 100 of the semiconductor chip of the first embodiment of the present invention.
Fig. 2 is the test waveform figure of the experimental rig 100 of Fig. 1.
Fig. 3 is the explanatory diagram for illustrating the test method of the second embodiment of the present invention.
Fig. 4 is the explanatory diagram for the test method that map interlinking 3 illustrates the second embodiment of the present invention.
Fig. 5 is the explanatory diagram for the test method that map interlinking 4 illustrates the second embodiment of the present invention.
Fig. 6 is the explanatory diagram for the test method that map interlinking 5 illustrates the second embodiment of the present invention.
Fig. 7 is the explanatory diagram for the test method that map interlinking 6 illustrates the second embodiment of the present invention.
Fig. 8 is the explanatory diagram for the test method that map interlinking 7 illustrates the second embodiment of the present invention.
Fig. 9 is the explanatory diagram for the test method that map interlinking 8 illustrates the second embodiment of the present invention.
Figure 10 is the explanatory diagram for the test method that map interlinking 9 illustrates the second embodiment of the present invention.
Figure 11 is the explanatory diagram of the experimental rig 200 of the semiconductor chip of the third embodiment of the present invention, and (a) is test dress
200 major part composition figure is set, is (b) circuit diagram of hookup 200a.
Figure 12 is the waveform diagram of each section.
Figure 13 is the test schematic and test waveform figure of the reverse recovery characteristic of existing diode chip for backlight unit, and (a) is examination
Circuit diagram is tested, is (b) test waveform figure.
Figure 14 is the composition figure of the characteristic test apparatus of chip C described in Patent Document 1.
Figure 15 is the major part composition figure of the experimental rig 500 of the reverse recovery characteristic of existing FWD chip.
Symbol description
1: power supply
2: power capacitor
3,7,8:IGBT
4:FWD or FWD chip
5: loading coil
6: circuit diode
9: support part
10: contact probe
11: contact
12: parallel flat substrate
12a: the plate of upside
12b: the plate of downside
12c: insulation board
13: test electrode
14,15,16: conductor
R: resistance
100,200: experimental rig
Specific embodiment
Illustrate embodiment according to the following examples.Part same as the prior art indicates the same symbol.
[embodiment one]
Fig. 1 is the major part composition figure of the experimental rig 100 of the semiconductor chip of the first embodiment of the present invention.The examination
Experiment device 100 is the experimental rig tested the reverse recovery characteristic of FWD chip 4, can be realized hookup 100a's
The low inductanceization of primary circuit route F and the damage for preventing test electrode 13.
The experimental rig 100 has the test electrode 13 of mounting FWD chip 4, presses FWD chip 4 and make current flow through
Contact probe 10, contact 11 and contact module 9.Contact 11 is made of acicular electroconductive component, is configured with more.Test
Electrode 13 is set as to load and unload can dismantle when being damaged.It is test electrode 13 at handling with the plate 12b's of downside
Tie point.In addition, having the parallel flat substrate 12 for constituting primary circuit route F, IGBT 3, the IGBT for stopping back flow current
8.In addition, having power supply 1, power capacitor 2, loading coil 5 and round about circuit G.Round about circuit G has IGBT 7 and circuit
With diode 6.Power capacitor 2 is connected to the collector C of IGBT3 via the conductor 16 of positive 2a, and negative electrode 2b is connected to flat
The plate 12a of the upside of row flat panel substrate 12.IGBT 8, IGBT 7, loading coil 5 are interconnected via conductor 14.IGBT 7
It is connected with diode 6 via conductor 15 with circuit.The positive 2a of power capacitor 2 is connected to the current collection of IGBT 3 via conductor 16
Extreme son, negative terminal 2b are connected to the copper sheet 12a of the upside of parallel flat substrate 12.
In addition, pasting conductive plate 12a, 12b across insulation board 12c or more for aforementioned parallel flat substrate 12
To reduce self-induction and mutual inductance.
In Fig. 1, have be equipped with as by the upper of the FWD chip 4 (indicating symbol identical with FWD) of pilot chip
The support part 9 of the contact probe 10 of surface contact, there is the contact 11 being integrally formed with it.Support part 9 is by as first
The contact module 91 of support sector is constituted as the support part 92 of the second support sector and the conductive component 93 of plate.Contact 11
It is fixed in support part 92.In addition, support part 92, which is fixed on conductive component 93 and has, makes contact 11 and conductive component
93 wirings being electrically connected.The support part 9 has elevating mechanism, to decline in FWD Array analysis.If decline,
Contact probe 10 and contact 11 touch the FWD chip 4 that is mounted on base station 13 and the front of parallel flat panel substrate 12 simultaneously
The plate 12a of side utilizes the circuit of short wiring building hookup 100a.Further, for as by the FWD of pilot chip
The connection of the closed circuit of chip 4 and capacitor 2 and IGBT3 utilizes the plate up and down of the parallel flat substrate 12.
By can reduce inductance using the parallel flat substrate 12 ,-di/dt the progress for generating predetermined loss can be applied
Reverse recovery characteristic test.
It should be noted that with the C that small character indicates being collector in figure, E is emitter, A is anode, K is cathode.
Fig. 2 is the test waveform figure of the experimental rig 100 of Fig. 1.VGE3 is the grid voltage of IGBT 3, VGE7 is IGBT 7
Grid voltage, VGE8 be IGBT 8 grid voltage.IF4 is the back flow current for flowing through FWD4, IF6 is by two poles of circuit
Pipe 6 and flow electric current, IL be the electric current for flowing through loading coil 5.
IGBT 3 is connected in t1, disconnecting IGBT 3 in t2 flows back flow current IF4 on FWD 4.It is connected again in t3
IGBT 3 carries out the reverse recovery characteristic test (also testing comprising Reverse recovery tolerance) of FWD 4.IGBT is again off in t4
3, capacitor 2 of cutting off the power.Back flow current IF4 flows on FWD4 again at this time.IGBT 7 is connected in t5, turns off IGBT 8,
Make back flow current IF4 turn of tidal stream to the round about circuit G being made of circuit diode 6 and IGBT 7, flows through electric current IF6.At this
Reverse recovery characteristic off-test at the time of electric current IF6 reduction becomes zero.Therefore, what back flow current IF4 flowed on FWD 4 is
Between t2-t3 between t4-t5 this at two.It is to shorten the electric current (current wave flowed between t4-t5 in the embodiment one
At J in shape) flowing time prevent the damage of test electrode 13.
[embodiment two]
Fig. 3~Figure 10 is the explanatory diagram for illustrating the test method of the second embodiment of the present invention.(a) cutting for experimental rig
Face figure (b) is test schematic.
Firstly, carrying FWD chip 4 on test electrode 13 shown in Fig. 1 in Fig. 3.
Then, in Fig. 4, contact probe 10 is made to touch the anode A of FWD chip 4, makes cathode K and the test of FWD chip 4
Electrode 13 crimps.In addition, make contact 11 touch parallel flat substrate 12 upside plate 12a.It sets IGBT 8 to
IGBT 3 is set off-state by state.
Then, in Fig. 5, IGBT 3 is set as being connected, makes electric current Io (for example, 100A) via loading coil 5, IGBT 8
Flowing.
Then, in Fig. 6, IGBT 3 is disconnected, arrives the electric current turn of tidal stream for returning to power supply 1 via loading coil and IGBT 8
On FWD4.The turn of tidal stream electric current flows back as back flow current IF4 via loading coil 5, IGBT8.Back flow current IF4 becomes FWD4
Scheduled forward current (for example, 100A).
Then, in Fig. 7, IGBT 3 is connected again, fills the short circuit current Is (Io) of scheduled-di/dt from by power supply 1
The power capacitor 2 of electricity flows to FWD chip 4 via IGBT 3.By short circuit current Is, the reflux flowed on FWD chip 4
Electric current IF4 (forward current of FWD chip 4) is cancelled, and FWD chip 4 enters the Reverse recovery stage.It is flowed through on FWD chip 4 pre-
The reverse recovery current of fixed-di/dt applies Reverse recovery voltage.The Reverse recovery is born, if FWD chip 4 can
It is then qualified to bear, unqualified if damage.- the di/dt for flowing short circuit current Is depends on the electricity of primary circuit route F
Sense.Reduce the inductance, reverse recovery characteristic test is carried out at big-di/dt and is very important.In addition, measurement is reversed extensive
The reverse recovery characteristic of telegram in reply stream and/or Reverse recovery voltage etc..
Then, in Fig. 8, back flow current IF4 flows to power supply 1 as electric current Io after the Reverse recovery test of FWD chip 4.
Then, in Fig. 9, it is again off IGBT 3, back flow current IF4 flows on FWD4 chip again.
Then, in Figure 10, IGBT 8 is disconnected while 7 IGBT are connected, makes the electric current IL flowed on loading coil 5
Turn of tidal stream disconnects the back flow current IF4 flowed on FWD chip 4 to round about circuit G.Turn of tidal stream is to round about circuit G and in circuit with two
The stage that the electric current IF6 flowed in pole pipe 6 becomes zero takes out FWD chip 4 from test electrode 13, reverse recovery characteristic test
Terminate.
By making substantially shorten on the back flow current IF4 turn of tidal stream to round about circuit G flowed on FWD chip 4
During the circulation of the back flow current IF4 flowed on FWD chip 4, the damage of test electrode 13 can be prevented.With regard to the test electrode 13
Damage for FWD chip 4 reverse recovery characteristic test in damage in the case where, the melting of chip can be to test electrode 13
It has an impact and causes to damage.Therefore, the damage of test electrode 13 can be only prevented in the case where FWD 4 qualification of chip.
[embodiment three]
Figure 11 is the explanatory diagram of the experimental rig 200 of the semiconductor chip of the third embodiment of the present invention, and (a) is test dress
200 major part composition figure is set, (b) is the circuit diagram 200a of experimental rig 200.Difference with the experimental rig 100 of Fig. 1 exists
In deletion round about circuit G has been connected in parallel resistance R on IGBT 8.Make the back flow current IF4 flowed on FWD 4 due to electricity
Resistance R is reduced rapidly, and prevents the damage of test electrode 13.Because without round about circuit G circuit becomes simply, in addition, not scheming
The driving circuit shown can also become simple.
Figure 12 is the waveform diagram of each section.The decaying of the back flow current IF4 in the portion Q becomes larger due to resistance R, can prevent from trying
The damage of electrical verification pole 13.
It should be noted that the example for using IGBT as test switch element is shown in embodiment one, two above-mentioned,
But it is not limited to this, and MOSFET or bipolar junction transistor etc. also can be used.
Claims (9)
1. a kind of experimental rig of chip, which is characterized in that carried out to by the reverse recovery characteristic of test diode chip for backlight unit
The experimental rig of the chip of test, has:
Power supply；
First switching element, the high potential terminal of first switching element are connected to the anode of the power supply；
Load, one end is connect by the first wiring with the low potential terminal of the first switching element, and contains inductance；
Test electrode, connect and be used for one end of the load with the cathode contacts by test diode chip for backlight unit
Mode carries the cathode by test diode chip for backlight unit；
Second wiring, the other end of the load and the cathode of the power supply are connected via second switch element；
Contact probe, for contacting the anode by test diode chip for backlight unit；
Support part has the first support sector for supporting the contact probe and supports the other end for making the contact probe
With the second support sector of the contact of second wiring contact；
The cathode of circuit diode, circuit diode is connected to one end of the load；
The low potential terminal of third switch element, third switch element is connect with the anode of circuit diode, and third is opened
The high potential terminal for closing element is connected to the other end of the load,
Wherein, the potential side terminal of the second switch element is connected to the load, the low electricity of the second switch element
Position terminal is connected to second wiring.
2. the experimental rig of chip according to claim 1, which is characterized in that the circuit diode and the third
Switch element constitutes round about circuit.
3. a kind of experimental rig of chip, which is characterized in that carried out to by the reverse recovery characteristic of test diode chip for backlight unit
The experimental rig of the chip of test, has:
Power supply；
First switching element, the high potential terminal of first switching element are connected to the anode of the power supply；
Load, one end is connect by the first wiring with the low potential terminal of the first switching element, and contains inductance；
Test electrode, connect and be used for one end of the load with the cathode contacts by test diode chip for backlight unit
Mode carries the cathode by test diode chip for backlight unit；
Second wiring, the other end of the load and the cathode of the power supply are connected via second switch element；
Contact probe, for contacting the anode by test diode chip for backlight unit；
Support part has the first support sector for supporting the contact probe and supports the other end for making the contact probe
With the second support sector of the contact of second wiring contact；
Resistance is connect with the second switch element in parallel,
Wherein, the potential side terminal of the second switch element is connected to the load, the low electricity of the second switch element
Position terminal is connected to second wiring.
4. the experimental rig of chip according to claim 1 or 3, which is characterized in that first wiring and the second wiring
It is centre across the parallel flat substrate of insulation board.
5. the experimental rig of chip according to claim 1 or 3, which is characterized in that the support part has elevator
Structure.
6. a kind of test method of chip, which is characterized in that
In the experimental rig of chip described in claim 1 or 3, touch the contact probe described by two poles of test
The anode of tube chip, while the contact being made to touch second wiring to carry out reverse recovery characteristic test.
7. the test method of chip according to claim 6, which is characterized in that described to be with diode chip for backlight unit by test
Any of FWD chip, pn-junction diode chip for backlight unit, body diode of MOSFET chip.
8. a kind of hookup of chip, which is characterized in that the hookup has:
Power supply；
First switching element, the high potential terminal of first switching element are connected to the anode of the power supply；
Load, one end is connect with the low potential terminal of the first switching element, and contains inductance；
By test diode chip for backlight unit, it is connect by the cathode of test diode chip for backlight unit with one end of the load；
Second switch element, the potential side terminal of second switch element are connect with the other end of the load, second switch member
The low potential terminal of part is connect with the cathode of the power supply；
The cathode of circuit diode, circuit diode is connected to one end of the load；
The low potential terminal of third switch element, third switch element is connect with the anode of circuit diode, and third is opened
The high potential terminal for closing element is connected to the other end of the load,
Wherein, the low potential side terminal of the second switch element is connect with the anode by test diode chip for backlight unit.
9. a kind of hookup of chip, which is characterized in that the hookup has:
Power supply；
First switching element, the high potential terminal of first switching element are connected to the anode of the power supply；
Load, one end is connect with the low potential terminal of the first switching element, and contains inductance；
By test diode chip for backlight unit, it is connect by the cathode of test diode chip for backlight unit with one end of the load；
Second switch element, the potential side terminal of second switch element are connect with the other end of the load, second switch member
The low potential terminal of part is connect with the cathode of the power supply；
Resistance is connect with the second switch element in parallel,
Wherein, the low potential side terminal of the second switch element is connect with the anode by test diode chip for backlight unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014-119568 | 2014-06-10 | ||
| JP2014119568A JP6369151B2 (en) | 2014-06-10 | 2014-06-10 | Semiconductor chip test apparatus, test method, and test circuit |
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| Publication Number | Publication Date |
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| CN105277864A CN105277864A (en) | 2016-01-27 |
| CN105277864B true CN105277864B (en) | 2019-05-10 |
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| JP6332165B2 (en) * | 2015-06-25 | 2018-05-30 | 株式会社デンソー | Semiconductor element inspection apparatus and inspection method |
| CN109073705B (en) * | 2016-11-16 | 2021-03-23 | 富士电机株式会社 | Semiconductor test circuit, semiconductor test apparatus, and semiconductor test method |
| JP7052409B2 (en) * | 2017-05-26 | 2022-04-12 | 富士電機株式会社 | Pulse current application circuit and its control method |
| JP7304299B2 (en) | 2020-01-29 | 2023-07-06 | 株式会社アドバンテスト | power module |
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| JP2008175700A (en) * | 2007-01-19 | 2008-07-31 | Matsushita Electric Ind Co Ltd | Inspection device or inspection method for semiconductor device |
| CN102313864A (en) * | 2010-06-02 | 2012-01-11 | 富士电机株式会社 | Testing apparatus and method of testing |
| JP2013057589A (en) * | 2011-09-08 | 2013-03-28 | Fuji Electric Co Ltd | Characteristic test device for semiconductor element and method for testing characteristic of semiconductor element using the same |
| CN203178427U (en) * | 2013-01-30 | 2013-09-04 | 苏州同冠微电子有限公司 | Tester for diode reverse recovery characteristic |
| CN104167374A (en) * | 2013-05-17 | 2014-11-26 | 富士电机株式会社 | Testing device for semiconductor chip and testing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4663930B2 (en) * | 2001-09-12 | 2011-04-06 | 日本インター株式会社 | Reverse recovery time characteristic measuring device |
| KR101091202B1 (en) * | 2009-09-28 | 2011-12-09 | 한국전기연구원 | A precision measuring equipment for extracting a reverse recovery time of high-speed power semiconductor |
| JP5413349B2 (en) * | 2010-09-30 | 2014-02-12 | 富士電機株式会社 | Semiconductor test equipment and semiconductor test circuit connection equipment |
| JP5742681B2 (en) * | 2011-11-18 | 2015-07-01 | トヨタ自動車株式会社 | Semiconductor device test apparatus and test method thereof |
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- 2014-06-10 JP JP2014119568A patent/JP6369151B2/en active Active
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008175700A (en) * | 2007-01-19 | 2008-07-31 | Matsushita Electric Ind Co Ltd | Inspection device or inspection method for semiconductor device |
| CN102313864A (en) * | 2010-06-02 | 2012-01-11 | 富士电机株式会社 | Testing apparatus and method of testing |
| JP2013057589A (en) * | 2011-09-08 | 2013-03-28 | Fuji Electric Co Ltd | Characteristic test device for semiconductor element and method for testing characteristic of semiconductor element using the same |
| CN203178427U (en) * | 2013-01-30 | 2013-09-04 | 苏州同冠微电子有限公司 | Tester for diode reverse recovery characteristic |
| CN104167374A (en) * | 2013-05-17 | 2014-11-26 | 富士电机株式会社 | Testing device for semiconductor chip and testing method |
Also Published As
| Publication number | Publication date |
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| CN105277864A (en) | 2016-01-27 |
| JP2015232501A (en) | 2015-12-24 |
| JP6369151B2 (en) | 2018-08-08 |
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