CN115997285A - 硅通孔结构的制备方法和硅通孔结构 - Google Patents

硅通孔结构的制备方法和硅通孔结构 Download PDF

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Publication number
CN115997285A
CN115997285A CN202080103632.4A CN202080103632A CN115997285A CN 115997285 A CN115997285 A CN 115997285A CN 202080103632 A CN202080103632 A CN 202080103632A CN 115997285 A CN115997285 A CN 115997285A
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CN
China
Prior art keywords
holes
substrate layer
layer
metal
pattern
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Pending
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CN202080103632.4A
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English (en)
Inventor
李珩
张晓东
胡天麒
戚晓芸
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN115997285A publication Critical patent/CN115997285A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本申请提供一种硅通孔结构的制备方法和硅通孔结构。该制备方法包括：提供晶圆，该晶圆包括衬底层、介质层和金属层；从衬底层的第二侧形成贯穿衬底层的导通孔，该导通孔停止在金属层上；从衬底层的第二侧形成凹孔；在衬底层的第二侧的表面、导通孔内和凹孔内沉积金属；对金属进行研磨，以去除衬底层的第二侧的表面上的除导通孔和凹孔之外的区域上的金属。本申请中凹孔的设置能够使得在衬底层上没有导通孔的地方增加金属，有助于在研磨过程中金属尽可能地均匀分布，从而有助于提高研磨工艺的一致性和可靠性。另外，本申请中导通孔对应的TSV可以不是TSV array，因而够根据产品需要，灵活地设计TSV图案，增大工艺窗口。

Description

PCT国内申请，说明书已公开。

Claims (17)

  1. PCT国内申请，权利要求书已公开。
CN202080103632.4A 2020-09-27 2020-09-27 硅通孔结构的制备方法和硅通孔结构 Pending CN115997285A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/118157 WO2022061825A1 (zh) 2020-09-27 2020-09-27 硅通孔结构的制备方法和硅通孔结构

Publications (1)

Publication Number Publication Date
CN115997285A true CN115997285A (zh) 2023-04-21

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CN202080103632.4A Pending CN115997285A (zh) 2020-09-27 2020-09-27 硅通孔结构的制备方法和硅通孔结构

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EP (1) EP4210093A4 (zh)
CN (1) CN115997285A (zh)
WO (1) WO2022061825A1 (zh)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232231B1 (en) * 1998-08-31 2001-05-15 Cypress Semiconductor Corporation Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect
US6611045B2 (en) * 2001-06-04 2003-08-26 Motorola, Inc. Method of forming an integrated circuit device using dummy features and structure thereof
JP2011515843A (ja) * 2008-03-19 2011-05-19 アイメック 基板貫通バイアの作製方法
JP2011258687A (ja) * 2010-06-08 2011-12-22 Renesas Electronics Corp 半導体装置およびその製造方法
US8853857B2 (en) * 2011-05-05 2014-10-07 International Business Machines Corporation 3-D integration using multi stage vias
CN102969270A (zh) * 2011-08-31 2013-03-13 上海华力微电子有限公司 半导体器件及其制作方法
CN102446827A (zh) * 2011-09-23 2012-05-09 上海华力微电子有限公司 一种去除金属层冗余金属填充的制造工艺
CN102354682B (zh) * 2011-10-29 2014-04-09 上海华力微电子有限公司 半导体器件制作方法
US8883638B2 (en) * 2012-01-18 2014-11-11 United Microelectronics Corp. Method for manufacturing damascene structure involving dummy via holes
US9287197B2 (en) * 2013-03-15 2016-03-15 Globalfoundries Singapore Pte. Ltd. Through silicon vias
CN103855044B (zh) * 2014-03-31 2016-09-07 上海华力微电子有限公司 一种添加冗余图形的方法
US9704784B1 (en) * 2016-07-14 2017-07-11 Nxp Usa, Inc. Method of integrating a copper plating process in a through-substrate-via (TSV) on CMOS wafer

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Publication number Publication date
EP4210093A4 (en) 2023-11-15
WO2022061825A1 (zh) 2022-03-31
EP4210093A1 (en) 2023-07-12

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