WO2022061825A1 - 硅通孔结构的制备方法和硅通孔结构 - Google Patents

硅通孔结构的制备方法和硅通孔结构 Download PDF

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Publication number
WO2022061825A1
WO2022061825A1 PCT/CN2020/118157 CN2020118157W WO2022061825A1 WO 2022061825 A1 WO2022061825 A1 WO 2022061825A1 CN 2020118157 W CN2020118157 W CN 2020118157W WO 2022061825 A1 WO2022061825 A1 WO 2022061825A1
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Prior art keywords
holes
hole
substrate layer
layer
concave
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PCT/CN2020/118157
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English (en)
French (fr)
Inventor
李珩
张晓东
胡天麒
戚晓芸
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华为技术有限公司
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Priority to PCT/CN2020/118157 priority Critical patent/WO2022061825A1/zh
Priority to CN202080103632.4A priority patent/CN115997285A/zh
Priority to EP20954676.1A priority patent/EP4210093A4/en
Publication of WO2022061825A1 publication Critical patent/WO2022061825A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • the present application relates to the technical field of chip packaging, and more particularly, to a method for preparing a TSV structure and a TSV structure.
  • chip packaging technology has gradually developed to a mature three-dimensional (3-dimensional, 3D) stacking method. By stacking, the chip packaging area can be minimized, thereby reducing the cost of build of material (BOM).
  • Stacked packaging technology can be applied to microsystem integration, and is a packaging manufacturing technology developed after system-on-a-chip (SoC) and multi-chip module (MCM).
  • SoC system-on-a-chip
  • MCM multi-chip module
  • the present application provides a method for preparing a TSV structure and a TSV structure, which can flexibly prepare the TSV structure.
  • a method for preparing a TSV structure including the following steps: providing a wafer, the wafer includes a substrate layer, a dielectric layer and a metal layer, wherein the metal layer is wrapped around the dielectric layer wherein the dielectric layer and the metal layer are located on a first side of the substrate layer; a via hole is formed through the substrate layer from the second side of the substrate layer, and the via hole stops at the on the metal layer; forming a concave hole from the second side of the substrate layer; depositing metal on the surface of the second side of the substrate layer, in the via hole and in the concave hole; grinding the metal , to remove metal on the surface of the second side of the substrate layer except for the via hole and the concave hole.
  • concave holes and via holes for forming TSVs can be formed from one side of the substrate layer, and the substrate layer is opposite to the substrate layer on the side of the substrate layer.
  • the metal is deposited on the surface, vias and concave holes, so that when the metal on the surface of the substrate layer is ground, the setting of the concave holes can add metal to the places where there are no via holes on the substrate layer, which is helpful for the grinding process.
  • the metal is distributed as evenly as possible, helping to improve the consistency and reliability of the grinding process.
  • the TSV corresponding to the via hole may not be a TSV array, or a TSV array verified by a vendor (vendor).
  • the TSV of the wafer can be equivalent to the TSV array, or the TSV array verified by the vendor, in the subsequent grinding process. Therefore, compared with the TSV fabrication scheme without the formation of concave holes, the embodiments of the present application can help to make the distribution of metal more uniform in the subsequent grinding process, thereby reducing the complexity of grinding.
  • the present application can flexibly design a TSV pattern and increase the process window according to product needs.
  • the above-mentioned grinding of the metal may start grinding of the metal deposited from the second side of the substrate layer.
  • the second side of the substrate layer may still continue to be ground, which is not limited in this application.
  • a suitable concave hole depth may be set.
  • the depth of the concave holes cannot be too shallow, and it is necessary to ensure that there is always metal in the concave holes during or after the grinding process.
  • the depth of the concave hole should not be too deep, so as not to affect the performance of the device or increase the difficulty of the process.
  • the depth of the concave hole may be 1 micrometer ( ⁇ m) to 30 micrometers, which is not limited in the present application.
  • the etching time (or the etching time and the etching rate) can be controlled, so that when the etching process for the via hole ends, The metal layer is exposed inside.
  • the wafer may include an etch stop layer, which is located between the metal layer and the substrate layer, for example, may be connected to the surface of the metal layer.
  • the etching time or controlling the etching time and the etching rate
  • the etching barrier layer can be etched, for example, by controlling the etching time (or controlling the etching time and the etching rate), so that after the second time period ends, the via hole stops on the metal layer.
  • the number of the via holes is at least one, the number of the concave holes is at least one, and each of the via holes is at the bottom of the substrate layer.
  • a first pattern is formed on the surface of the second side, each of the recesses forms a second pattern on the surface of the second side of the substrate layer, wherein at least one of the first patterns is formed on the surface of the second side In a pattern and at least one of the second patterns, the distance between any two adjacent patterns in the width direction is the same, and/or the distance between any adjacent two patterns in the length direction is the same.
  • the TSV corresponding to the at least one first pattern that is, the TSV corresponding to the via hole
  • the dummy pad corresponding to the at least one second pattern that is, the dummy pad corresponding to the concave hole
  • the effect is the TSV array constructed during the preparation process of the TSV structure, that is, the TSV corresponding to the at least one first pattern and the dummy pad corresponding to the at least one second pattern together can be called the equivalent TSV array of the wafer.
  • any two adjacent ones in the width direction and/or the length direction is the same, which can help the vias and recesses to be evenly distributed on the surface of the substrate layer, which in turn helps to make the wafer have an equivalent TSV array, which helps to make the metal evenly distributed in the subsequent grinding process .
  • any two adjacent patterns described above may include a pattern corresponding to the concave hole and a pattern of the via hole adjacent to the concave hole, and a pattern corresponding to the concave hole and a pattern adjacent to the concave hole The pattern of another concave hole, the pattern corresponding to the via hole, and the pattern of another via hole adjacent to the via hole.
  • the number of the via holes is 1, the number of the concave holes is 8, and the 8 concave holes are evenly distributed in the conductive holes. around the through hole.
  • the distance between any two adjacent patterns in the length direction is the same, and the distance between any adjacent two patterns in the width direction is the same.
  • the distances between the patterns are the same, i.e., the wafer has an equivalent TSV array of 3 ⁇ 3.
  • any adjacent The two patterns have the same distance in the length direction, and any adjacent two patterns have the same distance in the width direction.
  • the number of added recesses may be 15, making the equivalent TSV array of the wafer a 4 ⁇ 4 TSV array, and for another example, the number of added recesses may be 11, so that the wafer has a 4 ⁇ 3 TSV array The equivalent TSV array of .
  • the number of the via holes is multiple, and the plurality of via holes includes a first portion of the via hole and a second portion of the via hole, wherein, On the surface of the second side of the substrate layer, there is a first distance between any two adjacent via holes in the first partial via holes in the first direction, and in the second partial via hole If there is a second distance between any two adjacent via holes in the first direction, and the first distance is an integer multiple of the second distance, the concave hole is located in the first part of the conductive hole. Between two adjacent through holes in the first direction in the through holes, wherein the first direction is the length direction or the width direction.
  • the pattern corresponding to the concave hole may be located between two adjacent patterns in the first direction in the first partial pattern, so that after the concave hole is added, the The distance between two adjacent patterns in the first direction in the pattern corresponding to the first partial pattern and the concave hole is also the second distance.
  • the patterns formed on the lower surface of the entire substrate layer have the same distance between any two adjacent patterns in the first direction, that is, the second distance. Therefore, the embodiments of the present application can help the via holes and the concave holes to be evenly distributed on the surface of the substrate layer, thereby helping the wafer to have an equivalent TSV array, thereby helping to make the metal uniform in the subsequent grinding process distributed.
  • the first distance between any two adjacent via holes in the first direction in the first portion of the via holes on the surface of the substrate layer is greater than that in the second portion of the via holes
  • the second distance between any two adjacent via holes in the first direction but when the first distance is not an integer multiple of the second distance, at least one concave hole may still be provided in the first part of the conductive hole
  • the pattern formed by the concave holes and the via holes on the surface of the substrate layer looks as regular or uniform as possible, so that the via holes and the concave holes can be evenly distributed on the surface of the substrate layer, which helps To make the metal evenly distributed during the subsequent grinding process.
  • the distances between adjacent via holes in the width direction or the length direction are different.
  • concave holes can be added between the via holes, so that the pattern formed by the concave holes and the via holes on the surface of the substrate layer looks as regular or uniform as possible, which can help the via holes and the concave holes to be evenly distributed On the surface of the substrate layer, it helps to make the metal evenly distributed during the subsequent grinding process.
  • concave holes can still be added between the via holes.
  • a concave hole can be added, so that the equivalent TSV array corresponding to the pattern formed by the concave hole and the via hole is the TSV array verified by the vendor.
  • the TSV array corresponding to the via hole is a TSV array with a larger pitch, since the via hole is relatively sparse, the metal distribution will be uneven when the metal is subsequently ground.
  • the equivalent TSV array pitch of the wafer is made smaller, which can help to make the metal distribution more uniform during subsequent grinding.
  • the shape of the concave hole (ie, the top view of the concave hole) on the surface of the second side of the substrate layer is a circle, a rectangle or a diamond.
  • the shape of the concave hole on the surface of the second side of the substrate layer may be the same as or similar to the shape of the via hole (ie, the top view of the via hole), for example, both are circles with the same or similar diameter shape, which is not limited in this application.
  • the pattern formed by the concave holes on the surface of the second side of the substrate layer may have a different shape or size from the pattern formed by the via hole, for example, the pattern formed by the via hole may be circular , and the pattern formed by the concave holes is a rhombus or a rectangle, etc., which is not limited in this application.
  • the depositing metal on the surface of the second side of the substrate layer, in the via hole and in the recessed hole may include: A liner layer, a barrier layer and a seed layer are sequentially formed on the surface of the second side of the substrate layer, in the via hole and in the concave hole, and then depositing the metal on the seed layer through an electroplating process .
  • the above-mentioned liner layer can improve the flatness and stress buffer of the etched surface, and also has a blocking effect.
  • the barrier layers described above can be used to prevent metal diffusion, eg, into Si or SiO 2 , to improve device performance.
  • the above-mentioned seed layer is used for conducting electricity, so as to generate a metal thin film layer by means of electroplating.
  • the metal when the metal is ground, it can be stopped when the grinding reaches the liner layer, or stopped when the grinding reaches the substrate layer, or the grinding can be continued when the grinding reaches the substrate layer and concave after the grinding is completed. There is still metal remaining in the hole, or the grinding stops when there is no metal remaining in the concave hole, which is not limited in this application.
  • the barrier layer includes Ta or TaN.
  • the seed layer includes Cu.
  • the metal thin film layer includes Cu.
  • a through silicon via structure including a substrate layer, a dielectric layer, a metal layer, a via hole and a concave hole, wherein the metal layer is wrapped in the dielectric layer, and the dielectric layer and the The metal layer is located on the first side of the substrate layer, the via hole penetrates the substrate layer from the second side of the substrate layer, and stops on the metal layer, and the concave hole extends from the substrate layer. formed on the second side of the via hole and metal is deposited in the via hole and the concave hole.
  • the number of the via holes is at least one, the number of the concave holes is at least one, and each of the via holes is at the bottom of the substrate layer.
  • a first pattern is formed on the surface of the second side, each of the recesses forms a second pattern on the surface of the second side of the substrate layer, wherein at least one of the first patterns is formed on the surface of the second side A pattern and any two adjacent patterns in at least one of the second patterns have the same distance in the width direction, and/or the same distance in the length direction.
  • the number of the via holes is 1, the number of the concave holes is 8, and the 8 concave holes are evenly distributed in the conductive holes. around the through hole.
  • the number of the via holes is multiple, and the plurality of via holes includes a first portion of the via hole and a second portion of the via hole, wherein, On the surface of the second side of the substrate layer, there is a first distance between any two adjacent via holes in the first partial via holes in the first direction, and in the second partial via hole Any two adjacent via holes have a second distance in the first direction, and the first distance is an integer multiple of the second distance, then the concave hole is located in the first part of the via hole between two adjacent via holes in the first direction, wherein the first direction is the length direction or the width direction.
  • the shape of the recessed hole on the surface of the second side of the substrate layer is a circle, a rectangle or a diamond.
  • the depth of the recessed holes is 1 micrometer to 30 micrometers.
  • FIG. 1 is a schematic flowchart of a method for preparing a TSV structure provided by an embodiment of the present application
  • 2A is an example of a side view of a provided wafer
  • 2B is an example of a side view of a wafer during the preparation of a TSV structure
  • 2C is another example of a side view of a wafer during the fabrication of a TSV structure
  • 2D is another example of a side view of a wafer during the fabrication of a TSV structure
  • 2E is an example of a side view of the TSV structure in the present application.
  • Figure 3 is an example of a side view of the provided wafer
  • FIG. 4 is another example of a side view of a wafer during the preparation of a TSV structure
  • Figure 5 is an example of an equivalent TSV array of a wafer
  • 6A is a schematic diagram of a pattern formed by a via hole on the surface of the substrate layer
  • 6B is a schematic diagram of adding 8 concave holes around a via hole
  • 7A is a schematic diagram of a pattern of formation of a plurality of vias on the surface of the substrate layer
  • 7B is a schematic diagram of adding a concave hole in a plurality of vias
  • 8A is another schematic diagram of a pattern of formation of a plurality of vias on the surface of the substrate layer
  • 8B is another schematic diagram of adding a concave hole in a plurality of vias
  • 9A is another schematic diagram of a pattern of formation of a plurality of vias on the surface of the substrate layer
  • 9B is another schematic diagram of adding a concave hole in a plurality of vias
  • 10A is another schematic diagram of a pattern of formation of a plurality of vias on the surface of the substrate layer
  • FIG. 10B is another schematic diagram of adding a concave hole to a plurality of vias
  • 11A is another schematic diagram of a pattern of formation of a plurality of vias on the surface of the substrate layer
  • FIG. 11B is another schematic diagram of adding a concave hole in a plurality of vias
  • 12A is another schematic diagram of a pattern of formation of a plurality of vias on the surface of the substrate layer
  • 12B is another schematic diagram of adding a concave hole to a plurality of vias
  • FIG. 13 is another example of a side view of a wafer during the preparation of a TSV structure
  • 15A is another example of a side view of the TSV structure in the present application.
  • 15B is another example of a side view of the TSV structure in the present application.
  • Figure 15C is another example of a side view of a TSV structure in the present application.
  • FIG. 15D is another example of a side view of a TSV structure in the present application.
  • FIG. 1 is a schematic flowchart of a method 100 for fabricating a TSV structure provided by an embodiment of the present application
  • FIGS. 2A to 2E are a specific example of a process flowchart corresponding to the method 100 .
  • the method 100 for fabricating the TSV structure shown in FIG. 1 will be described with reference to the process flow shown in FIG. 2A to FIG. 2E .
  • the method 100 includes steps 110 to 150 .
  • Step 110 providing a wafer, the wafer includes a substrate layer, a dielectric layer and a metal layer, wherein the metal layer is wrapped in the dielectric layer, and the dielectric layer and the metal layer are located on the substrate layer. first side.
  • the wafer includes a substrate layer 01, a dielectric layer 02 and a metal layer 03, wherein the metal layer 03 is wrapped in the dielectric layer 02, and both the dielectric layer 02 and the metal layer 03 are located on the first side of the substrate layer 01, for example The portion above the first surface 011 (ie, the surface of the first side) of the substrate layer 01 .
  • the substrate layer in the present application may be a semiconductor substrate layer, such as a silicon substrate, a silicon germanium substrate, a sapphire substrate, etc., without limitation.
  • a device layer may also be included, and the device layer may be located between the substrate layer and the metal layer.
  • the device layer may include an active region, a drain region, a well region, etc., which is not limited in this application.
  • FIG. 3 shows an example of the structure of the wafer.
  • the device layer 04 may be located between the substrate layer 01 and the metal layer 03 (or the dielectric layer 02 ), and the device layer 04 may include an active region 041 , a drain region 042 , a well region 043 and a well region 044 .
  • FIG. 3 shows an example of a wafer, but this does not limit the application.
  • the wafers involved in this application may also be wafers with other structures other than FIG. 3 , which are all covered in this application. within the scope of protection.
  • the wafer may also include other layer structures, such as buffer layers, barrier layers, etc., and these layer structures may be located on the first side of the substrate layer, for example, between the dielectric layer and the substrate layer, which is not limited in this application.
  • the wafer may also be subjected to pre-processing for TSV preparation, such as substrate thinning (eg, thinning from hundreds of ⁇ m to tens of ⁇ m), grinding, etc., which are not limited in this application.
  • substrate thinning eg, thinning from hundreds of ⁇ m to tens of ⁇ m
  • grinding etc.
  • the polishing can be chemical mechanical polishing (CMP), or physical polishing, etc., which is not limited.
  • CMP chemical mechanical polishing
  • chemical mechanical polishing may also be called chemical mechanical polishing, which is not limited in this application.
  • Step 120 forming a via hole through the substrate layer from the second side of the substrate layer, the via hole stopping on the metal layer.
  • the number of the via holes may be one or more, which is not limited.
  • FIG. 2B an example of a side view of the wafer corresponding to step 120 is shown.
  • via holes 05 and 06 may be further formed on the wafer starting from the second side of the substrate layer 01 , and the via holes 05 and 06 pass through the substrate layer 01 , that is, the via holes are connected to each other.
  • the two opposite surfaces of the substrate layer 01 such as the first surface 011 and the second surface 012 (ie, the surfaces on the second side).
  • the vias 05 and 06 finally stop on the metal layer 03 .
  • step 120 only one via hole may be formed, or more via holes may be formed.
  • the via holes may be prepared by processes such as photolithography and etching.
  • the etching process is, for example, deep reactive ion etching (DRIE), deep plasma etching, etc., which is not limited in this application.
  • DRIE deep reactive ion etching
  • the etching time (or the etching time and the etching rate) can be controlled, so that when the etching process for the via hole ends, The metal layer is exposed inside.
  • the wafer may include an etch stop layer, which is located between the substrate layer and the metal layer, for example, may be connected to the surface of the metal layer (eg, FIG. 2B ).
  • the lower surface 031) of the metal layer 03 in the connection At this time, by controlling the etching time (or controlling the etching time and the etching rate), after the end of the first period of time, the via hole stops on the etching barrier layer.
  • Figure 4 shows an example where the via stops on the etch stop layer. As shown in FIG.
  • the via holes 05 and 06 stop on the etch stop layer 032 under the lower surface 031 of the metal layer 03 , at this time, the etch stop layer is exposed inside the via holes 05 and 06 032.
  • the etching barrier layer 032 can be etched, for example, by controlling the etching time (or controlling the etching time and the etching rate), so that after the second time period ends, the via holes 05 and 06 stop at on the metal layer 03.
  • the metal layer is exposed inside the via holes 05 and 06, that is, the structure shown in FIG. 2B is obtained.
  • the etching depth can be effectively controlled, which helps to avoid the etching depth being too deep or the etching depth being too shallow.
  • the metal layer may be completely etched, and when the etching depth is too shallow, the etching may stop when the metal layer is not exposed in the via hole.
  • the via hole generated in step 120 is used to form a TSV, so it may also be called a TSV hole, or may be called a TSV deep hole, which is not limited in this application.
  • the via holes will form a pattern, and the pattern is the via holes on the second side of the substrate layer 01 .
  • the via hole may be said to correspond to the TSV formed by the via hole, or the pattern formed by the via hole on the surface of the second side of the substrate layer may correspond to the TSV formed by the via hole.
  • the pattern formed by the via hole on the surface of the second side of the substrate layer is not limited.
  • the TSV corresponding to the pattern may be a part of the TSV array, or a complete TSV array, or the pattern
  • the corresponding TSV may include at least two TSV arrays with different pitches, or the TSV corresponding to the pattern may be a single (isolation) TSV, or the distance between two adjacent TSVs in the TSV corresponding to the pattern is different,
  • the TSV array formed by the TSV corresponding to the pattern may be the TSV array verified by the vendor (vendor), or may not be the TSV array verified by the vendor.
  • the TSV array may include at least two TSVs in the width direction and at least two TSVs in the length direction, and the distance between any two adjacent TSVs in the length direction (this distance may be referred to as the TSV array in the length direction).
  • the pitch on the TSV array is the same, and the distance in the width direction of any two adjacent TSVs (this distance can be referred to as the pitch of the TSV array in the width direction) is the same.
  • the TSV array may be an array composed of at least two TSVs with fixed pitches in both the width direction and the length direction.
  • the TSV array may be called an m ⁇ n TSV array.
  • m and n are positive integers respectively.
  • the number of TSVs in the width direction in the TSV array is the same or different from the number of TSVs in the length direction, and the distance between any two adjacent TSVs in the length direction is the same as that of any two TSVs in the width direction.
  • the distances above may be the same or different, which is not limited in this application.
  • the process flow of forming the via hole may be fine-tuned according to the actual situation, which is not limited in the embodiment of the present application.
  • Step 130 forming concave holes from the second side of the substrate layer.
  • the number of concave holes may be one or more, which is not limited.
  • a concave hole 07 may be further formed on the second side of the substrate layer 01 (ie, starting from the second surface 012 ).
  • the concave hole 07 may not penetrate the substrate layer 01 .
  • FIG. 2C only takes the formation of the concave hole 07 as an example, and the present application is not limited thereto.
  • a plurality of recessed holes may also be formed.
  • the above-mentioned concave holes may be prepared by processes such as photolithography and etching. Specifically, for processes such as photolithography and etching, reference may be made to the above description, and details are not repeated here.
  • the shape of the concave hole is not limited.
  • the shape of the concave hole may be a cylinder, a quadrangular prism, a terrace or other shapes.
  • the pattern of the concave holes formed on the surface of the second side of the substrate layer ie, the top view of the concave holes
  • the shape of the concave hole (or the top view of the concave hole) should be selected as much as possible to make the processing of the subsequent process (such as CMP) as convenient as possible, or to have a lower process risk, such as uniform flatness , roughness, no metal residue, etc.
  • the pattern formed by the concave holes on the surface of the second side of the substrate layer may be the same as or similar to the pattern formed by the via holes, for example, both are circles with the same or similar diameters.
  • the application is not limited in this regard.
  • the pattern formed by the concave holes on the surface of the second side of the substrate layer may have a different shape or size from the pattern formed by the via hole, for example, the pattern formed by the via hole may be circular , and the pattern formed by the concave holes is a rhombus or a rectangle, etc., which is not limited in this application.
  • the embodiment of the present application does not limit the depth of the concave hole.
  • the depth of the recessed holes may be 1 micrometer ( ⁇ m) to 30 micrometers, for example, may be 2 ⁇ m. It should be noted that the setting of the concave hole does not need to be too deep, so as not to affect the performance of the device or increase the difficulty of the process.
  • the concave hole may be used to form a dummy pad, and the concave hole may also be called a dummy hole.
  • the position of the concave hole corresponds to the position of the dummy pad (or the position of the pad).
  • the pattern formed by the concave holes may be located between or around the pattern formed by the via holes.
  • each via hole forms a first pattern on the surface of the second side of the substrate layer
  • each concave via hole forms a second pattern on the surface of the second side of the substrate layer. That is, at least one via hole may form at least one first pattern, and at least one concave hole may form at least one second pattern.
  • any two adjacent patterns in the at least one first pattern and the at least one second pattern have the same distance in the width direction and/or the same distance in the length direction.
  • the TSV corresponding to the at least one first pattern and the dummy pad corresponding to the at least one second pattern can be equivalent to the TSV array constructed during the preparation process of the TSV structure, that is, the TSV corresponding to the at least one first pattern. Together with the dummy pad corresponding to the at least one second pattern, it may be referred to as an equivalent TSV array of the wafer.
  • Figure 5 shows an example of an equivalent TSV array of a wafer.
  • the black filling pattern corresponds to the concave hole or the dummy pad formed by the concave hole
  • the white filling pattern corresponds to the via hole or the TSV formed by the via hole.
  • the two adjacent patterns may include a pattern corresponding to the concave holes and a pattern of via holes adjacent to the concave holes (for example, in the x-direction).
  • the pattern b and c in the y direction, the pattern e and f in the y direction), the pattern corresponding to the concave hole, and the pattern of another concave hole adjacent to the concave hole for example, the patterns a and b in the x direction, the pattern a in the y direction) and e
  • the pattern corresponding to the via hole and the pattern of another via hole adjacent to the via hole eg patterns c and d in the x-direction, patterns f and g in the y-direction
  • the x direction may be the width direction
  • the y direction may be the length direction.
  • the distances between patterns a and b, between patterns b and c, and between patterns c and d are the same, which are the equivalent TSV arrays of the wafer in the x-direction pitch.
  • the distances between patterns a and e, between patterns e and f, and between patterns f and g are all the same, which are the pitches of the equivalent TSV array of the wafer in the y direction.
  • the pitch of the equivalent TSV array in the x direction and the pitch in the y direction may be the same or different, which is not limited.
  • the black filling pattern corresponds to the concave hole or the dummy pad formed by the concave hole
  • the white filling pattern corresponds to the via hole or the TSV formed by the via hole as an example for description.
  • the number of concave holes may be eight, and the eight concave holes are evenly distributed around the via hole.
  • FIG. 6A is an example of a pattern formed by a via hole on the surface of the substrate layer, where the via hole can form a single TSV.
  • FIG. 6B is an example of the via hole and the added 8 concave holes in FIG. 6A , and the 8 concave holes are evenly distributed around the via hole.
  • the distance between any two adjacent patterns in the length direction is the same, and the distance between any adjacent two patterns in the width direction is the same.
  • the distances between the patterns are the same. That is, the pattern in Figure 6B is the equivalent 3 ⁇ 3 TSV array of the wafer.
  • any adjacent The two patterns have the same distance in the length direction, and any adjacent two patterns have the same distance in the width direction.
  • the number of added recesses may be 15, making the equivalent TSV array of the wafer a 4 ⁇ 4 TSV array, and for another example, the number of added recesses may be 11, so that the wafer has a 4 ⁇ 3 TSV array The equivalent TSV array of .
  • the TSVs corresponding to the multiple vias are part of the TSV array, for example, the TSVs remaining after removing one or a part of TSVs in the TSV array.
  • the concave hole may be located at a position corresponding to one or a part of the removed TSVs, so that the concave hole and the via hole together form a complete array, so that the wafer has an equivalent TSV array.
  • FIG. 7A shows an example of a pattern of formation of a plurality of vias on the surface of the substrate layer.
  • the via holes in the dotted boxes 701 and 702 are respectively 4 via holes less than the complete TSV array. That is to say, the TSVs corresponding to the via holes are the TSVs remaining after removing 4 TSVs from the dashed box 701 in the TSV array and the remaining TSVs after removing 4 TSVs from the dashed box 702 .
  • FIG. 7B is an example of the multiple via holes and the added 8 concave holes in FIG.
  • FIG. 7A wherein the four concave holes are located at the positions corresponding to the four TSVs removed from the dashed frame 701 , and the 4 concave holes are located in the dotted line frame at the positions corresponding to the 4 TSVs removed in 702.
  • FIG. 7B that is, in the pattern corresponding to the concave hole and the pattern corresponding to the via hole, the distance between any two adjacent patterns in the length direction is the same, and the distance between any two adjacent patterns in the width direction is the same. the same distance. That is, the pattern in FIG. 7B is the equivalent TSV array of the wafer.
  • the plurality of via holes include a first portion of via holes and a second portion of via holes, wherein the first portion of via holes is conductive on the surface of the substrate layer
  • the first portion of via holes is conductive on the surface of the substrate layer
  • in the second partial via hole there is a first distance between any two adjacent via holes in the first direction.
  • the first distance is an integer multiple of the second distance
  • the concave hole is located between two adjacent through holes in the first direction in the first partial through hole.
  • the first direction is the length direction or the width direction.
  • the pattern formed by the via hole on the lower surface of the substrate layer includes a first partial pattern and a second partial pattern
  • the first distance between any two adjacent patterns in the first direction in the first partial pattern is
  • the pattern corresponding to the concave hole may be located in two adjacent patterns in the first direction in the first partial pattern so that after the concave hole is added, the distance between two adjacent patterns in the first direction in the pattern corresponding to the first partial pattern and the concave hole is also the second distance.
  • the patterns formed on the lower surface of the entire substrate layer have the same distance between any two adjacent patterns in the first direction, that is, the second distance.
  • FIG. 8A shows another example of a pattern formed by a plurality of vias on the surface of the substrate layer.
  • the via holes in the dotted frame 802 are the first partial vias
  • the corresponding pattern is the first partial pattern
  • the vias in the dotted frame 801 are the second partial vias
  • the corresponding pattern is the first partial via Two-part pattern.
  • the distance between two adjacent patterns (or vias) in the x-direction in the first partial pattern (or the first partial via) is 10 ⁇ m
  • the distance between two adjacent patterns (or vias) in the y-direction is 10 ⁇ m.
  • the distance between the through holes) is 20 ⁇ m, that is, the TSV array corresponding to the first part of the pattern (or the first part of the through hole) is an array of 10 ⁇ m*20 ⁇ m.
  • the distance between two adjacent patterns (or vias) in the x-direction is 10 ⁇ m
  • the distance between the two adjacent patterns (or vias) in the y-direction is 10 ⁇ m.
  • the distance between them is also 10 ⁇ m, that is, the TSV array corresponding to the second part of the pattern (or the second part of the via hole) is an array of 10 ⁇ m*10 ⁇ m.
  • the distance between two adjacent patterns (or via holes) in the second partial pattern (or the second partial via hole) is the same as the distance between the first partial pattern (or the first partial via hole) in the first partial pattern (or the first partial via hole). 2 times the distance between two adjacent patterns (or vias).
  • FIG. 8B is an example of the plurality of vias and the added recess in FIG. 8A .
  • a row of concave holes is added between two adjacent rows of via holes in the y-direction in the dashed frame 802 , so that the distance between adjacent patterns in the y-direction in the dashed frame 802 is 10 ⁇ m.
  • the distance between adjacent concave holes in the x-direction of the added concave holes is 10 ⁇ m.
  • the TSV array corresponding to the pattern corresponding to the concave hole and the pattern corresponding to the via hole is an array of 10 ⁇ m*10 ⁇ m.
  • the pattern in FIG. 8B is the equivalent TSV array of the wafer, that is, a TSV array of 10 ⁇ m*10 ⁇ m.
  • FIG. 9A shows another example of a pattern of formation of a plurality of vias on the surface of the substrate layer.
  • the via holes in the dotted frame 902 are the first partial vias
  • the corresponding pattern is the first partial pattern
  • the vias in the dotted frame 901 are the second partial vias
  • the corresponding pattern is The second part of the pattern.
  • the distance between two adjacent patterns (or vias) in the x-direction in the first partial pattern (or the first partial via) is 20 ⁇ m
  • the distance between two adjacent patterns (or vias) in the y-direction is 20 ⁇ m.
  • the distance between the through holes) is 20 ⁇ m, that is, the TSV array corresponding to the first part of the pattern (or the first part of the through hole) is an array of 20 ⁇ m*20 ⁇ m.
  • the distance between two adjacent patterns (or vias) in the x-direction is 10 ⁇ m
  • the distance between the two adjacent patterns (or vias) in the y-direction is 10 ⁇ m.
  • the distance between them is also 10 ⁇ m, that is, the TSV array corresponding to the second part of the pattern (or the second part of the via hole) is an array of 10 ⁇ m*10 ⁇ m.
  • the distance between two adjacent patterns (or via holes) in the second partial pattern (or the second partial via hole) is the same as the first partial pattern (or the first partial via hole). 2 times the distance between two adjacent patterns (or vias) in vias.
  • FIG. 9B is an example of the plurality of vias and the added recesses in FIG. 9A .
  • concave holes are added between two adjacent rows of via holes in the x-direction and the y-direction in the dashed frame 902, so that the distance between the adjacent patterns in the y-direction in the dashed frame 902 is 10 ⁇ m, x The distance between adjacent patterns in the direction was 10 ⁇ m.
  • the TSV array corresponding to the pattern corresponding to the concave hole and the pattern corresponding to the via hole is an array of 10 ⁇ m*10 ⁇ m.
  • the pattern in FIG. 9B is the equivalent TSV array of the wafer, that is, a TSV array of 10 ⁇ m*10 ⁇ m.
  • FIG. 10A shows another example of a pattern of formation of a plurality of vias on the surface of the substrate layer.
  • the via holes in the dotted frame 1002 are the first partial via holes
  • the corresponding pattern is the first partial pattern
  • the via holes in the dotted frame 1001 are the second partial via holes
  • the corresponding pattern is The second part of the pattern.
  • the distance between two adjacent patterns (or vias) in the x-direction in the first partial pattern (or the first partial via) is 20 ⁇ m
  • the distance between two adjacent patterns (or vias) in the y-direction is 20 ⁇ m.
  • the distance between the through holes) is 40 ⁇ m, that is, the TSV array corresponding to the first part of the pattern (or the first part of the through hole) is an array of 20 ⁇ m*40 ⁇ m.
  • the distance between two adjacent patterns (or via hole) in the x direction is 15 ⁇ m
  • the distance between the two adjacent patterns (or via hole) in the y direction is 15 ⁇ m.
  • the distance between them is also 15 ⁇ m, that is, the TSV array corresponding to the second part of the pattern (or the second part of the via hole) is an array of 15 ⁇ m*15 ⁇ m.
  • the distance between two adjacent patterns (or vias) in the second partial pattern (or the second partial via) is greater than the distance between the first partial pattern (or the first partial via)
  • the distance between two adjacent patterns (or via holes) in the through hole is not an integer multiple of the two adjacent patterns (or via holes) in the first partial pattern (or the first partial via hole).
  • FIG. 10B is an example of the plurality of vias and the added recess in FIG. 10A .
  • a row of concave holes is added between two adjacent rows of via holes in the y-direction in the dashed frame 1002 , so that the distance between adjacent patterns in the y-direction in the dashed frame 1002 is 20 ⁇ m.
  • the distance between adjacent concave holes in the x-direction of the added concave holes is 20 ⁇ m.
  • the equivalent TSV array corresponding to the pattern corresponding to the concave hole and the pattern corresponding to the via hole in the dotted frame 1002 is an array of 20 ⁇ m*20 ⁇ m.
  • the TSV array corresponding to the dotted frame 1002 corresponds to the dotted frame 1001
  • the pitches of the TSV arrays are similar, so that the pattern formed by the concave holes and the via holes in the dotted frame 1002 and the pattern formed by the concave holes and the via holes in the dotted frame 1001 on the surface of the substrate layer can look as regular or uniform as possible.
  • the equivalent TSV array corresponding to the pattern corresponding to the concave hole and the pattern corresponding to the via hole in the dotted frame 1002 is used as an example for illustration, but the application is not limited to this.
  • the equivalent TSV array may also be an array of 10 ⁇ m*20 ⁇ m, or others, which are not limited.
  • the fifth possible situation when the pattern corresponding to the via hole is irregular, that is, when the TSV corresponding to the via hole is not a TSV array, for example, when the distance between adjacent via holes in the width direction or the length direction is not the same, you can
  • the concave holes are added between the via holes, so that the pattern formed by the concave holes and the via holes on the surface of the substrate layer looks as regular or uniform as possible.
  • a concave hole can still be added between the via holes.
  • a concave hole can be added, so that the equivalent TSV array corresponding to the pattern formed by the concave hole and the via hole is the TSV array verified by the vendor.
  • the TSV array corresponding to the via hole is a TSV array with a larger pitch, since the via hole is relatively sparse, the metal distribution will be uneven when the metal is subsequently ground.
  • the equivalent TSV array pitch of the wafer is smaller, which can help to make the metal distribution more uniform during subsequent grinding, thereby reducing the difficulty of CMP.
  • FIG. 11A and FIG. 11B show an example of adding a concave hole when the TSV corresponding to the via hole is a TSV array.
  • FIG. 11A is an example of the TSV array corresponding to the via hole.
  • a concave hole having the same shape as the via hole may be added between the via holes to obtain the pattern formed by the concave hole and the via hole as shown in FIG. 11B .
  • FIG. 12A and 12B show another example of adding a concave hole when the TSV corresponding to the via hole is a TSV array.
  • FIG. 12A is an example of the TSV array corresponding to the via hole.
  • diamond-shaped or rectangular concave holes may be added between the via holes to obtain the pattern formed by the concave holes and the via holes as shown in FIG. 12B .
  • FIGS. 11B and 12B an example is described by adding a concave hole at the center of four adjacent via holes capable of forming a rectangular shape, but the embodiment of the present application is not limited to this.
  • the concave holes may also be located between adjacent via holes in the width direction or the length direction, or other positions.
  • step 120 may be performed before step 130, or step 120 may be performed after step 130, or step 120 and step 130 may be performed simultaneously.
  • Step 140 depositing metal on the surface of the second side of the substrate layer, in the via hole and in the recessed hole. In this way, the metal within the vias can form via pillars that connect to the metal layer.
  • metal 08 may be deposited on the second surface 012 , the via holes 05 and 06 , and the concave hole 07 of the substrate layer 01 (ie, the shaded part in the figure).
  • the metal in the via holes 05 and 06 can respectively form the via post, the concave hole 07 is also filled with metal, and a metal thin film layer is formed on the second surface 012 .
  • the metal thin film layer may include Cu metal, or may also include other metals, such as Ag, Au, etc., without limitation.
  • a liner layer, a barrier layer and a seed layer may be sequentially formed on the surface of the second side of the substrate layer, in the via hole and in the concave hole, and then through an electroplating process Metal is deposited on the seed layer to achieve metal deposition on the surface of the second side of the substrate layer, within the vias, and within the recesses.
  • FIG. 13 shows an example of a side view of a wafer, in which a liner layer, a barrier layer, a seed layer and a Metal.
  • the above-mentioned liner layer can improve the flatness and stress buffer of the etched surface.
  • the liner layer also functions as a barrier layer.
  • the barrier layers described above can be used to prevent metal diffusion, eg, into Si or SiO 2 , to improve device performance.
  • the above-mentioned seed layer is used to conduct electricity so as to deposit the metal by means of electroplating.
  • the liner, the barrier layer or the seed layer may be prepared by processes such as chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (ALD), etc., which are not limited in this application.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the inner liner may be SiO2
  • the barrier layer may include Ta/N, or Ta, which is not limited in this application.
  • the metal thin film layer may include Cu
  • the seed layer may include Cu, which is not limited in the present application.
  • Step 150 grinding the metal to remove the metal on the surface of the second side of the substrate layer except for the via hole and the concave hole.
  • the above-mentioned grinding of the metal may start grinding of the metal deposited from the second side of the substrate layer.
  • the second side of the substrate layer may still continue to be ground, which is not limited in this application.
  • FIG. 2E an example of a side view of the wafer corresponding to step 150 is shown.
  • grinding can be performed from the metal on the second surface 012 of the substrate layer 01 to remove the via holes 05 and 06 and the concave holes on the second surface 012 of the substrate layer.
  • grinding may be stopped when the second surface 012 of the substrate layer 01 is reached.
  • the grinding may continue along the second side of the substrate layer 01 for a period of time and then stop. At this time, the thickness of the substrate layer 01 is reduced by grinding, and the depths of the via holes 05 and 06 and the recessed hole 07 are correspondingly reduced. As a possible situation, as shown in FIG. 14 , after a period of grinding, the depth of the concave hole 07 will be reduced to 0, that is, the area corresponding to the concave hole 07 on the substrate layer 01 and the second side of the substrate layer 01 are newly formed surface is flush. It can be understood that during the grinding process of the substrate layer 01 , the heights of the metal pillars in the via holes 05 and 06 are always flush with the newly formed surface of the second side of the substrate layer 01 .
  • a liner layer, a barrier layer, a seed layer and a metal are sequentially formed on the surface of the second side of the substrate layer, in the via hole and in the concave hole (that is, corresponding to the one shown in FIG. 13 ) wafer).
  • the grinding can be stopped when the grinding reaches the liner layer.
  • the heights of the via holes 05 and 06 and the metal pillars in the recessed hole 07 are flush with the liner layer.
  • the grinding when grinding starts from the metal on the second surface 012 of the substrate layer 01 , the grinding can be stopped when the grinding reaches the second surface 012 of the substrate layer 01 . At this time, the heights of the via holes 05 and 06 and the metal pillars in the concave hole 07 are flush with the second surface 012 of the substrate layer 01 .
  • the substrate layer 01 may continue to be ground when the second surface 012 of the substrate layer 01 is ground. Grind. At this time, the thickness of the substrate layer 01 is reduced by grinding, and the depths of the via holes 05 and 06 and the recessed hole 07 are correspondingly reduced.
  • the substrate layer 01 when grinding to the second surface 012 of the substrate layer 01 , the substrate layer 01 is continued to be ground until no metal remains in the via hole 07 .
  • the concave hole 07 may include a liner layer, a barrier layer and a seed layer.
  • the heights of the metal pillars in the via holes 05 and 06 are always flush with the newly formed surface of the second side of the substrate layer 01 .
  • step 150 there may be metal residues in the concave holes during the grinding process in step 150 , and after the grinding in step 150 is completed, there may be no metal residues in the concave holes, for example, corresponding to the situation in FIG. 15D .
  • step 150 there may be metal residues in the concave holes during the grinding process in step 150 , and after the grinding in step 150 is completed, there may be no concave holes on the substrate layer 01 , for example, corresponding to the situation in FIG. 14 .
  • the polishing may be chemical mechanical polishing (ie, CMP) or physical polishing, which is not limited in this embodiment of the present application.
  • a standard processing process may be used to perform step 150, for example, annealing (anneal) processing may be performed before CMP, or multiple annealing and CMP processing may be performed, such as anneal-CMP-anneal-CMP, etc. , which is not limited in this application.
  • annealing anneal
  • CMP annealing-CMP-anneal-CMP
  • a subsequent processing flow such as a redistributed layer (redistributed layer, RDL), etc., may be performed, which is not limited in this application.
  • RDL redistributed layer
  • concave holes and via holes for forming TSVs can be formed from one side of the substrate layer, and the substrate layer is opposite to the substrate layer on the side of the substrate layer.
  • the metal is deposited on the surface, vias and concave holes, so that when the metal on the surface of the substrate layer is ground, the setting of the concave holes can add metal to the places where there are no via holes on the substrate layer, which is helpful for the grinding process.
  • the metal is distributed as evenly as possible, helping to improve the consistency and reliability of the grinding process.
  • the TSV corresponding to the via hole may not be a TSV array, or a TSV array verified by a vendor.
  • the TSV of the wafer can be equivalent to a TSV array, or a vendor-verified TSV array in the subsequent grinding process. Therefore, compared with the TSV fabrication solution without the formation of concave holes, the embodiments of the present application can help to make the distribution of metal more uniform in the subsequent grinding process, thereby reducing the complexity of grinding.
  • the present application can flexibly design a TSV pattern and increase the process window according to product needs.
  • Embodiments of the present application further provide a TSV structure, including a substrate layer, a dielectric layer, a metal layer, a via hole and a concave hole, wherein the metal layer is wrapped in the dielectric layer, and the dielectric layer and The metal layer is located on the first side of the substrate layer, the via hole penetrates the substrate layer from the second side of the substrate layer, and stops on the metal layer, and the concave hole extends from the lining layer. A second side of the bottom layer is formed, and metal is deposited in the via hole and the recessed hole.
  • the TSV structure can be, for example, the structures shown in the above-mentioned FIGS. 2E , 15A, 15B, 15C, and 15D.
  • the substrate layer, the dielectric layer, the metal layer, the via hole and the concave hole reference may be made to the above description, and details are not repeated here.
  • the concave holes may be located on the lower surface of the substrate layer.
  • the metal in the recessed holes can help improve the adhesion of the lower surface of the substrate layer.
  • the metal in the recessed holes can help to improve the thermal conductivity of the substrate layer.
  • the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, rather than the implementation of the embodiments of the present application.
  • the process constitutes any qualification.

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Abstract

本申请提供一种硅通孔结构的制备方法和硅通孔结构。该制备方法包括：提供晶圆，该晶圆包括衬底层、介质层和金属层；从衬底层的第二侧形成贯穿衬底层的导通孔，该导通孔停止在金属层上；从衬底层的第二侧形成凹孔；在衬底层的第二侧的表面、导通孔内和凹孔内沉积金属；对金属进行研磨，以去除衬底层的第二侧的表面上的除导通孔和凹孔之外的区域上的金属。本申请中凹孔的设置能够使得在衬底层上没有导通孔的地方增加金属，有助于在研磨过程中金属尽可能地均匀分布，从而有助于提高研磨工艺的一致性和可靠性。另外，本申请中导通孔对应的TSV可以不是TSV array，因而够根据产品需要，灵活地设计TSV图案，增大工艺窗口。

Description

硅通孔结构的制备方法和硅通孔结构 技术领域
本申请涉及芯片封装技术领域，并且更具体的，涉及一种硅通孔结构的制备方法和硅通孔结构。
背景技术
近年来，随着电子设备的小型化、便携化的发展趋势，芯片封装技术逐渐向成熟的三维(3dimensional，3D)堆叠方式发展。通过堆叠的方式，能够实现芯片封装面积最小，从而降低物料构造(build of material，BOM)成本。堆叠封装技术可应用于微系统集成，是继片上系统(system-on-a-chip，SoC)、多芯片模块(multi-chip module，MCM)之后发展起来的封装制造技术。
传统的二维(2dimensional，2D)芯片将芯片中各模块都放在平面层，而3D芯片允许对晶粒(die，或芯片(chip))进行多层堆叠，并可以通过硅通孔(through silicon via，TSV)来实现多个die在垂直方向的信号连接，因此TSV技术成为3D芯片堆叠技术的关键。随着TSV技术的不断进步，芯片在3D方向堆叠的密度增大，外形尺寸变小，将大大改善芯片速度，降低芯片功耗。
由于TSV技术工艺相对较为复杂，因此对TSV设计有较多的约束，例如只能够采用验证过的具有固定pitch的TSV阵列(array)。因此，亟需一种灵活的TSV结构的制备方法。
发明内容
本申请提供一种硅通孔结构的制备方法和硅通孔结构，能够灵活地进行硅通孔结构的制备。
第一方面，提供了一种硅通孔结构的制备方法，包括以下步骤：提供晶圆，所述晶圆包括衬底层、介质层和金属层，其中，所述金属层包裹在所述介质层中，所述介质层和所述金属层位于所述衬底层的第一侧；从所述衬底层的第二侧形成贯穿所述衬底层的导通孔，所述导通孔停止在所述金属层上；从所述衬底层的第二侧形成凹孔；在所述衬底层的第二侧的表面、所述导通孔内和所述凹孔内沉积金属；对所述金属进行研磨，以去除所述衬底层的第二侧的表面上的除所述导通孔和所述凹孔之外的区域上的金属。
因此，本申请实施例中，在晶圆上形成硅通孔时，可以从衬底层的一侧形成凹孔和用于形成硅通孔的导通孔，并在衬底层的该侧对衬底层表面、导通孔和凹孔沉积金属，这样在对衬底层表面上的金属进行研磨时，凹孔的设置能够使得在衬底层上没有导通孔的地方增加金属，有助于在研磨过程中金属尽可能地均匀分布，从而有助于提高研磨工艺的一致性和可靠性。
示例性的，在本申请实施例中，导通孔对应的TSV可以不是TSV array，或者不是供应商(vendor)验证过的TSV array。而通过在衬底层上增加凹孔，能够在后续研磨工艺中， 将晶圆的TSV等效为TSV array，或者vendor验证过的TSV array。因此，本申请实施例相比较不形成凹孔的TSV制作方案而言，能够有助于在后续研磨工艺过程中金属的分布更加均匀，从而降低研磨的复杂度。进一步的，由于本申请中导通孔对应的TSV可以不是TSV array或不是vendor验证过的TSV array，因此本申请能够根据产品需要，灵活地设计TSV图案，增大工艺窗口。
作为示例，上述对金属进行研磨，可以为从衬底层第二侧沉积的金属开始研磨。可选的，在研磨至衬底层的第二侧的表面上金属没有剩余时，仍然可以继续对衬底层的第二侧进行研磨，本申请对此不作限定。
结合第一方面，在第一方面的某些实现方式中，在所述研磨结束后所述凹孔中存在金属剩余。这样，能够使得在研磨的过程中，凹孔中始终存在金属剩余，从而有助于研磨过程中金属均匀分布。
在一些可选的实施例中，在研磨过程中凹孔中存在金属剩余，而在研磨结束之后，凹孔内可以没有金属剩余，或者衬底层表面上不存在凹孔，本申请对此不作限定。
在一些可能的实现方式中，为了使得在研磨结束后或者在研磨过程中凹孔中存在金属剩余，可以设置合适的凹孔深度。一方面，凹孔的深度不能太浅，需要保证在研磨过程中或结束后，凹孔中始终存在金属。另一方面，凹孔的深度不能太深，以免影响器件性能，或增加工艺难度。
作为示例，凹孔的深度可以为1微米(μm)至30微米，本申请对此不作限定。
作为一种实现导通孔停止在金属层上的方式，可以通过控制刻蚀时间(或者控制刻蚀时间以及刻蚀速率)，使得在对导通孔的刻蚀工艺结束时，在导通孔内部裸露出金属层。
作为另一种实现导通孔停止在金属层上的方式，晶圆中可以包括刻蚀阻挡层，该刻蚀阻挡层位于金属层和衬底层之间，例如可以与金属层表面连接。此时，通过控制刻蚀时间(或者控制刻蚀时间以及刻蚀速率)，使得在第一时间段结束后，该导通孔停止在刻蚀阻挡层上。之后，可以对该刻蚀阻挡层进行刻蚀，例如可以通过控制刻蚀时间(或者控制刻蚀时间以及刻蚀速率)，使得在第二时间段结束后，导通孔停止在金属层上。
结合第一方面，在第一方面的某些实现方式中，所述导通孔的数量为至少一个，所述凹孔的数量为至少一个，每个所述导通孔在所述衬底层的第二侧的表面上形成第一图案，每个所述凹孔在所述衬底层的第二侧的表面上形成第二图案，其中，在所述第二侧的表面上至少一个所述第一图案和至少一个所述第二图案中在宽度方向上任意相邻的两个图案的距离相同，和/或在长度方向上任意相邻的两个图案的距离相同。
在一些可选的实施例中，可以将上述至少一个第一图案对应的TSV(即导通孔对应的TSV)和至少一个第二图案对应的dummy pad(即凹孔对应的dummy pad)一起等效为在进行TSV结构的制备过程构造的TSV array，即该至少一个第一图案对应的TSV和至少一个第二图案对应的dummy pad一起可以称为晶圆的等效TSV array。
因此，通过使得在衬底层的第二侧的表面上导通孔形成的至少一个第一图案和凹孔形成的至少一个第二图案中，宽度方向和/或长度方向上任意相邻的两个图案的距离相同，能够有助于导通孔和凹孔均匀分布在衬底层的表面，进而有助于使得晶圆具有等效TSV array，从而有助于在后续的研磨过程中使得金属均匀分布。
由于凹孔设置在导通孔之间或周围，因此上述任意相邻的两个图案可以包括凹孔对应的图案和与该凹孔相邻的导通孔的图案、凹孔对应的图案和与该凹孔相邻的另一个凹孔的 图案、导通孔对应的图案和与该导通孔相邻的另一个导通孔的图案。
结合第一方面，在第一方面的某些实现方式中，所述导通孔的数量为1个，所述凹孔的数量为8个，且8个所述凹孔均匀分布在所述导通孔四周。这样，在8个凹孔对应的图案与该1个导通孔对应的图案中，在长度方向上任意相邻的两个图案之间的距离相同，且在宽度方向上任意相邻的两个图案之间的距离相同，即使得晶圆具有3×3的等效TSV array。
在一些可选的实施例中，还可以在上述1个导通孔周围增加其他数量凹孔，这些凹孔在衬底层的表面形成的图案与该导通孔形成的图案中，任意相邻的两个图案在长度方向上距离相同，且任意相邻的两个图案在宽度方向上距离相同。例如，增加的凹孔的数量可以为15个，使得晶圆的等效TSV array为4×4的TSV array，又例如，增加的凹孔的数量可以为11个，使得晶圆具有4×3的等效TSV array。
结合第一方面，在第一方面的某些实现方式中，所述导通孔的数量为多个，多个所述导通孔包括第一部分导通孔和第二部分导通孔，其中，在所述衬底层的第二侧的表面上所述第一部分导通孔中在第一方向上任意相邻的两个导通孔之间具有第一距离，所述第二部分导通孔中在所述第一方向上任意相邻的两个导通孔之间具有第二距离，且所述第一距离是所述第二距离的整数倍，则所述凹孔位于所述第一部分导通孔中的所述第一方向上的相邻的两个导通孔之间，其中，所述第一方向为长度方向或宽度方向。
这样，在凹孔对应的图案与导通孔对应的图案中，凹孔对应的图案可以位于第一部分图案中第一方向上的相邻两个图案之间，使得在增加了凹孔之后，在第一部分图案与凹孔对应的图案中在该第一方向上相邻两个图案之间的距离也为第二距离。这样整个衬底层下表面上形成的图案在第一方向上任意相邻的两个图案之间都具有相同的距离，即第二距离。因此，本申请实施例能够有助于导通孔和凹孔均匀分布在衬底层的表面，进而有助于使得晶圆具有等效TSV array，从而有助于在后续的研磨过程中使得金属均匀分布。
在一些可选的实施例中，当在衬底层的表面上第一部分导通孔中在第一方向上任意相邻的两个导通孔之间的第一距离大于第二部分导通孔中在该第一方向上任意相邻的两个导通孔之间的第二距离，但该第一距离不是第二距离的整数倍时，仍然可以将至少一个凹孔设置在所述第一部分导通孔之间，使得衬底层的表面上凹孔和导通孔形成的图案看起来尽可能规则或均匀一些，从而能够有助于导通孔和凹孔均匀分布在衬底层的表面，有助于在后续的研磨过程中使得金属均匀分布。
在一些可选的实施例中，当导通孔对应的图案不规则(即导通孔对应的TSV不是TSV array)时，例如在宽度方向或长度方向上相邻导通孔之间距离不相同时，可以在导通孔之间增加凹孔，使得衬底层的表面上凹孔和导通孔形成的图案看起来尽可能规则或均匀一些，从而能够有助于导通孔和凹孔均匀分布在衬底层的表面，有助于在后续的研磨过程中使得金属均匀分布。
在一些可选的实施例中，在导通孔对应的TSV为TSV array时，仍然可以在导通孔之间的增加凹孔。例如，当导通孔对应的TSV array并不是vendor验证过的TSV array时，可以通过增加凹孔，使得凹孔和导通孔形成的图案对应的等效TSV array为经vendor验证过的TSV array。又例如，当导通孔对应的TSV array为pitch较大的TSV array时，由于导通孔比较稀疏，会导致后续对金属进行研磨时，金属分布不均匀。此时通过增加凹孔，使得晶圆的等效TSV array pitch较小，从而能够有助于在后续研磨时，金属分布的更加均 匀。
结合第一方面，在第一方面的某些实现方式中，在所述衬底层的第二侧的表面上凹孔的形状(即凹孔的俯视图)的为圆形、矩形或菱形。
在一些实施例中，在所述衬底层的第二侧的表面上凹孔的形状可以和导通孔的形状(即导通孔的俯视图)相同或相近，例如都为直径相同或相近的圆形，本申请对此不作限定。
或者，在另一些实施例中，在衬底层的第二侧的表面上凹孔形成的图案可以和导通孔形成的图案具有不同的形状，或尺寸，例如导通孔形成的图案为圆形，而凹孔形成的图案为菱形或长方形等，本申请对此不作限定。
结合第一方面，在第一方面的某些实现方式中，所述在所述衬底层的第二侧的表面、所述导通孔内和所述凹孔内沉积金属，可以包括在所述衬底层的第二侧的表面、所述导通孔内和所述凹孔内依次形成内衬(liner)层、阻挡层和种子层，然后通过电镀工艺在所述种子层上沉积所述金属。
其中，上述liner层可以提高刻蚀表面的平整度以及应力缓冲，也具有阻挡作用。上述阻挡层可以用于阻止金属扩散，例如阻止金属扩散到Si或SiO 2中，以提高器件性能。上述种子层用于导电，以便通过电镀的方式来生成金属薄膜层。
在一些可选的实施例中，在对金属进行研磨时，可以在研磨至liner层时停止，或者在研磨至衬底层时停止，或者在在研磨至衬底层时继续研磨且在研磨结束后凹孔内还有金属剩余，或者在研磨至凹孔内的金属没有剩余时停止，本申请对此不作限定。
结合第一方面，在第一方面的某些实现方式中，所述阻挡层包括Ta或TaN。
结合第一方面，在第一方面的某些实现方式中，所述种子层包括Cu。
结合第一方面，在第一方面的某些实现方式中，所述金属薄膜层包括Cu。
第二方面，提供了一种硅通孔结构，包括衬底层、介质层、金属层、导通孔和凹孔，其中，所述金属层包裹在所述介质层中，所述介质层和所述金属层位于所述衬底层的第一侧，所述导通孔从所述衬底层的第二侧贯穿所述衬底层，且停止在所述金属层上，所述凹孔从所衬底层的第二侧形成，所述导通孔和所述凹孔内沉积有金属。
结合第二方面，在第二方面的某些实现方式中，所述导通孔的数量为至少一个，所述凹孔的数量为至少一个，每个所述导通孔在所述衬底层的第二侧的表面上形成第一图案，每个所述凹孔在所述衬底层的第二侧的表面上形成第二图案，其中，在所述第二侧的表面上至少一个所述第一图案和至少一个所述第二图案中任意相邻的两个图案在宽度方向上距离相同，和/或在长度方向上距离相同。
结合第二方面，在第二方面的某些实现方式中，所述导通孔的数量为1个，所述凹孔的数量为8个，且8个所述凹孔均匀分布在所述导通孔四周。
结合第二方面，在第二方面的某些实现方式中，所述导通孔的数量为多个，多个所述导通孔包括第一部分导通孔和第二部分导通孔，其中，在所述衬底层的第二侧的表面上所述第一部分导通孔中任意相邻的两个导通孔之间在第一方向上具有第一距离，所述第二部分导通孔中任意相邻的两个导通孔在所述第一方向上具有第二距离，且所述第一距离是所述第二距离的整数倍，则所述凹孔位于所述第一部分导通孔中的所述第一方向上的相邻的两个导通孔之间，其中，所述第一方向为长度方向或宽度方向。
结合第二方面，在第二方面的某些实现方式中，在所述衬底层的第二侧的表面上所述 凹孔的形状为圆形、矩形或菱形。
结合第二方面，在第二方面的某些实现方式中，所述凹孔的深度为1微米至30微米。
应理解，本申请的第二方面及对应的实现方式所取得的有益效果可以参见本申请的第一方面及对应的实现方式所取得的有益效果，不再赘述。
附图说明
图1是本申请实施例提供的一种硅通孔结构的制备方法的示意性流程图；
图2A是提供的晶圆的侧视图的一个示例；
图2B是硅通孔结构的制备过程中晶圆的侧视图的一个示例；
图2C是硅通孔结构的制备过程中晶圆的侧视图的另一个示例；
图2D是硅通孔结构的制备过程中晶圆的侧视图的另一个示例；
图2E是本申请中硅通孔结构的侧视图的一个示例；
图3是提供的晶圆的侧视图的一个示例；
图4是硅通孔结构的制备过程中晶圆的侧视图的另一个示例；
图5是晶圆的等效TSV array的一个示例；
图6A是衬底层的表面上一个导通孔形成的图案的示意图；
图6B为在一个导通孔周围增加8个凹孔的一个示意图；
图7A是在衬底层的表面上多个导通孔的形成的图案的一个示意图；
图7B是多个导通孔中增加凹孔的一个示意图；
图8A是在衬底层的表面上多个导通孔的形成的图案的另一个示意图；
图8B是多个导通孔中增加凹孔的另一个示意图；
图9A是在衬底层的表面上多个导通孔的形成的图案的另一个示意图；
图9B是多个导通孔中增加凹孔的另一个示意图；
图10A是在衬底层的表面上多个导通孔的形成的图案的另一个示意图；
图10B是多个导通孔中增加凹孔的另一个示意图；
图11A是在衬底层的表面上多个导通孔的形成的图案的另一个示意图；
图11B是多个导通孔中增加凹孔的另一个示意图；
图12A是在衬底层的表面上多个导通孔的形成的图案的另一个示意图；
图12B是多个导通孔中增加凹孔的另一个示意图；
图13是硅通孔结构的制备过程中晶圆的侧视图的另一个示例；
图14是本申请中硅通孔结构的侧视图的一个示例；
图15A是本申请中硅通孔结构的侧视图的另一个示例；
图15B是本申请中硅通孔结构的侧视图的另一个示例；
图15C是本申请中硅通孔结构的侧视图的另一个示例；
图15D是本申请中硅通孔结构的侧视图的另一个示例。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
图1是本申请实施例提供的一种硅通孔结构的制备方法100的示意性流程图，图2A至图2E是方法100对应的工艺流程图的一个具体示例。下面，结合图2A至图2E所示的 工艺流程，描述图1中所示的硅通孔结构的制备方法100。如图1所示，方法100包括步骤110至步骤150。
步骤110，提供晶圆，所述晶圆包括衬底层、介质层和金属层，其中，所述金属层包裹在所述介质层中，所述介质层和所述金属层位于所述衬底层的第一侧。
参见图2A，示出了步骤110对应的晶圆(wafer)侧视图的一个示例。如图2A所示，晶圆包括衬底层01、介质层02和金属层03，其中金属层03包裹在介质层02中，介质层02和金属层03均位于衬底层01的第一侧，例如衬底层01的第一表面011(即第一侧的表面)之上的部分。
示例性的，本申请中衬底层可以为半导体衬底层，例如硅衬底、锗硅衬底、蓝宝石衬底等，不作限定。
可以理解的是，在晶圆中，还可以包括器件层，器件层可以位于衬底层和金属层之间。示例性的，器件层中可以包括有源区、漏区和阱区等，本申请对此不作限定。图3示出了晶圆的结构的一个示例。如图3所示，器件层04可以位于衬底层01和金属层03(或介质层02)之间，器件层04中可以包括有源区041、漏区042、阱区043和阱区044。
应理解，图3示出了晶圆的一个示例，但这并不对本申请构成限定，本申请涉及的晶圆也可以为除图3之外的具有其他结构的晶圆，这都在本申请的保护范围之内。
另外，在晶圆中还可以包括其他层结构，例如缓冲层、阻挡层等，这些层结构可以位于衬底层的第一侧，例如位于介质层和衬底层之间，本申请对此不作限定。
在步骤110中，还可以对晶圆进行TSV制备的前处理，例如衬底减薄处理(例如从几百μm减薄至几十μm)、研磨处理等，本申请对此不作限定。作为示例，研磨可以为化学机械研磨(chemical mechanical polishing，CMP)，或物理研磨等，不作限定。其中，化学机械研磨还可以称为化学机械抛光，本申请对此不作限定。
步骤120，从所述衬底层的第二侧形成贯穿所述衬底层的导通孔，该导通孔停止在金属层上。其中，导通孔的数量可以为一个，或多个，不作限定。
参见图2B，示出了步骤120对应的晶圆的侧视图的一个示例。如图2B所示，在图2A的基础上，可以在晶圆上从衬底层01的第二侧开始进一步形成导通孔05和06，该导通孔05和06贯穿衬底层01，即连通衬底层01相对的两个表面，比如第一表面011和第二表面012(即第二侧的表面)。继续参见图2B，导通孔05和06最终停止在金属层03上。
应理解，图2B中仅以形成导通孔05和06为例进行描述，本申请并不限于此。例如，在步骤120中还可以只形成一个导通孔，或者可以形成更多导通孔等。
示例性的，本申请中可以通过光刻以及刻蚀等工艺，制备导通孔。其中，刻蚀工艺例如为深反应离子刻蚀(deep reactive ion etching，DRIE)、深等离子刻蚀等，本申请对此不作限定。
作为一种实现导通孔停止在金属层上的方式，可以通过控制刻蚀时间(或者控制刻蚀时间以及刻蚀速率)，使得在对导通孔的刻蚀工艺结束时，在导通孔内部裸露出金属层。
作为另一种实现导通孔停止在金属层上的方式，晶圆中可以包括刻蚀阻挡层，该刻蚀阻挡层位于衬底层和金属层之间，例如可以与金属层表面(例如图2B中的金属层03的下表面031)连接。此时，通过控制刻蚀时间(或者控制刻蚀时间以及刻蚀速率)，使得在第一时间段结束后，该导通孔停止在刻蚀阻挡层上。图4示出了导通孔停止在刻蚀阻挡层上的一个示例。如图4所示，导通孔05和06停止位于金属层03的下表面031之下的刻 蚀阻挡层032上，此时，在该导通孔05和06内部裸露出该刻蚀阻挡层032。之后，可以对该刻蚀阻挡层032进行刻蚀，例如可以通过控制刻蚀时间(或者控制刻蚀时间以及刻蚀速率)，使得在第二时间段结束后，导通孔05和06停止在金属层03上。此时，在导通孔05和06内部裸露出金属层，即得到图2B所示的结构。
因此，通过设置刻蚀阻挡层，可以有效的控制刻蚀深度，有助于避免刻蚀深度过深或刻蚀深度过浅。作为示例，当刻蚀深度过深时，可能会出现对金属层的完全刻蚀，当刻蚀深度过浅时，可能会出现导通孔内还没有裸露出金属层时就停止了刻蚀。
本申请实施例中，步骤120中生成的导通孔用于形成TSV，因此也可以称为TSV孔，或可称为TSV深孔，本申请对此不作限定。
在通过步骤120形成导通孔之后，在衬底层01的第二侧的表面(即第二表面012)上，导通孔将形成图案，该图案即为导通孔在衬底层01的第二表面012上形成的俯视图。在一些实施例中，可以称导通孔与该导通孔形成的TSV对应，或称导通孔在衬底层的第二侧的表面上形成的图案与该导通孔形成的TSV对应。
本申请实施例中，对导通孔在衬底层的第二侧的表面上形成的图案不作限定，例如，该图案对应的TSV可以是TSV array的一部分，或者是完整的TSV array，或者该图案对应的TSV可以包含至少两部分的具有不同pitch的TSV array，或者该图案对应的TSV可以为单根(isolation)TSV，或者该图案对应的TSV中相邻两个TSV之间的距离不相同，或者该图案对应的TSV形成的TSV array可以是供应商(vendor)验证过的TSV array，也可以不是vendor验证过的TSV array。
其中，TSV array可以包括宽度方向上的至少两个TSV和长度方向上的至少两个TSV，在长度方向上任意相邻的两个TSV之间的距离(该距离可以称为TSV array在长度方向上的pitch)相同，且任意相邻的两个TSV在宽度方向上的距离(该距离可以称为TSV array在宽度方向上的pitch)相同。换句话说，TSV array可以为在宽度方向和长度方向上均具有固定pitch至少两个TSV构成的阵列。示例性的，当TSV array在宽度方向上TSV的个数为m，在长度方向上TSV的个数为n时，可以称该TSV array为m×n的TSV array。其中，m，n分别为正整数。
需要说明的是，TSV array中在宽度方向上的TSV的数量与在长度方向上的TSV的数量相同或不同，任意相邻的两个TSV在长度方向上的距离与任意两个TSV在宽度方向上的距离可以相同或不同，本申请对此不作限定。
需要说明的是，本申请实施例中，形成导通孔的工艺流程可以根据实际情况进行微调，本申请实施例对此不作限定。
步骤130，从所述衬底层的第二侧形成凹孔。其中，凹孔的数量可以为一个，或多个，不作限定。
参见图2C，示出了步骤130对应的晶圆的侧视图的一个示例。如图所示，在图2B的基础上，可以在衬底层01的第二侧(即从第二表面012开始)进一步形成凹孔07。可选的，凹孔07可以不贯穿衬底层01。应理解，图2C中仅以形成凹孔07为例进行描述，本申请并不限于此。例如，还可以形成多个凹孔。
示例性的，本申请中可以通过光刻以及刻蚀等工艺，制备上述凹孔。具体的，光刻以及刻蚀等工艺可以参见上文中的描述，不再赘述。
本申请实施例中，对凹孔的形状不作限定。示例性的，凹孔的形状可以为圆柱、四棱 柱、梯台或其他形状。在一些具体的例子中，凹孔在衬底层的第二侧的表面上形成的图案(即凹孔的俯视图)可以为圆形、矩形、菱形或其他，不作限定。可以理解的是，所选择的凹孔的形状(或凹孔俯视图)应当尽可能使得后续工艺(例如CMP)的处理尽可能方便的进行，或具有较低工艺风险，例如具有一致性的平整度、粗糙度，无金属残留等。
需要说明的是，在一些实施例中，在衬底层的第二侧的表面上凹孔形成的图案可以和导通孔形成的图案相同或相近，例如都为直径相同或相近的圆形，本申请对此不作限定。
或者，在另一些实施例中，在衬底层的第二侧的表面上凹孔形成的图案可以和导通孔形成的图案具有不同的形状，或尺寸，例如导通孔形成的图案为圆形，而凹孔形成的图案为菱形或长方形等，本申请对此不作限定。
本申请实施例对凹孔的深度不作限定。示例性的，凹孔的深度可以为1微米(μm)至30微米，例如可以为2μm。需要说明的是，凹孔的设置不需要太深，以免影响器件性能，或增加工艺难度。
本申请实施例中，该凹孔可以用于形成虚假电极(dummy pad)该凹孔也可以称为dummy孔。相应的，凹孔的位置即对应于dummy pad的位置(或pad的位置)。
一些实施例中，在通过步骤120和步骤130形成导通孔和凹孔之后，在衬底层的第二侧的表面上，凹孔形成的图案可以位于导通孔形成的图案之间或周围。此时，每个导通孔孔在衬底层的第二侧的表面形成第一图案，每个凹通孔在衬底层的第二侧的表面形成第二图案。也就是说，至少一个导通孔可以形成至少一个第一图案，至少一个凹孔可以形成至少一个第二图案。
在一些可选的实施例中，上述至少一个第一图案和至少一个第二图案中任意相邻的两个图案在宽度方向上距离相同，和/或在长度方向上距离相同。此时，可以将上述至少一个第一图案对应的TSV和至少一个第二图案对应的dummy pad一起等效为在进行TSV结构的制备过程构造的TSV array，即该至少一个第一图案对应的TSV和至少一个第二图案对应的dummy pad一起可以称为晶圆的等效TSV array。
图5示出了晶圆的等效TSV array的一个示例。其中，黑色填充图案对应凹孔或凹孔形成的dummy pad，白色填充图案对应导通孔或导通孔形成的TSV。如图5所示，由于凹孔设置在导通孔之间或周围，因此该任意相邻的两个图案可以包括凹孔对应的图案和与该凹孔相邻的导通孔的图案(例如x方向上的图案b和c，y方向上的图案e和f)、凹孔对应的图案和与该凹孔相邻的另一个凹孔的图案(例如x方向上的图案a和b，y方向上的图案a和e)、导通孔对应的图案和与该导通孔相邻的另一个导通孔的图案(例如x方向上的图案c和d，y方向上的图案f和g)三种可能的情况。其中，x方向可以为宽度方向，y方向可以为长度方向。
继续参见图5，在x方向上，图案a和b之间，图案b和c之间，以及图案c和d之间的距离均相同，均为晶圆的等效TSV array在x方向上的pitch。在y方向上，图案a和e之间，图案e和f之间，以及图案f和g之间的距离均相同，均为晶圆的等效TSV array在y方向上的pitch。其中，该等效TSV array在x方向上的pitch与y方向上的pitch可以相同或不同，不作限定。
下面结合附图，对衬底层的第二侧的表面上凹孔的位置和导通孔的位置的六种情况进行说明。在以下附图中，以黑色填充图案对应凹孔或凹孔形成的dummy pad，白色填充图案对应导通孔或导通孔形成的TSV为例进行描述。
第一种可能的情况，当导通孔的数量为1个时，凹孔的数量可以为8个，且8个该凹孔均匀分布在该导通孔的四周。
图6A为衬底层的表面上一个导通孔形成的图案的示例，此时该导通孔可以形成单根TSV。图6B为图6A中的该导通孔和增加的8个凹孔的一个示例，该8个凹孔均匀地分布在该导通孔的四周。在图6B，即该8个凹孔对应的图案与该导通孔对应的图案中，在长度方向上任意相邻的两个图案之间的距离相同，且在宽度方向上任意相邻的两个图案之间的距离相同。也就是说，图6B中的图案即为晶圆的3×3的等效TSV array。
在一些可选的实施例中，还可以在上述1个导通孔周围增加其他数量凹孔，这些凹孔在衬底层的表面形成的图案与该导通孔形成的图案中，任意相邻的两个图案在长度方向上距离相同，且任意相邻的两个图案在宽度方向上距离相同。例如，增加的凹孔的数量可以为15个，使得晶圆的等效TSV array为4×4的TSV array，又例如，增加的凹孔的数量可以为11个，使得晶圆具有4×3的等效TSV array。
第二种可能的情况，当导通孔的数量为多个时，该多个导通孔对应的TSV为TSV array的一部分，例如为在TSV array中去掉一个或一部分TSV之后剩余的TSV。此时，凹孔可以位于上述一个或一部分去掉的TSV对应的位置，使得凹孔和导通孔一起构成完整的array，进而使得晶圆具有等效TSV array。
图7A示出了在衬底层的表面上多个导通孔的形成的图案的一个示例。如图7A所示，虚线框701和702中导通孔相对完整的TSV array而言，分别少4个导通孔。也就是说，导通孔对应的TSV为在TSV array中的虚线框701中去掉4个TSV，以及虚线框702中去掉4个TSV之后剩余的TSV。图7B为图7A中的多个导通孔和增加的8个凹孔的一个示例，其中4个凹孔位于虚线框701中去掉的4个TSV对应的位置上，4个凹孔位于虚线框702中去掉的4个TSV对应的位置上。在图7B，即凹孔对应的图案与该导通孔对应的图案中，在长度方向上任意相邻的两个图案之间的距离相同，在宽度方向上任意相邻的两个图案之间的距离相同。也就是说，图7B中的图案即为晶圆的等效TSV array。
第三种可能的情况，当导通孔的数量为多个时，该多个导通孔包括第一部分导通孔和第二部分导通孔，其中，在衬底层的表面上第一部分导通孔中在第一方向上任意相邻的两个导通孔之间具有第一距离，第二部分导通孔中在所述第一方向上任意相邻的两个导通孔之间具有第二距离，且该第一距离是第二距离的整数倍，则此时凹孔位于第一部分导通孔中的该第一方向上的相邻的两个导通孔之间。其中，所述第一方向为长度方向或宽度方向。
也就是说，当衬底层的下表面上导通孔形成的图案包括第一部分图案和第二部分图案，且第一部分图案中在第一方向上任意相邻两个图案之间的第一距离是第二部分图案中的在该第一方向上任意相邻两个图案之间的第二距离的整数倍时，凹孔对应的图案可以位于第一部分图案中第一方向上的相邻两个图案之间，使得在增加了凹孔之后，在第一部分图案与凹孔对应的图案中在该第一方向上相邻两个图案之间的距离也为第二距离。这样整个衬底层下表面上形成的图案在第一方向上任意相邻的两个图案之间都具有相同的距离，即第二距离。
图8A示出了在衬底层的表面上多个导通孔形成的图案的另一个示例。如图8A所示，其中虚线框802中的导通孔为第一部分导通孔，对应图案为第一部分图案，虚线框801中的导通孔为第二部分导通孔，对应的图案为第二部分图案。作为一个具体的例子，第一部分图案(或第一部分导通孔)中x方向上相邻两个图案(或导通孔)之间的距离为10μm， y方向上相邻两个图案(或导通孔)之间的距离为20μm，即第一部分图案(或第一部分导通孔)对应的TSV array为10μm*20μm的array。第二部分图案(或第二部分导通孔)中x方向上相邻两个图案(或导通孔)之间的距离为10μm，y方向上相邻两个图案(或导通孔)之间的距离也为10μm，即第二部分图案(或第二部分导通孔)对应的TSV array为10μm*10μm的array。此时在y方向上，第二部分图案(或第二部分导通孔)中的相邻两个图案(或导通孔)之间的距离是第一部分图案(或第一部分导通孔)中相邻两个图案(或导通孔)之间的距离的2倍。
图8B为图8A中的多个导通孔和增加的凹孔的一个示例。如图8B所示，在虚线框802中y方向上的相邻的两行导通孔之间分别增加一行凹孔，使得虚线框802中y方向上相邻图案之间的距离为10μm。其中，增加的凹孔在x方向上相邻凹孔之间的距离为10μm。这样，在图8B，即凹孔对应的图案与导通孔对应的图案对应的TSV array为10μm*10μm的array。此时，图8B中的图案即为晶圆的等效TSV array，即10μm*10μm的TSV array。
图9A示出了在衬底层的表面上多个导通孔的形成的图案的另一个示例。如图9A所示，其中虚线框902中的导通孔为第一部分导通孔，对应的图案为第一部分图案，虚线框901中的导通孔为第二部分导通孔，对应的图案为第二部分图案。作为一个具体的例子，第一部分图案(或第一部分导通孔)中x方向上相邻两个图案(或导通孔)之间的距离为20μm，y方向上相邻两个图案(或导通孔)之间的距离为20μm，即第一部分图案(或第一部分导通孔)对应的TSV array为20μm*20μm的array。第二部分图案(或第二部分导通孔)中x方向上相邻两个图案(或导通孔)之间的距离为10μm，y方向上相邻两个图案(或导通孔)之间的距离也为10μm，即第二部分图案(或第二部分导通孔)对应的TSV array为10μm*10μm的array。此时在x方向和y方向上，第二部分图案(或第二部分导通孔)中的相邻两个图案(或导通孔)之间的距离均是第一部分图案(或第一部分导通孔)中相邻两个图案(或导通孔)之间的距离的2倍。
图9B为图9A中的多个导通孔和增加的凹孔的一个示例。如图9B所示，在虚线框902中x方向和y方向上相邻两行导通孔之间分别增加凹孔，使得虚线框902中y方向上相邻图案之间的距离为10μm，x方向上相邻图案之间的距离为10μm。这样，在图9B，即凹孔对应的图案与导通孔对应的图案对应的TSV array为10μm*10μm的array。此时，图9B中的图案即为晶圆的等效TSV array，即10μm*10μm的TSV array。
第四种可能的情况，当在衬底层的表面上第一部分导通孔中在第一方向上任意相邻的两个导通孔之间的第一距离大于第二部分导通孔中在该第一方向上任意相邻的两个导通孔之间的第二距离，但该第一距离不是第二距离的整数倍时，仍然可以将至少一个凹孔设置在所述第一部分导通孔之间，使得衬底层的表面上凹孔和导通孔形成的图案看起来尽可能规则或均匀一些。
图10A示出了在衬底层的表面上多个导通孔的形成的图案的另一个示例。如图10A所示，其中虚线框1002中的导通孔为第一部分导通孔，对应的图案为第一部分图案，虚线框1001中的导通孔为第二部分导通孔，对应的图案为第二部分图案。作为一个具体的例子，第一部分图案(或第一部分导通孔)中x方向上相邻两个图案(或导通孔)之间的距离为20μm，y方向上相邻两个图案(或导通孔)之间的距离为40μm，即第一部分图案(或第一部分导通孔)对应的TSV array为20μm*40μm的array。第二部分图案(或 第二部分导通孔)中x方向上相邻两个图案(或导通孔)之间的距离为15μm，y方向上相邻两个图案(或导通孔)之间的距离也为15μm，即第二部分图案(或第二部分导通孔)对应的TSV array为15μm*15μm的array。此时在x方向和y方向上，第二部分图案(或第二部分导通孔)中的相邻两个图案(或导通孔)之间的距离均大于第一部分图案(或第一部分导通孔)中相邻两个图案(或导通孔)之间的距离，且不是第一部分图案(或第一部分导通孔)中相邻两个图案(或导通孔)的整数倍。
图10B为图10A中的多个导通孔和增加的凹孔的一个示例。如图10B所示，在虚线框1002中y方向上的相邻的两行导通孔之间分别增加一行凹孔，使得虚线框1002中y方向上相邻图案之间的距离为20μm。其中，增加的凹孔在x方向上相邻凹孔之间的距离为20μm。这样，在图10B，虚线框1002中凹孔对应的图案与导通孔对应的图案对应的等效TSV array为20μm*20μm的array，此时虚线框1002对应的TSV array与虚线框1001对应的TSV array的pitch相近，进而能够使得衬底层的表面上虚线框1002中凹孔和导通孔形成的图案与虚线框1001中凹孔和导通孔形成的图案看起来尽可能规则或均匀一些。
需要说明的是，在图10B中，以虚线框1002中凹孔对应的图案与导通孔对应图案对应的等效TSV array为20μm*20μm的array为例进行说明，但是本申请并不限于此。例如，该等效TSV array还可以为10μm*20μm的array，或其他，不作限定。
第五种可能的情况，当导通孔对应的图案不规则，即导通孔对应的TSV不是TSV array时，例如在宽度方向或长度方向上相邻导通孔之间距离不相同时，可以在导通孔之间增加凹孔，使得衬底层的表面上凹孔和导通孔形成的图案看起来尽可能规则或均匀一些。
第六种可能的情况，在导通孔对应的TSV为TSV array时，仍然可以在导通孔之间的增加凹孔。例如，当导通孔对应的TSV array并不是vendor验证过的TSV array时，可以通过增加凹孔，使得凹孔和导通孔形成的图案对应的等效TSV array为经vendor验证过的TSV array。又例如，当导通孔对应的TSV array为pitch较大的TSV array时，由于导通孔比较稀疏，会导致后续对金属进行研磨时，金属分布不均匀。此时通过增加凹孔，使得晶圆的等效TSV array pitch较小，从而能够有助于在后续进行研磨时，金属分布的更加均匀，从而降低CMP难度。
图11A和图11B示出了在导通孔对应的TSV为TSV array的情况下增加凹孔的一个示例。其中，在图11A为导通孔对应的TSV array的一个示例。在图11A中，可以在导通孔之间增加与导通孔具有相同形状的凹孔，得到如图11B所示的凹孔与导通孔形成的图案。
图12A和图12B示出了在导通孔对应的TSV为TSV array的情况下增加凹孔的另一个示例。其中，在图12A为导通孔对应的TSV array的一个示例。在图12A中，可以在导通孔之间增加菱形或矩形的凹孔，得到如图12B所示的凹孔与导通孔形成的图案。
需要说明的是，在图11B和图12B中，以在相邻的4个能够形成矩形的导通孔的中心位置增加凹孔为例进行描述，但是本申请实施例并不限于此。例如，凹孔还可以位于宽度方向或长度方向上的相邻的导通孔之间，或其他位置。
还需要说明的是，本申请实施例对于步骤120和步骤130执行的先后顺序不作限定。例如，步骤120可以在步骤130之前执行，或步骤120可以在步骤130之后执行，或者步骤120和步骤130同时执行。
步骤140，在衬底层的第二侧的表面、导通孔内和凹孔内沉积金属。这样，在导通孔 内的金属可以形成与金属层连接的通孔柱。
参见图2D，示出了步骤140对应的晶圆的侧视图的一个示例。如图2D所示，在图2C的基础上，可以在衬底层01的第二表面012、导通孔05和06、凹孔07上沉积金属08(即图中阴影部分)。此时，在导通孔05和06中的金属可以分别形成通孔柱，凹孔07中也填充了金属，并且在在第二表面012上形成了金属薄膜层。
作为示例，金属薄膜层可以包括Cu金属，或者也可以包括其他金属，例如Ag、Au等，不作限定。
作为一种可能的实现方式，可以在衬底层的第二侧的表面上、导通孔内和凹孔内依次形成内衬(liner)层、阻挡层(barrier)和种子层，然后通过电镀工艺在种子层上沉积金属，以实现在衬底层的第二侧的表面、导通孔内和凹孔内沉积金属。图13示出了晶圆的侧视图的一个示例，其中，衬底层01的第二表面012上、导通孔05和06内、凹孔07内依次形成有liner层、阻挡层、种子层和金属。
其中，上述liner层可以提高刻蚀表面的平整度以及应力缓冲。另外，liner层也具有阻挡层的作用。上述阻挡层可以用于阻止金属扩散，例如阻止金属扩散到Si或SiO 2中，以提高器件性能。上述种子层用于导电，以便通过电镀的方式来沉积金属。
作为示例，可以通过化学气相沉积(chemical vapour deposition，CVD)、原子层沉积(atomic layer deposition,ALD)等工艺制备内衬、阻挡层或种子层，本申请对此不作限定。
作为示例，内衬可以为SiO2，阻挡层可以包括Ta/N，或Ta，本申请对此不作限定。
作为示例，当金属薄膜层可以包括Cu时，种子层可以包括Cu，本申请对此不作限定。
步骤150，对所述金属进行研磨，以去除所述衬底层的第二侧的表面上的除所述导通孔和所述凹孔之外的区域上的金属。
作为示例，上述对金属进行研磨，可以为从衬底层第二侧沉积的金属开始研磨。可选的，在研磨至衬底层的第二侧的表面上金属没有剩余时，仍然可以继续对衬底层的第二侧进行研磨，本申请对此不作限定。
参见图2E，示出了步骤150对应的晶圆的侧视图的一个示例。如图2E所示，在图2D的基础上，可以从衬底层01的第二表面012上的金属开始进行研磨，以去衬底层的第二表面012上除导通孔05和06、凹孔07之外的区域上的金属。作为示例，在图2E中，可以在研磨至衬底层01的第二表面012时停止。此时，该第二表面012上除导通孔05和06，以及凹孔07对应的区域之外没有金属剩余，并且导通孔05和06，以及凹孔07中的金属柱的高度与第二表面012平齐。
在一些可能的实现方式中，在研磨至衬底层01的第二表面012时，还可以继续沿衬底层01的第二侧继续研磨一段时间后停止。此时，通过研磨衬底层01会减薄，导通孔05和06，以及凹孔07的深度相应地会减小。作为一种可能的情况，如图14所示，经过一段时间的研磨，凹孔07的深度将减小为0，即衬底层01上凹孔07对应的区域与衬底层01第二侧新形成的表面平齐。可以理解的是，在对衬底层01的研磨过程中，导通孔05和06内的金属柱的高度始终与衬底层01第二侧新形成的表面平齐。
在一些可选的实施例中，当在衬底层的第二侧的表面上、导通孔内和凹孔内依次形成liner层、阻挡层、种子层和金属(即对应于图13所示的晶圆)时，作为一种可能的实现方式，如图15A所示，在从衬底层01的第二表面012上的金属开始进行研磨时，可以在研磨至liner层时停止。此时，导通孔05和06，以及凹孔07中的金属柱的高度与liner层 平齐。
作为另一种可能的实现方式，如图15B所示，从衬底层01的第二表面012上的金属开始进行研磨时，可以在研磨至衬底层01的第二表面012时停止。此时，导通孔05和06，以及凹孔07中的金属柱的高度与衬底层01的第二表面012平齐。
作为另一种可能的实现方式，如图15C所示，从衬底层01的第二表面012上的金属开始进行研磨时，可以在研磨至衬底层01的第二表面012时继续对衬底层01进行研磨。此时，通过研磨衬底层01会减薄，导通孔05和06，以及凹孔07的深度相应地会减小。
作为另一种可能的实现方式，如图15D所示，在研磨至衬底层01的第二表面012时继续对衬底层01进行研磨，直至导通孔07内的金属没有剩余。此时，凹孔07中可以包括liner层、阻挡层和种子层。在对衬底层01的研磨过程中，导通孔05和06内的金属柱的高度始终与衬底层01第二侧新形成的表面平齐。
由上述描述可知，在步骤150的研磨结束之后，凹孔中可以存在金属剩余，例如对应于上述图2E、图15A、图15B、图15C的情况，这样能够保证在研磨的过程中，凹孔中始终存在金属剩余。也就是说，凹孔的深度的不能太浅，需要保证在研磨的过程中，凹孔中始终存在金属剩余。
或者，在步骤150的研磨过程中凹孔中可以存在金属剩余，在步骤150的研磨结束之后，凹孔内可以没有金属剩余，例如对应图15D的情况。
或者，在步骤150的研磨过程中凹孔中可以存在金属剩余，在步骤150的研磨结束之后，衬底层01上可以不存在凹孔，例如对应图14的情况。
作为示例，在步骤150中，研磨可以为化学机械研磨(即CMP)，或者物理研磨，本申请实施例对此不作限定。
需要说明的是，本申请实施例可以采用标准的处理工艺执行步骤150，例如在CMP之前可以进行退火(anneal)处理，或者经过多次退火、CMP处理，比如anneal-CMP-anneal-CMP等处理，本申请对此不作限定。
在一些实施例中，在CMP完成之后，可以进行后续的加工流程，例如再布线层(redistributed layer，RDL)等，本申请对此不作限定。
因此，本申请实施例中，在晶圆上形成硅通孔时，可以从衬底层的一侧形成凹孔和用于形成硅通孔的导通孔，并在衬底层的该侧对衬底层表面、导通孔和凹孔沉积金属，这样在对衬底层表面上的金属进行研磨时，凹孔的设置能够使得在衬底层上没有导通孔的地方增加金属，有助于在研磨过程中金属尽可能地均匀分布，从而有助于提高研磨工艺的一致性和可靠性。
示例性的，在本申请实施例中，导通孔对应的TSV可以不是TSV array，或者不是vendor验证过的TSV array。而通过在衬底层上增加凹孔，能够在后续研磨工艺中，将晶圆的TSV等效为TSV array，或者vendor验证过的TSV array。因此，本申请实施例相比较不形成凹孔的TSV制作方案而言，能够有助于在后续研磨工艺过程中金属(metal)的分布更加均匀，从而降低研磨的复杂度。进一步的，由于本申请中导通孔对应的TSV可以不是TSV array或不是vendor验证过的TSV array，因此本申请能够根据产品需要，灵活地设计TSV图案，增大工艺窗口。
本申请实施例还提供了一种硅通孔结构，包括衬底层、介质层、金属层、导通孔和凹孔，其中，所述金属层包裹在所述介质层中，所述介质层和所述金属层位于所述衬底层的 第一侧，所述导通孔从所述衬底层的第二侧贯穿所述衬底层，且停止在所述金属层上，所述凹孔从所衬底层的第二侧形成，所述导通孔和所述凹孔内沉积有金属。
作为示例，该硅通孔结构例如可以为上述图2E、图15A、图15B、图15C以及图15D中所示的结构。具体的，衬底层、介质层、金属层、导通孔和凹孔可以参见上文中的描述，不再赘述。
一方面，介质层、金属层可以位于衬底层之上的部分，则凹孔可以位于衬底层的下表面上。当在衬底层的下表面形成金属层，或其他层结构时，凹孔内的金属能够有助于提高衬底层的下表面的粘附性。
另一方面，凹孔内的金属能够有助于提高衬底层的导热性。
应理解，在本文示出的实施例中，第一、第二以及各种数字编号仅为描述方便进行的区分，并不用来限制本申请实施例的范围。
还应理解，在本申请的实施例中，上述过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种硅通孔结构的制备方法，其特征在于，包括：
    提供晶圆，所述晶圆包括衬底层、介质层和金属层，其中，所述金属层包裹在所述介质层中，所述介质层和所述金属层位于所述衬底层的第一侧；
    从所述衬底层的第二侧形成贯穿所述衬底层的导通孔，所述导通孔停止在所述金属层上；
    从所述衬底层的第二侧形成凹孔；
    在所述衬底层的第二侧的表面、所述导通孔内和所述凹孔内沉积金属；
    对所述金属进行研磨，以去除所述衬底层的第二侧的表面上的除所述导通孔和所述凹孔之外的区域上的金属。
  2. 根据权利要求1所述的方法，其特征在于，在所述研磨结束后所述凹孔中存在金属剩余。
  3. 根据权利要求1或2所述的方法，其特征在于，所述导通孔的数量为至少一个，所述凹孔的数量为至少一个，每个所述导通孔在所述衬底层的第二侧的表面上形成第一图案，每个所述凹孔在所述衬底层的第二侧的表面上形成第二图案，其中，在所述第二侧的表面上至少一个所述第一图案和至少一个所述第二图案中在宽度方向上任意相邻的两个图案的距离相同，和/或在长度方向上任意相邻的两个图案的距离相同。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述导通孔的数量为1个，所述凹孔的数量为8个，且8个所述凹孔均匀分布在所述导通孔四周。
  5. 根据权利要求1-3任一项所述的方法，其特征在于，所述导通孔的数量为多个，多个所述导通孔包括第一部分导通孔和第二部分导通孔，其中，在所述衬底层的第二侧的表面上所述第一部分导通孔中在第一方向上任意相邻的两个导通孔之间具有第一距离，所述第二部分导通孔中在所述第一方向上任意相邻的两个导通孔之间具有第二距离，且所述第一距离是所述第二距离的整数倍，则所述凹孔位于所述第一部分导通孔中的所述第一方向上的相邻的两个导通孔之间，其中，所述第一方向为长度方向或宽度方向。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，在所述衬底层的第二侧的表面上所述凹孔的形状为圆形、矩形或菱形。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述凹孔的深度为1微米至30微米。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，所述在所述衬底层的第二侧的表面、所述导通孔内和所述凹孔内沉积金属，包括：
    在所述衬底层的第二侧的表面、所述导通孔内和所述凹孔内依次形成内衬层、阻挡层和种子层；
    通过电镀工艺在所述种子层上沉积所述金属。
  9. 根据权利要求8所述的方法，其特征在于，所述阻挡层包括Ta或TaN。
  10. 根据权利要求8或9所述的方法，其特征在于，所述种子层包括Cu。
  11. 根据权利要求1-10任一项所述的方法，其特征在于，所述金属包括Cu。
  12. 一种硅通孔结构，其特征在于，包括：
    衬底层、介质层、金属层、导通孔和凹孔；
    其中，所述金属层包裹在所述介质层中，所述介质层和所述金属层位于所述衬底层的第一侧，所述导通孔从所述衬底层的第二侧贯穿所述衬底层，且停止在所述金属层上，所述凹孔从所衬底层的第二侧形成，所述导通孔和所述凹孔内沉积有金属。
  13. 根据权利要求12所述的硅通孔结构，其特征在于，所述导通孔的数量为至少一个，所述凹孔的数量为至少一个，每个所述导通孔在所述衬底层的第二侧的表面上形成第一图案，每个所述凹孔在所述衬底层的第二侧的表面上形成第二图案，其中，在所述第二侧的表面上至少一个所述第一图案和至少一个所述第二图案中任意相邻的两个图案在宽度方向上距离相同，和/或在长度方向上距离相同。
  14. 根据权利要求12或13所述的硅通孔结构，其特征在于，所述导通孔的数量为1个时，所述凹孔的数量为8个，且8个所述凹孔均匀分布在所述导通孔四周。
  15. 根据权利要求12或13所述的硅通孔结构，其特征在于，所述导通孔的数量为多个，多个所述导通孔包括第一部分导通孔和第二部分导通孔，其中，在所述衬底层的第二侧的表面上所述第一部分导通孔中任意相邻的两个导通孔之间在第一方向上具有第一距离，所述第二部分导通孔中任意相邻的两个导通孔在所述第一方向上具有第二距离，且所述第一距离是所述第二距离的整数倍，则所述凹孔位于所述第一部分导通孔中的所述第一方向上的相邻的两个导通孔之间，其中，所述第一方向为长度方向或宽度方向。
  16. 根据权利要求12-15任一项所述的硅通孔结构，其特征在于，在所述衬底层的第二侧的表面上所述凹孔的形状为圆形、矩形或菱形。
  17. 根据权利要求12-16任一项所述的硅通孔结构，其特征在于，所述凹孔的深度为1微米至30微米。
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