CN115917744A8 - 鳍式场效应管、esd保护电路、滤波电路以及电子设备 - Google Patents

鳍式场效应管、esd保护电路、滤波电路以及电子设备 Download PDF

Info

Publication number
CN115917744A8
CN115917744A8 CN202080103261.XA CN202080103261A CN115917744A8 CN 115917744 A8 CN115917744 A8 CN 115917744A8 CN 202080103261 A CN202080103261 A CN 202080103261A CN 115917744 A8 CN115917744 A8 CN 115917744A8
Authority
CN
China
Prior art keywords
finfet
fins
field effect
effect transistor
esd protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080103261.XA
Other languages
English (en)
Other versions
CN115917744A (zh
Inventor
朱千明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of CN115917744A publication Critical patent/CN115917744A/zh
Publication of CN115917744A8 publication Critical patent/CN115917744A8/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0274Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20Resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种鳍式场效应管、ESD保护电路、滤波电路以及电子设备,该鳍式场效应管(FinFET),包括:一个或多个并列排布的鳍、多个有效栅极(G1,G2,G3)、第一冗余多晶硅(P1);该一个或多个鳍均沿第一方向延伸,该多个有效栅极(G1,G2,G3)、该第一冗余多晶硅(P1)均沿着第二方向延伸并覆盖于该一个或多个列排布的鳍(Fin)的表面上;该第一冗余多晶硅(P1)位于该多个有效栅极(G1,G2,G3)的一侧,该多个有效栅极(G1,G2,G3)中的每个有效栅极(G1,G2,G3)两侧的鳍分别为FinFET的源极端和漏极端;该多个有效栅极(G1,G2,G3)耦合到FinFET的栅极端;该第一冗余多晶硅(P1)耦合于FinFET的栅极端和电阻电位端之间。上述FinFET,充分利用冗余多晶硅,以冗余多晶硅作为电阻,减少电阻的占用面积,使芯片更加小型化。
CN202080103261.XA 2020-08-31 2020-08-31 鳍式场效应管、esd保护电路、滤波电路以及电子设备 Pending CN115917744A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/112663 WO2022041235A1 (zh) 2020-08-31 2020-08-31 鳍式场效应管、esd保护电路、滤波电路以及电子设备

Publications (2)

Publication Number Publication Date
CN115917744A CN115917744A (zh) 2023-04-04
CN115917744A8 true CN115917744A8 (zh) 2024-05-10

Family

ID=80354360

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080103261.XA Pending CN115917744A (zh) 2020-08-31 2020-08-31 鳍式场效应管、esd保护电路、滤波电路以及电子设备

Country Status (4)

Country Link
US (1) US20230230974A1 (zh)
EP (1) EP4199084A4 (zh)
CN (1) CN115917744A (zh)
WO (1) WO2022041235A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117491835B (zh) * 2023-12-29 2024-03-15 苏州元脑智能科技有限公司 测量方法、装置、系统、晶体管、集成电路、介质及设备

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9293452B1 (en) * 2010-10-01 2016-03-22 Altera Corporation ESD transistor and a method to design the ESD transistor
US8735993B2 (en) * 2012-01-31 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET body contact and method of making same
CN106558604B (zh) * 2015-09-24 2019-07-26 中芯国际集成电路制造(上海)有限公司 一种用于esd防护的栅控二极管
US10332871B2 (en) * 2016-03-18 2019-06-25 Intel IP Corporation Area-efficient and robust electrostatic discharge circuit
CN107799514B (zh) * 2016-08-29 2020-03-10 中芯国际集成电路制造(上海)有限公司 静电放电保护结构及其形成方法
US10777546B2 (en) * 2016-11-30 2020-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Planar and non-planar FET-based electrostatic discharge protection devices
US10242978B1 (en) * 2017-10-26 2019-03-26 Nanya Technology Corporation Semiconductor electrostatic discharge protection device

Also Published As

Publication number Publication date
WO2022041235A1 (zh) 2022-03-03
CN115917744A (zh) 2023-04-04
US20230230974A1 (en) 2023-07-20
EP4199084A4 (en) 2023-10-11
EP4199084A1 (en) 2023-06-21

Similar Documents

Publication Publication Date Title
US7989846B2 (en) Semiconductor device with three-dimensional field effect transistor structure
US11201213B2 (en) Channel all-around semiconductor device and method of manufacturing the same
KR101547390B1 (ko) 케스케이드 mos 트랜지스터를 포함하는 반도체 장치
JP2953416B2 (ja) 半導体装置
KR102211638B1 (ko) 반도체 장치
JP2006049846A (ja) 半導体装置
US4771327A (en) Master-slice integrated circuit having an improved arrangement of transistor elements for simplified wirings
CN115917744A8 (zh) 鳍式场效应管、esd保护电路、滤波电路以及电子设备
JP2007053316A (ja) Esd保護素子
JP5684850B2 (ja) 化合物半導体esd保護装置
US9509136B2 (en) ESD protection system, apparatus, and method with adjustable trigger voltage decoupled from DC breakdown voltage
JP2008235310A (ja) 半導体集積回路
CN111599862A (zh) 晶体管以及集成电路
US20210020629A1 (en) Circuit structure
US7170135B2 (en) Arrangement and method for ESD protection
US8115257B2 (en) Semiconductor apparatus
JPWO2019043888A1 (ja) 半導体集積回路装置
EP2966675B1 (en) Semiconductor device
JP2004031980A (ja) 複合型mosfet
TWI553822B (zh) 積體電路及其具自我靜電保護的輸出緩衝器佈局結構
EP3965156A1 (en) Integrated circuit device including metal-oxide semiconductor transistors
CN1331226C (zh) 具静电放电防护耐受能力的高压组件结构
CN1157789C (zh) 静电放电缓冲装置
JP2004221441A (ja) 半導体集積回路装置
US11398481B2 (en) Inverter cell structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CI02 Correction of invention patent application

Correction item: PCT international application to national stage day

Correct: 2023.02.20

False: 2023.02.17

Number: 14-01

Page: The title page

Volume: 39

Correction item: PCT international application to national stage day

Correct: 2023.02.20

False: 2023.02.17

Number: 14-01

Volume: 39

CI02 Correction of invention patent application