CN115917744A - 鳍式场效应管、esd保护电路、滤波电路以及电子设备 - Google Patents
鳍式场效应管、esd保护电路、滤波电路以及电子设备 Download PDFInfo
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- CN115917744A CN115917744A CN202080103261.XA CN202080103261A CN115917744A CN 115917744 A CN115917744 A CN 115917744A CN 202080103261 A CN202080103261 A CN 202080103261A CN 115917744 A CN115917744 A CN 115917744A
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- 235000012239 silicon dioxide Nutrition 0.000 description 3
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
- H01L27/0274—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
一种鳍式场效应管、ESD保护电路、滤波电路以及电子设备，该鳍式场效应管(FinFET)，包括：一个或多个并列排布的鳍、多个有效栅极(G1,G2,G3)、第一冗余多晶硅(P1)；该一个或多个鳍均沿第一方向延伸，该多个有效栅极(G1,G2,G3)、该第一冗余多晶硅(P1)均沿着第二方向延伸并覆盖于该一个或多个列排布的鳍(Fin)的表面上；该第一冗余多晶硅(P1)位于该多个有效栅极(G1,G2,G3)的一侧，该多个有效栅极(G1,G2,G3)中的每个有效栅极(G1,G2,G3)两侧的鳍分别为FinFET的源极端和漏极端；该多个有效栅极(G1,G2,G3)耦合到FinFET的栅极端；该第一冗余多晶硅(P1)耦合于FinFET的栅极端和电阻电位端之间。上述FinFET，充分利用冗余多晶硅，以冗余多晶硅作为电阻，减少电阻的占用面积，使芯片更加小型化。
Description
PCT国内申请，说明书已公开。
Claims (13)
- PCT国内申请，权利要求书已公开。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/112663 WO2022041235A1 (zh) | 2020-08-31 | 2020-08-31 | 鳍式场效应管、esd保护电路、滤波电路以及电子设备 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115917744A true CN115917744A (zh) | 2023-04-04 |
| CN115917744A8 CN115917744A8 (zh) | 2024-05-10 |
Family
ID=80354360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080103261.XA Pending CN115917744A (zh) | 2020-08-31 | 2020-08-31 | 鳍式场效应管、esd保护电路、滤波电路以及电子设备 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20230230974A1 (zh) |
| EP (1) | EP4199084A4 (zh) |
| CN (1) | CN115917744A (zh) |
| WO (1) | WO2022041235A1 (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117491835A (zh) * | 2023-12-29 | 2024-02-02 | 苏州元脑智能科技有限公司 | 测量方法、装置、系统、晶体管、集成电路、介质及设备 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9293452B1 (en) * | 2010-10-01 | 2016-03-22 | Altera Corporation | ESD transistor and a method to design the ESD transistor |
| US8735993B2 (en) * | 2012-01-31 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET body contact and method of making same |
| CN106558604B (zh) * | 2015-09-24 | 2019-07-26 | 中芯国际集成电路制造(上海)有限公司 | 一种用于esd防护的栅控二极管 |
| US10332871B2 (en) * | 2016-03-18 | 2019-06-25 | Intel IP Corporation | Area-efficient and robust electrostatic discharge circuit |
| CN107799514B (zh) * | 2016-08-29 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | 静电放电保护结构及其形成方法 |
| US10777546B2 (en) * | 2016-11-30 | 2020-09-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planar and non-planar FET-based electrostatic discharge protection devices |
| US10242978B1 (en) * | 2017-10-26 | 2019-03-26 | Nanya Technology Corporation | Semiconductor electrostatic discharge protection device |
-
2020
- 2020-08-31 WO PCT/CN2020/112663 patent/WO2022041235A1/zh unknown
- 2020-08-31 CN CN202080103261.XA patent/CN115917744A/zh active Pending
- 2020-08-31 EP EP20950904.1A patent/EP4199084A4/en active Pending
-
2023
- 2023-02-27 US US18/175,096 patent/US20230230974A1/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117491835A (zh) * | 2023-12-29 | 2024-02-02 | 苏州元脑智能科技有限公司 | 测量方法、装置、系统、晶体管、集成电路、介质及设备 |
| CN117491835B (zh) * | 2023-12-29 | 2024-03-15 | 苏州元脑智能科技有限公司 | 测量方法、装置、系统、晶体管、集成电路、介质及设备 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20230230974A1 (en) | 2023-07-20 |
| EP4199084A1 (en) | 2023-06-21 |
| EP4199084A4 (en) | 2023-10-11 |
| WO2022041235A1 (zh) | 2022-03-03 |
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| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CI02 | Correction of invention patent application |
Correction item: PCT international application to national stage day Correct: 2023.02.20 False: 2023.02.17 Number: 14-01 Page: The title page Volume: 39 Correction item: PCT international application to national stage day Correct: 2023.02.20 False: 2023.02.17 Number: 14-01 Volume: 39 |