CN115688671B - Wiring method, wiring device, terminal and storage medium - Google Patents
Wiring method, wiring device, terminal and storage medium Download PDFInfo
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Abstract
The application discloses a wiring method, a wiring device, a terminal and a storage medium, wherein the wiring method comprises the following steps: setting netlist names and wiring types of pins in n element modules in m target chips and an intermediate layer on a first display interface, and displaying a wiring diagram generated according to the netlist names and the wiring types of the pins on the target display interface in response to trigger operation executed by a target control in the first display interface. According to the application, the connection relation of each pin is determined by automatically identifying the netlist name and the signal type of the pin, so that the corresponding wiring diagram is displayed on the target display interface directly based on the connection relation between the pins, the automatic connection between the chip and the interposer is realized, and the wiring efficiency is improved. In addition, the netlist names and signal types of different pins are set, so that different wiring patterns are generated according to the netlist names and signal types of different pins, wiring between a chip and an intermediary layer is clear, and user experience is improved.
Description
Technical Field
The application relates to the technical field of EDA, in particular to a wiring method, a wiring device, a wiring terminal and a storage medium.
Background
Chiplet technology refers to decomposing a Soc (System on Chip) into a plurality of smaller chiplets, where the chiplets can have different functions and processes, and then packaging the modular chiplets together using a novel packaging technology to achieve interconnection of the chiplets, i.e., to form a heterogeneous integrated Chip.
To realize the wide application of the Chiplet technology, chiplet technology is applied to EDA (electronic design automation ). In EDA based on Chiplet technology, there are typically multiple chiplets that need to be connected to pins between the multiple chips according to customer requirements to make up a heterogeneous integrated chip. In addition, since the heterogeneous integrated chip needs to be connected with the active medium layer and the substrate. Therefore, how to realize wiring among a plurality of chiplets, active interposer, and substrate is a problem to be solved.
At present, wiring among a plurality of chiplets, active intermediaries and substrates is mainly achieved manually, i.e. experienced wiring personnel manually connect the plurality of chiplets, active intermediaries and substrates based on customer requirements.
However, the above method cannot realize automatic wiring among a plurality of chiplets, active interposer, substrate, so that the cost of resources such as manpower, time and the like increases, and the cost of resources is high.
Disclosure of Invention
The application mainly aims to provide a wiring method, a wiring device, a wiring terminal and a storage medium, so as to solve the problem of high resource cost in the related technology.
In order to achieve the above object, in a first aspect, the present application provides a wiring method comprising:
setting netlist names and wiring types of pins in n element modules in m target chips and an intermediate layer on a first display interface, wherein m and n are integers larger than 1;
responding to the triggering operation executed by the target control in the first display interface, and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface;
in the wiring diagram, wirings between the pins of the m target chips and the pins of the n element modules in the interposer and wirings between the pins of the m target chips are displayed in a differentiated manner.
In one possible implementation manner, the setting, at the first display interface, netlist names and routing types of pins in n component modules in the m target chips and the interposer includes:
Suspending a display pin setup window at the first display interface in response to a trigger operation performed for any pin of the n element modules in the m target chips and the interposer;
responding to trigger operation executed for netlist names and wiring types in a pin setting window which is displayed in a floating way on the first display interface, and displaying a netlist name input box or a netlist name list and a wiring type list in the pin setting window;
responding to the input operation executed for the netlist name input box or the selection operation executed by the netlist name list and the selection operation executed by the wiring type list, and displaying a target netlist name identifier corresponding to the target netlist name at any pin in the first display interface;
in response to a selection operation of the cursor for any target pin of the displayed target netlist name identifications, in response to a selection operation of the cursor for pins required to be connected with the target pin, the pin selected by the cursor displays the target netlist name identifications same as the target pin and is defined as the netlist name and the wiring type same as the target pin.
In one possible implementation, the routing types include a first routing type for characterizing routing through the interposer and a second routing type for characterizing routing through the rewiring layer.
In one possible implementation, the pin setup window displays a list of pin signal types in response to an operation performed for the list of wire types to select a wire type; the pin signal types include: the pin signal type is selected through cursor clicking.
In one possible implementation, in response to the operation of selecting the first routing type performed for the routing type list and the operation of selecting the digital signal performed by the pin signal type, a driving pin is selected from pins with the same netlist name, and a window is set for the driving pin to pick up a driving control.
In one possible implementation, the first display interface further includes a tool menu bar;
displaying a view of any tool in the tool menu at a cursor in response to a selection operation performed by the cursor for the any tool;
responsive to the cursor moving to any pin of the m target chips and n element modules in the interposer;
and responding to the triggering operation executed for any pin, and displaying the identification corresponding to any tool at any pin.
In one possible implementation, at least passive electronic components or contacts are included in the tool menu.
In one possible implementation manner, after the responding to the triggering operation performed on the any pin and displaying the identifier corresponding to the any tool at the any pin, the method further includes:
when any tool is the contact, responding to a triggering operation executed for the identifier corresponding to the contact displayed at any pin, and suspending and displaying a contact setting window on the first display interface;
and responding to the selection operation executed for the contact name list in the contact setting window, displaying the names of the contacts, wherein the names of the contacts are in one-to-one correspondence with the names of the contacts on the interposer on the target display interface.
In one possible implementation, the target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control;
the responding to the triggering operation executed by the target control in the first display interface displays the wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface, and the method comprises the following steps:
The second display interface is displayed in response to the triggering operation executed by the first control in the first display interface, wherein the m target chips and the intermediary layer are displayed in the second display interface,
connecting wires belonging to the same target netlist name between the pins of the m target chips and the pins of the n element modules in the interposer;
responding to the triggering operation executed by the second control in the first display interface, displaying a third display interface, the third display interface displaying the m target chips and the intermediary layer,
and connecting wires among the pins of the m target chips, which belong to the same target netlist name.
In one possible implementation, the target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control;
the responding to the triggering operation executed by the target control in the first display interface displays the wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface, and the method comprises the following steps:
the second display interface is displayed in response to the triggering operation executed by the first control in the first display interface, wherein the m target chips and the intermediary layer are displayed in the second display interface,
Connecting wires which belong to the same target netlist name and belong to the same wiring type between the pins of the m target chips and the pins of the n element modules in the intermediate layer;
responding to the triggering operation executed by the second control in the first display interface, displaying a third display interface, the third display interface displaying the m target chips and the intermediary layer,
and connecting wires among the pins of the m target chips, which belong to the same target netlist name and the same wiring type.
In one possible implementation, the method further includes:
responding to a triggering operation executed by a first control in a second display interface, and displaying connecting lines which belong to the same target netlist name and belong to a first wiring type among the m target chips, the interposer, pins of the m target chips and pins of n element modules in the interposer in the second display interface;
responding to a triggering operation executed by a second control in a second display interface, and displaying connecting lines which belong to the same target netlist name and belong to a second wiring type among the m target chips, the interposer, pins of the m target chips and pins of n element modules in the interposer in the second display interface;
Responding to a triggering operation executed by a first control in a third display interface, and displaying connecting wires which belong to the same target netlist name and belong to a first wiring type among the m target chips, the interposer and pins of the m target chips in the third display interface;
and responding to a triggering operation executed by a second control in a third display interface, and displaying the m target chips, the interposer and connecting wires which belong to the same target netlist name and belong to a second wiring type among pins of the m target chips in the third display interface.
In one possible implementation, the target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control;
responding to the triggering operation executed by the first control of the first display interface, displaying the second display interface, wherein the m target chips, the medium layer and the substrate are displayed in the second display interface, the medium layer is provided with contacts, the substrate is provided with contact pads which can be connected with the contacts,
connecting wires belonging to the same target netlist name and connecting wires of the contact and the contact pad are arranged between the pins of the m target chips and the pins of the n element modules in the interposer;
Responding to the triggering operation executed by the second control of the first display interface, displaying the third display interface, wherein the third display interface displays the m target chips, an intermediate layer and a substrate, wherein the intermediate layer is provided with contacts, the substrate is provided with contact pads which can be connected with the contacts,
and connecting wires among the pins of the m target chips, which belong to the same target netlist name, and connecting wires of the contact points and the contact pads.
In a second aspect, an embodiment of the present invention provides a wiring device including:
the setting module is used for setting netlist names and wiring types of pins in n element modules in m target chips and an interposer on a first display interface, wherein m and n are integers larger than 1;
the wiring module is used for responding to the triggering operation executed by the target control in the first display interface and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface;
in the wiring diagram, wirings between the pins of the m target chips and the pins of the n element modules in the interposer and wirings between the pins of the m target chips are displayed in a differentiated manner.
In a third aspect, an embodiment of the present invention provides a terminal including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps of any one of the routing methods described above when executing the computer program.
In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the wiring methods described above.
The embodiment of the invention provides a wiring method, a wiring device, a terminal and a storage medium, comprising the following steps: setting netlist names and wiring types of pins in n element modules in m target chips and an interposer layer on a first display interface, and displaying a wiring diagram generated according to the netlist names and the wiring types of the pins on the target display interface in response to trigger operation executed by a target control in the first display interface. According to the invention, the connection relation of each pin is determined by automatically identifying the netlist name and the signal type of the pin, so that the corresponding wiring diagram is displayed on the target display interface directly based on the connection relation between the pins, the automatic connection between the chip and the interposer is realized, and the wiring efficiency is improved. In addition, the netlist names and signal types of different pins are set, so that different wiring patterns are generated according to the netlist names and signal types of different pins, and the wiring between the chip and the interposer and the wiring between the chip and the chip are distinguished and displayed, so that the wiring between the chip and the interposer is clear, and the user experience is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application, are incorporated in and constitute a part of this specification. The drawings and their description are illustrative of the application and are not to be construed as unduly limiting the application. In the drawings:
FIG. 1 is a flow chart of an implementation of a wiring method provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a first display interface according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a pin setup window according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a pin setup window according to another embodiment of the present application;
FIG. 5 is a schematic diagram of a pin setup window according to another embodiment of the present application;
FIG. 6 is a schematic diagram of a chiplet U12 provided in accordance with an embodiment of the present application;
FIG. 7 is a schematic diagram of a tool menu bar provided by an embodiment of the present application;
FIG. 8 is a schematic diagram of a resistance setting window according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a chiplet U12 provided in accordance with another embodiment of the present application;
FIG. 10 is a schematic view of a contact setting window according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a contact name list provided by an embodiment of the present application;
Fig. 12 is a schematic view of a contact setting window according to another embodiment of the present invention;
FIG. 13 is a schematic diagram of a second display interface according to an embodiment of the present invention;
FIG. 14 is another schematic view of a second display interface according to an embodiment of the present invention;
FIG. 15 is a schematic view of a third display interface according to an embodiment of the present invention;
FIG. 16 is a schematic diagram of a second display interface according to another embodiment of the present invention;
FIG. 17 is a schematic diagram of a third display interface according to another embodiment of the present invention;
FIG. 18 is a schematic diagram of a wiring switching button provided by an embodiment of the present invention;
fig. 19 is a schematic structural view of a wiring device according to an embodiment of the present invention;
fig. 20 is a schematic diagram of a terminal according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
It should be understood that, in various embodiments of the present invention, the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
It should be understood that in the present invention, "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that in the present invention, "plurality" means two or more. "and/or" is merely an association relationship describing an association object, and means that three relationships may exist, for example, and/or B may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. "comprising A, B and C", "comprising A, B, C" means that all three of A, B, C comprise, "comprising A, B or C" means that one of the three comprises A, B, C, and "comprising A, B and/or C" means that any 1 or any 2 or 3 of the three comprises A, B, C.
It should be understood that in the present invention, "B corresponding to a", "a corresponding to B", or "B corresponding to a" means that B is associated with a, from which B can be determined. Determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information. The matching of A and B is that the similarity of A and B is larger than or equal to a preset threshold value.
As used herein, "if" may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the following description will be made by way of specific embodiments with reference to the accompanying drawings.
In one embodiment, as shown in fig. 1, a wiring method is provided, comprising the steps of:
step S101: netlist names and routing types of pins in n component modules in m target chips and an interposer are set in a first display interface.
The target chip can be any chip, and is selected according to the requirements of customers, such as a sensor chip, a power chip and the like. The component module in the interposer is preset, wherein the component module is set based on the type of the interposer, and the component module can comprise any electronic device, circuit and combination of the electronic device and the circuit, wherein the electronic device can be an amplifier device, a power chip, an MCU and the like.
Wherein m and n are integers greater than 1.
As shown in fig. 2, the first display interface 21 displays an interposer 22 and 2 target chips, wherein 2 component modules, respectively S4 and S5, are in the interposer 22, and the target chips disposed on the right side of the interposer 22 are U12 and U15, respectively.
As can be seen from fig. 2, whether the component modules on the interposer 22 or some of the pins of the target chip on the right side thereof are required to be set according to the customer requirements, the set items include the netlist names of the pins, the routing types, and the Extended lots. The set operation method for the pins in the n element modules in the m target chips and the interposer is the same.
Further, the operations performed for setting netlist names and routing types of pins in n component modules in the interposer and m target chips at the first display interface mainly include: a pin setting window is displayed in suspension on a first display interface in response to a triggering operation executed for any pin of n element modules in m target chips and an intermediate layer, then a netlist name input frame or a netlist name list and a wiring type list are displayed on the pin setting window in response to a triggering operation executed for the netlist names and wiring types in the pin setting window displayed in suspension on the first display interface, and then a target netlist name identifier corresponding to the target netlist name is displayed on any pin in the first display interface in response to an input operation executed for the netlist name input frame or a selection operation executed for the netlist name list and a selection operation executed for the wiring type list.
Wherein the wiring types include: the first wiring type is used for representing wiring through the intermediate layer, and the second wiring type is used for representing wiring through the rewiring layer. Optionally, the routing types may also include a third routing type for characterizing routing through the re-routing layer and/or the interposer.
After selecting the wiring types corresponding to the pins, the pin signal types corresponding to different wiring types can be selected. Namely, according to the selection operation performed in response to the input operation performed for the netlist name input box or the netlist name list and the selection operation performed for the wiring type list in the above steps, then in response to the operation performed for the wiring type list to select the wiring type, the pin setting window displays the pin signal type list; the pin signal types include: the pin signal type is selected by clicking a cursor.
In one possible implementation, in response to an operation performed for the routing type list to select the first routing type or the third routing type and an operation performed for the pin signal type to select the digital signal, a drive pin is selected from pins of the same netlist name, and a window is set for the drive pin to select the drive control.
Specifically, as shown in fig. 3, when clicking the C3 pin on the chip U12, a pin setting window is displayed in a floating manner on the chip U12, where the pin setting window includes three boxes, and the upper box on the left side is a netlist name input box or a netlist name list, and the netlist name setting of the pin C3 can be achieved by inputting a netlist name (e.g., the Enter Netname shown in fig. 3) in the netlist name input box. In addition, the upper left box can also be a netlist name list, and the netlist name setting of the pin C3 is realized through selecting any one netlist name in the netlist name list.
The right frame in the pin setting window is mainly used for setting the wiring types of pins, and for pins which are not subjected to wiring type setting, the Unassign is displayed in the frame first, and after clicking the Unassign, a wiring type list is directly displayed, wherein the wiring type list comprises three wiring types, namely a first wiring type (Programmable), a second wiring type (Metal Only) and a third wiring type (Metal Programmable). By clicking any wiring type, the setting of the wiring type of the pin C3 can be realized. Alternatively, only two types of wiring types, namely, a first wiring type (Programmable) and a second wiring type (Metal Only), may be included in the wiring type list.
With reference to fig. 4, after setting the wiring type of the pin C3 to the first wiring type (Programmable), the pin signal type corresponding to the Programmable, that is, the Digital signal (Digital), the Analog signal (Analog), and the Power signal (Power), may be displayed by clicking the Programmable.
By setting the netlist name of the pin C3 as U12 DEC3 in the above manner, after the wiring type is set as Programmable, clicking a confirmation key in the pin setting window, wherein the confirmation key can be represented by Save, ok and the like, and the pin setting window is hidden or retracted. Accordingly, an identification corresponding to the netlist name, namely U12 DEC3, is displayed at pin C3. Wherein, the U12 DEC3 is displayed with a preset highlighting color, which can be defined by a customer or selected through a color setting menu.
Referring to fig. 2 and 6, after setting both the netlist name and the routing type of the pin C3, responding to a selection operation of the cursor for the target pin C3, responding to a selection operation of the cursor for the other pins, for example, the D2 pin on the U15 chip, and selecting the D2 pin to be connected with the pin C3; the same netlist name as pin C3 is displayed at the selected pin and the same highlighting color as pin C3 is displayed, at which point the D2 pin has been defined as the same netlist name and routing type as C3.
Referring to fig. 5, if the C3 wiring type is the first wiring type (Programmable) or the third wiring type (metal Programmable), the signal type is selected as the Digital signal (Digital) type, and one of the pins with the same netlist name, i.e. pin C3 and pin D2, needs to be selected as a driving pin, and the driving control (driver) in the three lower right-hand corner controls is checked. This is because the driver pins need to be selected when the digital signal lines are routed through the interposer.
Referring to fig. 5, if the C3 wiring type is the second wiring type (metal Programmable) or the third wiring type (metal only), a flying lead control (performance title) in the three controls at the lower right corner may be checked, then the target display interface may display a flying lead between the pins routed through the re-routing layer, and when the target display interface needs to edit the pin connection line routed through the re-routing layer, the pins with the same name of the netlist may be identified by the flying lead between the pins.
In addition, the lower left box in the pin set window is.
The first display interface in the present application further includes a tool menu bar, that is, an a area, a B area, and a C area in fig. 2, where the a area, the B area, and the C area may set various setting items in each area according to a user's requirement. It should be noted that the setting items in the respective areas are not repeatable.
Referring to fig. 7, a tool menu bar is set in the area a, where the tool (tool) menu bar includes passive electronic components, contacts (bond pads), print buttons, and withdraw operation buttons from left to right.
In the case where the Tool (TOOLS) menu bar includes a resistor, a contact (BONDPAD), a view of any tool is displayed at the cursor in response to a selection operation performed by the cursor for any tool in the tool menu, then a corresponding identification of any tool is displayed at any pin in response to movement of the cursor to any pin in the n component modules in the m target chips and interposer, and then in response to a triggering operation performed for any pin.
When any tool is a resistor, by clicking the icon of the resistor shown in fig. 7, the icon of the resistor is displayed at the cursor, and simultaneously the resistor resistance setting window shown in fig. 8 is popped up, after 10000 (i.e. 10 k) is input, the cursor is moved to the pin D2 of the chip U12, and then it can be seen that a resistor with a resistance of 10k is connected to the pin D2 shown in fig. 9, and the icon of the resistor and the mark rn_1 are displayed.
When any tool is bond pad, by clicking the bond pad icon shown in fig. 6, the bond pad icon is displayed at the cursor, and the bond pad icon is directly moved to the pin B4 of the chip U12, then it can be seen that a bond pad is connected to the pin B4 shown in fig. 9, and the bond pad icon and the identification bond pad_2 are displayed.
After the bond pad is set on the corresponding pin in the above manner, when the bond pad jumps to the target display interface, the bond pad set before and the name corresponding to the bond pad are displayed on the interposer displayed in the target display interface. Therefore, the name corresponding to the bond pad needs to be set on the first display interface, and the specific implementation manner is as follows: and displaying the names of the contacts in a one-to-one correspondence manner with the names of the contacts on the interposer on the target display interface in response to a triggering operation executed for the identifier corresponding to the contact displayed at any pin, suspending the display of the contact setting window on the first display interface, and then in response to a selecting operation executed for the contact name list in the contact setting window.
Through the above operation, a bond pad is connected to the pin B4 shown in fig. 9, and an icon of the bond pad and the identifier bond pad_2 are displayed. Then clicking on the bond pad at B4 pops up the contact setting window shown in fig. 10, and clicking on the contact setting window displays the contact name list shown in fig. 11, where the contact name list displays a plurality of contact names, such as pacdio_i_0/12, pacdio_i_1/20, pacdio_i_2/28, and so on. The corresponding contact name is selected by clicking on the box in front of the contact name. After clicking on the box in front of the Padio_I_4/44, the contact name list is hidden or collapsed, after which Padio_I_4/44 is displayed in the contact setup window as shown in FIG. 12. Finally, clicking the confirm button Save.
Step S102: and responding to the triggering operation executed by the target control in the first display interface, and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface.
And the wiring patterns are used for distinguishing and displaying the wiring between the pins of the m target chips and the pins of the n element modules in the intermediate layer and the wiring between the pins of the m target chips.
The target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control, where the first control and the second control may be controls disposed in any of the area a, the area B, and the area C in the first display interface shown in fig. 2.
Based on the distinction of the wirings between the pins of the m target chips and the pins of the n element modules in the interposer (hereinafter may be simply referred to as "chip interposer wirings"), the wirings between the pins of the m target chips (hereinafter may be simply referred to as "chip-to-chip wirings"), different distinguished wirings may be displayed in different display interfaces. For example, inter-chip wiring may be displayed in the second display interface and inter-chip wiring may be displayed in the third display interface.
The second display interface is used for displaying connecting wires which belong to the same target netlist name between the pins of the m target chips and the pins of the n element modules in the intermediate layer. The specific implementation steps are as follows: responding to the triggering operation executed by the first control in the first display interface, displaying a second display interface, wherein,
and m target chips and an intermediate layer are displayed in the second display interface, and connecting wires which belong to the same target netlist name are arranged between the pins of the m target chips and the pins of n element modules in the intermediate layer.
Illustratively, clicking on a first control disposed in the first display interface jumps to the second display interface. As shown in fig. 13, the second display interface includes a chip layer 1201 (including a chip U15) and an interposer 1202 sequentially arranged from top to bottom, where a pin C2 of the element module S4 in the interposer and a pin A1 of the chip U15 belong to the same netlist name (e.g., GPIO 0), and a connection line between the pin C2 and the pin A1 is displayed on the interposer 1202. In addition, pin C1 of element module S4 in the interposer belongs to the same netlist name as pin A3 of chip U15 (e.g., GPIO 1), and then the connection lines of pin C1 and pin A3 are displayed in interposer 1202.
According to the above example, further, a menu bar may be further disposed on the right side of the second display interface, where a route view button is disposed; clicking a first control arranged in the first display interface, and jumping to a second display interface, wherein only the chip layer 1201 and the interposer 1202 are displayed at the moment, and connecting wires between pins are not displayed; responding to the cursor for connection operation of the pin C1 and the pin A3 and the pin C2 and the pin A1 or responding to triggering operation executed for a route view button in a menu bar in a second display interface; pin C1 and pin A3 and pin C2 and pin A1 are connected by a connecting wire.
Optionally, as shown in fig. 14, a region 12021 may also be disposed on the interposer 1202, where the region 12021 is connected to the component modules in the interposer 1202. The target chip may be connected to the component module in the interposer 1202 by routing to the area 12021 on the interposer 1202 when it is desired to connect to the component module in the interposer 1202. If the pin A1 of the chip U15 needs to be connected to the pin C2 of the device module S4, the pin A1 may be routed to the area 12021, and the area 12021 communicates with the pin C2 of the device module S4 in the interposer 1202.
The third display interface is used for displaying connecting lines among pins of the m target chips, which belong to the same target netlist name. The specific implementation steps are as follows: and responding to the triggering operation executed by the first control in the first display interface, displaying a third display interface, wherein m target chips and an intermediate layer are displayed in the third display interface, and connecting lines among pins of the m target chips belong to the same target netlist name.
Illustratively, clicking on a second control disposed in the first display interface jumps to the third display interface. As shown in fig. 15, in the third display interface, a chip layer 1201 (including a chip U12 and a chip U15) and an interposer 1202 are displayed sequentially from top to bottom, where a pin C3 of the chip U12 and a pin A2 of the chip U15 belong to the same netlist name (i.2c0_sda), and then a connection relationship between the pin C3 and the pin A2 is displayed in the interposer 1202. In addition, pin C1 of chip U12 and pin A3 of chip U15 belong to the same netlist name (i.e., i3c1_sda), and then the connection between pin C1 and pin A3 is shown.
Optionally, the second display interface may be further configured to display connection lines between pins of the m target chips and pins of n element modules in the interposer, where the connection lines belong to the same target netlist name and belong to the same wiring type, that is, display of the connection lines is controlled according to the wiring type, for example, only display connection lines of the first wiring type or only display connection lines of the second wiring type.
Further, in the second display interface, a first control and a second control may be further provided, and control of the wiring type of the displayed connection line is performed through the first control and the second control. For example, when the first control in the second display interface is triggered, only the connection lines which belong to the same target netlist name and belong to the first wiring type between the pins of the m target chips and the pins of the n element modules in the interposer may be displayed in the second display interface.
Optionally, the third display interface may be further configured to display connection lines between pins of the m target chips, which belong to the same target netlist name and belong to the same wiring type, that is, display of the connection lines is controlled according to the wiring type, for example, only display connection lines of the first wiring type or only display connection lines of the second wiring type.
Further, in the third display interface, a first control and a second control may be further provided, and control of the wiring type of the displayed connection line is performed through the first control and the second control. For example, when the first control in the third display interface is triggered, only the connection lines among the pins of m target chips, which belong to the same target netlist name and belong to the first wiring type, can be displayed in the third display interface, and when the second control in the third display interface is triggered, only the connection lines among the pins of m target chips, which belong to the same target netlist name and belong to the second wiring type, can be displayed in the third display interface.
In the embodiment of the invention, the connection relation between the pins and the external bonding pads can be set and displayed in the interface.
As shown in fig. 16, the second display interface may include a chip layer 1201 (including a chip U15), an interposer 1202, an element module S4 in the interposer 1202, and a substrate 1205 sequentially arranged from top to bottom, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, and the number and arrangement of contact pads in fig. 15 are merely examples. On the basis of the pin connection relationship of fig. 13, the following pad connection relationship is also provided: the contact 11 on the interposer 1202 is connected to the contact pad 21 on the substrate 1205, and the contact 13 on the interposer 1202 is connected to the contact pad 23 on the substrate 1205. At this time, the connection lines between the contact 11 on the interposer 1202 and the contact pad 21 on the substrate 1205, and the connection lines between the contact 13 on the interposer 1202 and the contact pad 23 on the substrate 1205 are displayed in the second display interface. If pins A1, C2 are provided to connect with contacts 11 on interposer 1202, pins A1, C2 will be connected to the outside of the chip through contact pads 21.
As shown in fig. 17, a third display interface may include a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202, and a substrate 1205, which are sequentially arranged from top to bottom, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, and the number and arrangement of contact pads in fig. 16 are only examples. On the basis of the pin connection relationship of fig. 14, the following pad connection relationship is also provided: the contact 11 on the interposer 1202 is connected to the contact pad 21 on the substrate 1205, and the contact 13 on the interposer 1202 is connected to the contact pad 23 on the substrate 1205. At this time, the third display interface displays the connection lines between the contact 11 on the interposer 1202 and the contact pad 21 on the substrate 1205, and the connection lines between the contact 13 on the interposer 1202 and the contact pad 23 on the substrate 1205. If pins A2, C3 are provided to connect with contacts 11 on interposer 1202, pins A2, C3 will be connected to the outside of the chip through contact pads 21.
In the embodiment of the invention, a menu bar can be arranged on the right side of the third display interface, and an editing list is arranged on the menu bar; and selecting a flying wire control (performance Tilemap) in three controls at the right lower corners of the pin C3 and the pin C1 pin setting window on the first display interface, clicking a second control arranged in the first display interface, and jumping to a third display interface, wherein the third display interface can display flying wires between the pin C3 and the pin A2 as well as between the pin C1 and the pin A3, and when the target display interface needs to edit connecting wires between the pin C3 and the pin A2 and between the pin C1 and the pin A3, the pins with the same names of netlists can be identified through the flying wires between the pins. Selecting editable options in an edit list in a menu bar in a third display interface; connecting wires are formed by connecting the pins C3 and A2 with the pins A1 and A3 through a cursor, or connecting wires between the pins C3 and A2 and between the pins C1 and A3 are formed by clicking an automatic connecting button in a menu bar in a third display interface.
Note that, the four sides of the periphery of the interposer 1202 are uniformly provided with contacts (bond pads) 1203, and each bond pad is marked with a respective code. Among them, the BONDPAD shown in fig. 13, 14 and 15 is only an example.
In addition, the application can also realize the jump or switch of the first display interface, the second display interface and the third display interface through the first interface control, the second interface control and the third interface control respectively. The first interface control may be a "scheme View" button, the second interface control may be an "Optimize" button, etc., and the third interface control may be a "Package View" button, etc. The buttons corresponding to the three interface controls are only examples, and can be represented by other identifiers.
Because the menu bar above the first display interface, the second display interface and the third display interface comprises the three interface controls, the user can jump to the corresponding display interface automatically by clicking any one of the three interface controls. The first display interface is provided with m target chips and an intermediate layer, and connecting lines belonging to the same target netlist name pin on the m target chips and the intermediate layer.
In addition, only one target display interface may be provided, that is, the second display interface and the third display interface are displayed on one interface, and the view is switched by providing a first Wiring button, a second Wiring button and a third Wiring button in a toolbar on the right side of the target display interface, where the first Wiring button, the second Wiring button and the third Wiring button may be provided as a Wiring switching button (wire) as shown in fig. 18.
The embodiment of the invention provides a wiring method, which comprises the following steps: setting netlist names and wiring types of pins in n element modules in m target chips and an interposer layer on a first display interface, and displaying a wiring diagram generated according to the netlist names and the wiring types of the pins on the target display interface in response to trigger operation executed by a target control in the first display interface. According to the invention, the connection relation of each pin is determined by automatically identifying the netlist name and the signal type of the pin, so that the corresponding wiring diagram is displayed on the target display interface directly based on the connection relation between the pins, the automatic connection between the chip and the interposer is realized, and the wiring efficiency is improved. In addition, the netlist names and signal types of different pins are set, so that different wiring patterns are generated according to the netlist names and signal types of different pins, wiring between a chip and an intermediary layer is clear, and user experience is improved.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.
The following are device embodiments of the invention, for details not described in detail therein, reference may be made to the corresponding method embodiments described above.
Fig. 19 shows a schematic structural diagram of a wiring device according to an embodiment of the present invention, and for convenience of explanation, only a portion related to the embodiment of the present invention is shown, and the wiring device includes a setting module 1801 and a wiring module 1802, specifically as follows:
a setting module 1801, configured to set netlist names and routing types of pins in n element modules in m target chips and an interposer on a first display interface, where m and n are integers greater than 1;
the wiring module 1802 is configured to respond to a triggering operation executed by a target control in a first display interface, and display, on the target display interface, a wiring diagram generated according to the name of the pin netlist and the wiring type;
in the wiring diagram, wirings between the pins of the m target chips and the pins of the n element modules in the interposer and wirings between the pins of the m target chips are displayed in a differentiated manner.
The specific description of the wiring device may refer to the specific description of the wiring method, and in order to avoid repetition, a detailed description will be omitted.
Fig. 20 is a schematic diagram of a terminal according to an embodiment of the present invention. As shown in fig. 20, the terminal 19 of this embodiment includes: a processor 1901, a memory 1902, and a computer program 1903 stored in the memory 1902 and executable on the processor 1901. The steps in the various wiring method embodiments described above, such as steps 101 through 102 shown in fig. 1, are implemented when the processor 1901 executes the computer program 1903. Alternatively, the processor 1901, when executing the computer program 1903, performs the functions of the modules/units in the wiring device embodiments described above, such as the functions of the modules/units 1801 to 1802 shown in fig. 19.
The present invention also provides a readable storage medium having a computer program stored therein, which when executed by a processor is configured to implement the wiring method provided in the above-described various embodiments.
The readable storage medium may be a computer storage medium or a communication medium. Communication media includes any medium that facilitates transfer of a computer program from one place to another. Computer storage media can be any available media that can be accessed by a general purpose or special purpose computer. For example, a readable storage medium is coupled to the processor such that the processor can read information from, and write information to, the readable storage medium. In the alternative, the readable storage medium may be integral to the processor. The processor and the readable storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC). In addition, the ASIC may reside in a user device. The processor and the readable storage medium may reside as discrete components in a communication device. The readable storage medium may be read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tape, floppy disk, optical data storage device, etc.
The present invention also provides a program product comprising execution instructions stored in a readable storage medium. The at least one processor of the apparatus may read the execution instructions from the readable storage medium, and execution of the execution instructions by the at least one processor causes the apparatus to implement the wiring methods provided by the various embodiments described above.
In the above described embodiments of the apparatus, it is understood that the processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (13)
1. A wiring method, characterized by comprising:
setting netlist names and wiring types of pins in n element modules in m target chips and an intermediate layer on a first display interface, wherein m and n are integers larger than 1;
responding to the triggering operation executed by the target control in the first display interface, and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface;
in the wiring diagram, wiring between pins of the m target chips and pins of n element modules in the interposer and wiring between pins of the m target chips are distinguished and displayed;
the wiring types include a first wiring type for characterizing wiring through the interposer and a second wiring type for characterizing wiring through the rewiring layer;
the target display interface comprises a second display interface and a third display interface, and the target control comprises a first control and a second control;
the responding to the triggering operation executed by the target control in the first display interface displays the wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface, and the method comprises the following steps:
The second display interface is displayed in response to the triggering operation executed by the first control in the first display interface, wherein the m target chips and the intermediary layer are displayed in the second display interface,
connecting wires which belong to the same target netlist name and belong to the same wiring type between the pins of the m target chips and the pins of the n element modules in the intermediate layer;
responding to the triggering operation executed by the second control in the first display interface, displaying a third display interface, the third display interface displaying the m target chips and the intermediary layer,
and connecting wires among the pins of the m target chips, which belong to the same target netlist name and the same wiring type.
2. The routing method of claim 1, wherein the setting netlist names and routing types of pins in n component modules in m target chips and intermediaries at the first display interface comprises:
suspending a display pin setup window at the first display interface in response to a trigger operation performed for any pin of the n element modules in the m target chips and the interposer;
Responding to trigger operation executed for netlist names and wiring types in a pin setting window which is displayed in a floating way on the first display interface, and displaying a netlist name input box or a netlist name list and a wiring type list in the pin setting window;
responding to the input operation executed for the netlist name input box or the selection operation executed by the netlist name list and the selection operation executed by the wiring type list, and displaying a target netlist name identifier corresponding to a target netlist name at any pin in the first display interface;
in response to a selection operation of the cursor for any target pin of the displayed target netlist name identifications, in response to a selection operation of the cursor for pins required to be connected with the target pin, the pin selected by the cursor displays the target netlist name identifications same as the target pin and is defined as the netlist name and the wiring type same as the target pin.
3. The wiring method as in claim 1, wherein the pin setup window displays a list of pin signal types in response to an operation of selecting a wiring type performed for the list of wiring types; the pin signal types include: the pin signal type is selected through cursor clicking.
4. The routing method of claim 3, wherein in response to the operation of selecting the first routing type performed for the list of routing types and the operation of selecting the digital signal performed by the pin signal type, a drive pin is selected among pins of a same netlist name, and a window tick drive control is set at a pin of the drive pin.
5. The routing method of claim 1, wherein the first display interface further comprises a tool menu bar;
displaying a view of any tool in the tool menu at a cursor in response to a selection operation performed by the cursor for the any tool;
responsive to the cursor moving to any pin of the m target chips and n element modules in the interposer;
and responding to the triggering operation executed for any pin, and displaying the identification corresponding to any tool at any pin.
6. The routing method of claim 5, wherein at least passive electronic components or contacts are included in the tool menu.
7. The routing method of claim 6, wherein after displaying the identifier corresponding to the arbitrary tool at the arbitrary pin in response to the trigger operation performed for the arbitrary pin, further comprising:
When any tool is the contact, responding to a triggering operation executed for the identifier corresponding to the contact displayed at any pin, and suspending and displaying a contact setting window on the first display interface;
and responding to the selection operation executed for the contact name list in the contact setting window, displaying the names of the contacts, wherein the names of the contacts are in one-to-one correspondence with the names of the contacts on the interposer on the target display interface.
8. The routing method of claim 1, wherein the target display interface comprises a second display interface and a third display interface, the target control comprising a first control and a second control;
the responding to the triggering operation executed by the target control in the first display interface displays the wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface, and the method comprises the following steps:
the second display interface is displayed in response to the triggering operation executed by the first control in the first display interface, wherein the m target chips and the intermediary layer are displayed in the second display interface,
connecting wires belonging to the same target netlist name between the pins of the m target chips and the pins of the n element modules in the interposer;
Responding to the triggering operation executed by the second control in the first display interface, displaying a third display interface, the third display interface displaying the m target chips and the intermediary layer,
and connecting wires among the pins of the m target chips, which belong to the same target netlist name.
9. The wiring method as in claim 1, wherein said method further comprises:
responding to a triggering operation executed by a first control in a second display interface, and displaying connecting lines which belong to the same target netlist name and belong to a first wiring type among the m target chips, the interposer, pins of the m target chips and pins of n element modules in the interposer in the second display interface;
responding to a triggering operation executed by a second control in a second display interface, and displaying connecting lines which belong to the same target netlist name and belong to a second wiring type among the m target chips, the interposer, pins of the m target chips and pins of n element modules in the interposer in the second display interface;
responding to a triggering operation executed by a first control in a third display interface, and displaying connecting wires which belong to the same target netlist name and belong to a first wiring type among the m target chips, the interposer and pins of the m target chips in the third display interface;
And responding to a triggering operation executed by a second control in a third display interface, and displaying the m target chips, the interposer and connecting wires which belong to the same target netlist name and belong to a second wiring type among pins of the m target chips in the third display interface.
10. The routing method of claim 6, wherein the target display interface comprises a second display interface and a third display interface, the target control comprising a first control and a second control;
responding to the triggering operation executed by the first control of the first display interface, displaying the second display interface, wherein the m target chips, the medium layer and the substrate are displayed in the second display interface, the medium layer is provided with contacts, the substrate is provided with contact pads which can be connected with the contacts,
connecting wires belonging to the same target netlist name and connecting wires of the contact and the contact pad are arranged between the pins of the m target chips and the pins of the n element modules in the interposer;
responding to the triggering operation executed by the second control of the first display interface, displaying the third display interface, wherein the third display interface displays the m target chips, an intermediate layer and a substrate, wherein the intermediate layer is provided with contacts, the substrate is provided with contact pads which can be connected with the contacts,
And connecting wires among the pins of the m target chips, which belong to the same target netlist name, and connecting wires of the contact points and the contact pads.
11. A wiring device, characterized by comprising:
the setting module is used for setting netlist names and wiring types of pins in n element modules in m target chips and an interposer on a first display interface, wherein m and n are integers larger than 1;
the wiring module is used for responding to the triggering operation executed by the target control in the first display interface and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface;
in the wiring diagram, wiring between pins of the m target chips and pins of n element modules in the interposer and wiring between pins of the m target chips are distinguished and displayed;
the wiring types include a first wiring type for characterizing wiring through the interposer and a second wiring type for characterizing wiring through the rewiring layer;
the target display interface comprises a second display interface and a third display interface, and the target control comprises a first control and a second control;
The responding to the triggering operation executed by the target control in the first display interface displays the wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface, and the method comprises the following steps:
the second display interface is displayed in response to the triggering operation executed by the first control in the first display interface, wherein the m target chips and the intermediary layer are displayed in the second display interface,
connecting wires which belong to the same target netlist name and belong to the same wiring type between the pins of the m target chips and the pins of the n element modules in the intermediate layer;
responding to the triggering operation executed by the second control in the first display interface, displaying a third display interface, the third display interface displaying the m target chips and the intermediary layer,
and connecting wires among the pins of the m target chips, which belong to the same target netlist name and the same wiring type.
12. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the wiring method according to any one of claims 1 to 10 when the computer program is executed.
13. A computer-readable storage medium storing a computer program, characterized in that the computer program realizes the steps of the wiring method according to any one of claims 1 to 10 when the computer program is executed by a processor.
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| CN116681010B (en) * | 2023-05-17 | 2023-12-22 | 珠海妙存科技有限公司 | Chip substrate netlist checking method, device, equipment and medium |
| CN116306469B (en) * | 2023-05-22 | 2023-08-01 | 深圳前海深蕾半导体有限公司 | Metal wiring method, device, equipment and storage medium for simulated layout |
| CN117574851B (en) * | 2024-01-11 | 2024-04-19 | 上海合见工业软件集团有限公司 | Method, device and storage medium for reconstructing circuit schematic diagram in EDA tool |
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