CN115688671A - Wiring method, device, terminal and storage medium - Google Patents
Wiring method, device, terminal and storage medium Download PDFInfo
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Abstract
The application discloses a wiring method, a wiring device, a terminal and a storage medium, wherein the method comprises the following steps: setting net list names and wiring types of pins in n element modules in m target chips and an intermediate layer on a first display interface, and responding to trigger operation executed by a target control in the first display interface, and displaying a wiring diagram generated according to the pin net list names and the wiring types on the target display interface. The invention determines the connection relation of each pin by automatically identifying the netlist name and the signal type of the pin, thereby directly displaying the corresponding wiring diagram on the target display interface based on the connection relation between the pins, realizing the automatic connection between the chip and the interposer and improving the wiring efficiency. In addition, different wiring diagrams are generated according to the netlist names and the signal types of the different pins by setting the netlist names and the signal types of the different pins, so that wiring between the chip and the interposer is clear, and user experience is improved.
Description
Technical Field
The present application relates to the field of EDA technologies, and in particular, to a wiring method, an apparatus, a terminal, and a storage medium.
Background
The chipset technology is to decompose Soc (System on Chip) into a plurality of smaller chiplets, wherein the chiplets can have different functions and processes, and then package the modularized chiplets together by using a novel packaging technology to realize interconnection of the chiplets, i.e. to form a heterogeneous integrated Chip.
In order to realize wide application of the chipset technology, the chipset technology is applied to EDA (Electronic design automation). In EDA based on chipset technology, there are usually multiple small chips, and pins between multiple chips need to be connected according to customer requirements to form heterogeneous integrated chips. In addition, the heterogeneous integrated chips also need to be connected with the active interposer and the substrate. Therefore, how to implement the wiring among the multiple chiplets, the active interposer, and the substrate is a problem to be solved.
At present, routing among a plurality of chiplets, active interposers, and substrates is mainly achieved manually, that is, an experienced routing worker manually connects the chiplets, the active interposers, and the substrates based on customer requirements.
However, the above method cannot achieve automatic wiring among a plurality of chiplets, active interposer, and substrate, which increases the cost of resources such as labor and time, and further increases the cost of resources.
Disclosure of Invention
The present application provides a wiring method, a device, a terminal and a storage medium, so as to solve the problem of high resource cost in the related art.
In order to achieve the above object, in a first aspect, the present application provides a wiring method including:
setting net list names and wiring types of pins in n element modules in m target chips and a middle layer on a first display interface, wherein m and n are integers larger than 1;
responding to a trigger operation executed by a target control in a first display interface, and displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface;
in the wiring diagram, the wiring among the pins of the m target chips and the pins of the n component modules in the interposer and the wiring among the pins of the m target chips are displayed in a differentiated manner.
In one possible implementation, the setting, in the first display interface, netlist names and wiring types of pins in n component modules in m target chips and interposers includes:
in response to a trigger operation executed on any pin of the m target chips and the n element modules in the interposer, displaying a pin setting window in a floating manner on the first display interface;
in response to a trigger operation executed for a netlist name and a wiring type in a pin setting window displayed in a floating mode on the first display interface, displaying a netlist name input box or a netlist name list and a wiring type list in the pin setting window;
in response to an input operation executed for the netlist name input box or a selection operation executed for a netlist name list and a selection operation executed for a routing type list, displaying a target netlist name identification corresponding to the target netlist name at any pin in the first display interface;
and in response to the selection operation of the cursor on any target pin which displays the target netlist name identification, and in response to the selection operation of the cursor on a pin which needs to be connected with the target pin, the pin selected by the cursor displays the target netlist name identification which is the same as the target pin and is defined as the netlist name and the wiring type which are the same as the target pin.
In one possible implementation, the routing types include a first routing type and a second routing type, the first routing type characterizing routing through the interposer, and the second routing type characterizing routing through the redistribution layer.
In one possible implementation manner, in response to the operation of selecting the wiring type executed aiming at the wiring type list, the pin setting window displays a pin signal type list; the pin signal types include: the device comprises a digital signal, an analog signal and a power supply signal, wherein the type of the pin signal is selected by clicking a cursor.
In one possible implementation manner, in response to an operation of selecting a first wiring type performed on the wiring type list and an operation of selecting a digital signal performed on a pin signal type, a driving pin is selected from pins with the same netlist name, and a window is set in the pin of the driving pin to select a driving control.
In one possible implementation, the first display interface further includes a tool menu bar;
in response to a selection operation performed by a cursor for any tool in the tool menu, displaying a view of the any tool at the cursor;
responding to the cursor moving to any pin in the m target chips and the n element modules in the interposer;
and displaying the corresponding identification of any tool at any pin in response to the trigger operation executed for any pin.
In one possible implementation, the tool menu includes at least passive electronic components or contacts.
In one possible implementation manner, after displaying, at the any pin, an identifier corresponding to the any tool in response to the triggering operation performed on the any pin, the method further includes:
under the condition that any tool is the contact, in response to a trigger operation executed for the identifier corresponding to the contact displayed at any pin, displaying a contact setting window in a floating mode on the first display interface;
and responding to a selection operation executed aiming at the contact name list in the contact setting window, and displaying the names of the contacts, wherein the names of the contacts correspond to the names of the contacts on the intermediate layer on the target display interface one by one.
In one possible implementation manner, the target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control;
the step of displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface in response to the trigger operation executed by the target control in the first display interface comprises the following steps:
displaying the second display interface in response to a trigger operation executed by the first control in the first display interface, wherein the m target chips and the interposer are displayed in the second display interface,
connecting lines which belong to the same target netlist name are arranged between the pins of the m target chips and the pins of the n element modules in the interposer;
responding to a trigger operation executed by a second control in the first display interface, and displaying a third display interface, wherein the third display interface displays the m target chips and the intermediate layer,
and connecting lines among the pins of the m target chips, which belong to the same target netlist name.
In one possible implementation manner, the target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control;
the step of displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface in response to the trigger operation executed by the target control in the first display interface comprises the following steps:
displaying the second display interface in response to a trigger operation executed by the first control in the first display interface, wherein the m target chips and the interposer are displayed in the second display interface,
connecting lines which belong to the same target netlist name and the same wiring type are arranged between the pins of the m target chips and the pins of the n element modules in the interposer;
responding to a trigger operation executed by a second control in the first display interface, and displaying a third display interface, wherein the third display interface displays the m target chips and the intermediate layer,
and connecting lines which belong to the same target netlist name and the same wiring type are arranged among the pins of the m target chips.
In one possible implementation, the method further includes:
in response to a triggering operation executed by a first control in a second display interface, displaying the m target chips and the interposer in the second display interface, and connecting lines, which belong to the same target netlist name and belong to a first routing type, between pins of the m target chips and pins of n element modules in the interposer;
in response to a triggering operation executed by a second control in a second display interface, displaying the m target chips and the interposer in the second display interface, and connecting lines, which belong to the same target netlist name and belong to a second routing type, between pins of the m target chips and pins of n element modules in the interposer;
in response to a trigger operation executed by a first control in a third display interface, displaying the m target chips, the interposer and connecting lines, which belong to the same target netlist name and a first wiring type, among pins of the m target chips in the third display interface;
and in response to a triggering operation executed by a second control in a third display interface, displaying the m target chips, the intermediate layer and connecting lines, which belong to the same target netlist name and a second wiring type, among pins of the m target chips in the third display interface.
In one possible implementation manner, the target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control;
displaying the second display interface in response to a trigger operation performed by the first control of the first display interface, wherein the m target chips, an interposer and a substrate are displayed in the second display interface, wherein joints are displayed on the interposer, and joint pads capable of being connected to the joints are displayed on the substrate,
connecting lines which belong to the same target netlist name and are arranged between the pins of the m target chips and the pins of the n element modules in the interposer, and connecting lines between the joints and the joint pads;
displaying the third display interface in response to a trigger operation performed by the second control of the first display interface, wherein the third display interface displays the m target chips, an interposer and a substrate, wherein contacts are displayed on the interposer and contact pads connectable with the contacts are displayed on the substrate,
and connecting lines among the pins of the m target chips, which belong to the same target netlist name, and connecting lines of the contact and the contact pad.
In a second aspect, an embodiment of the present invention provides a wiring device, including:
the device comprises a setting module, a setting module and a control module, wherein the setting module is used for setting net list names and wiring types of pins in n element modules in m target chips and a middle layer on a first display interface, and m and n are integers larger than 1;
the wiring module is used for responding to triggering operation executed by a target control in the first display interface and displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface;
in the wiring diagram, the wirings between the pins of the m target chips and the pins of the n component modules in the interposer and the wirings between the pins of the m target chips are distinguished and displayed.
In a third aspect, an embodiment of the present invention provides a terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of any one of the above wiring methods when executing the computer program.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above wiring methods are implemented.
The embodiment of the invention provides a wiring method, a wiring device, a terminal and a storage medium, wherein the wiring method comprises the following steps: the method comprises the steps of firstly setting net list names and wiring types of pins in n element modules in m target chips and an intermediate layer on a first display interface, and responding to trigger operation executed by a target control in the first display interface to display a wiring diagram generated according to the pin net list names and the wiring types on the target display interface. The invention determines the connection relation of each pin by automatically identifying the netlist name and the signal type of the pin, thereby directly displaying the corresponding wiring diagram on the target display interface based on the connection relation between the pins, realizing the automatic connection between the chip and the interposer and improving the wiring efficiency. In addition, different wiring diagrams are generated according to the netlist names and the signal types of the different pins by setting the netlist names and the signal types of the different pins, and a connecting line between the chip and the interposer and a connecting line between the chip and the chip are distinguished and displayed, so that the wiring between the chip and the interposer is clear, and the user experience is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, serve to provide a further understanding of the application and to enable other features, objects, and advantages of the application to be more apparent. The drawings and their description illustrate the embodiments of the invention and do not limit it. In the drawings:
fig. 1 is a flowchart of an implementation of a wiring method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a first display interface provided by an embodiment of the invention;
FIG. 3 is a diagram illustrating a pin setup window according to an embodiment of the invention;
FIG. 4 is a diagram illustrating a pin setup window according to another embodiment of the present invention;
FIG. 5 is a diagram illustrating a pin setup window according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a chiplet U12 provided in accordance with an embodiment of the present invention;
FIG. 7 is a diagram of a tool menu bar provided by an embodiment of the present invention;
FIG. 8 is a diagram illustrating a resistance value setting window according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a chiplet U12 provided in accordance with another embodiment of the present invention;
fig. 10 is a schematic view of a contact placement window provided in accordance with an embodiment of the present invention;
FIG. 11 is a diagram illustrating a contact name list provided by an embodiment of the invention;
fig. 12 is a schematic view of a contact placement window according to another embodiment of the present invention;
FIG. 13 is a diagram illustrating a second display interface provided in accordance with an embodiment of the present invention;
FIG. 14 is another schematic diagram of a second display interface provided in accordance with an embodiment of the invention;
FIG. 15 is a diagram illustrating a third display interface provided by an embodiment of the invention;
FIG. 16 is a schematic diagram of a second display interface provided in accordance with another embodiment of the present invention;
FIG. 17 is a schematic diagram of a third display interface provided in accordance with another embodiment of the invention;
fig. 18 is a schematic diagram of a wiring switching button provided by an embodiment of the present invention;
fig. 19 is a schematic structural diagram of a wiring device according to an embodiment of the present invention;
fig. 20 is a schematic diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.
It should be understood that, in various embodiments of the present invention, the sequence numbers of the processes do not mean the execution sequence, and the execution sequence of the processes should be determined by the functions and the internal logic of the processes, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
It should be understood that in the present application, "comprising" and "having" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that, in the present invention, "a plurality" means two or more. "and/or" is merely an association describing an associated object, meaning that three relationships may exist, for example, and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "comprises A, B and C" and "comprises A, B, C" means that all three of A, B, C comprise, "comprises A, B or C" means that one of three of A, B, C is comprised, "comprises A, B and/or C" means that any 1 or any 2 or 3 of the three of A, B, C is comprised.
It should be understood that in the present invention, "B corresponding to a", "a corresponds to B", or "B corresponds to a" means that B is associated with a, and B can be determined from a. Determining B from a does not mean determining B from a alone, but may be determined from a and/or other information. And the matching of A and B means that the similarity of A and B is greater than or equal to a preset threshold value.
As used herein, "if" can be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on context.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description is made by way of specific embodiments with reference to the accompanying drawings.
In one embodiment, as shown in fig. 1, there is provided a wiring method comprising the steps of:
step S101: and setting net list names and wiring types of pins in the n element modules in the m target chips and the intermediate layers on the first display interface.
The target chip can be any chip, and can be selected according to the requirements of customers, such as a sensor chip, a power supply chip and the like. The component modules in the interposer are preset, wherein the component modules are set based on the type of the interposer, and the component modules may include any electronic device, circuit, and a combination thereof, wherein the electronic device may be an amplifier device, a power chip, an MCU, or the like.
Wherein m and n are integers more than 1.
As shown in fig. 2, the first display interface 21 displays an interposer 22 and 2 target chips, wherein the interposer 22 has 2 component modules S4 and S5, respectively, and the target chips on the right side of the interposer 22 are U12 and U15, respectively.
As can be seen from fig. 2, whether the component module on the interposer 22 or part of the pins of the target chip on the right side thereof need to be set according to customer requirements, the set items include netlist names, routing types, and Extended Tiles of the pins. The setting operation method for the pins in the n component modules in the m target chips and the interposer is the same.
Further, the operations performed for setting the netlist names and the wiring types of the pins in the m target chips and the n component modules in the interposer on the first display interface mainly include: the method comprises the steps of firstly responding to a trigger operation executed aiming at any pin in m target chips and n element modules in a middle layer, displaying a pin setting window in a first display interface in a floating mode, then responding to the trigger operation executed aiming at a net list name and a wiring type in the pin setting window displayed in the first display interface in the floating mode, displaying a net list name input box or a net list name list and a wiring type list in the pin setting window, responding to an input operation executed aiming at the net list name input box or a selection operation executed by the net list name list and a selection operation executed by the wiring type list, and displaying a target net list name identification corresponding to the target net list name at any pin in the first display interface.
Wherein the wiring types include: the routing module comprises a first routing type and a second routing type, wherein the first routing type is used for representing that routing is carried out through an interposer, and the second routing type is used for representing that routing is carried out through a rewiring layer. Optionally, the routing types may also include a third routing type, the third routing type being used to characterize routing through the redistribution layer and/or the interposer.
And after the wiring type corresponding to the pin is selected, the pin signal types corresponding to different wiring types can be selected. After the selection operation executed according to the input operation executed aiming at the netlist name input box or the netlist name list and the selection operation executed according to the wiring type list in the steps are performed, and then the operation executed according to the wiring type is selected according to the wiring type list, and the pin signal type list is displayed by the pin setting window; the pin signal types include: digital signals, analog signals and power signals, wherein the pin signal type is selected by cursor clicking.
In one possible implementation manner, in response to an operation of selecting a first wiring type or a third wiring type performed on the wiring type list and an operation of selecting a digital signal performed by the pin signal type, a driving pin is selected from pins with the same netlist name, and a window is set for the pin of the driving pin to hook up a driving control.
Specifically, as shown in fig. 3, when a C3 pin on the chip U12 is clicked, a pin setting window is displayed in a floating manner on the chip U12, wherein the pin setting window includes three frames, a frame on the left side is a netlist name input frame or a netlist name list, and the netlist name setting of the pin C3 can be realized by inputting a netlist name (e.g., enter Netname shown in fig. 3) into the netlist name input frame. In addition, the upper left box can also be a netlist name list, and the netlist name setting of the pin C3 is realized by selecting any netlist name in the netlist name list.
The right frame in the pin setting window is mainly used for setting the wiring type of the pin, for the pin which is not set by the wiring type, unassigned is displayed in the frame, and after the Unassigned is clicked, a wiring type list is directly displayed, wherein the wiring type list comprises three wiring types, namely a first wiring type (Programmable), a second wiring type (Metal Only) and a third wiring type (Metal Programmable). By clicking any wiring type, the setting of the wiring type of the pin C3 can be realized. Alternatively, the wiring type list may include Only two wiring types, i.e., a first wiring type (Programmable) and a second wiring type (Metal Only).
Referring to fig. 4, after the wiring type of the pin C3 is set to the first wiring type (Programmable), the pin signal types corresponding to the Programmable, that is, the Digital signal (Digital), the Analog signal (Analog), and the Power signal (Power), can be displayed by clicking the Programmable.
Through the method, the netlist name of the pin C3 is set to be U12_ DEC3, after the wiring type is set to be Programmable, a confirmation key in the pin setting window is clicked, wherein the confirmation key can be represented by Save, ok and the like, and then the pin setting window is hidden or retracted. Accordingly, the identification corresponding to the netlist name, i.e., U12_ DEC3, is displayed at pin C3. U12_ DEC3 is displayed by a preset highlight color, wherein the highlight color can be defined by a customer or can be selected through a color setting menu.
With reference to fig. 2 and 6, after the netlist name and the wiring type of the pin C3 are set, in response to the selection operation of the cursor for the target pin C3, and in response to the selection operation of the cursor for the remaining pins, for example, the D2 pin on the U15 chip, the D2 pin to be connected with the pin C3 is selected; the selected pin displays the same netlist name as pin C3 and displays the same highlight color as pin C3, at which time the D2 pin has been defined to be the same netlist name and wiring type as C3.
With reference to fig. 5, if the C3 wiring type is the first wiring type (Programmable) or the third wiring type (metal Programmable), and the signal type is selected as the Digital signal type, it is necessary to select one of the two pins with the same netlist name, i.e., the pin C3 and the pin D2, as a driving pin, and select a driving control (driver) in the three controls at the bottom right corner. This is because the digital signal lines need to be routed through the interposer, with the drive-side pins selected.
With reference to fig. 5, if the C3 wiring type is the second wiring type (metal Programmable) or the third wiring type (metal only), the flying lead control (implementation tile) in the three controls at the lower right corner can be selected, the target display interface can display the flying leads between the pins wired by the redistribution layer, and when the target display interface needs to edit the pin connection line wired by the redistribution layer, the pins with the same netlist name can be identified by the flying leads between the pins.
In addition, the lower left frame in the pin setting window is Extended Tiles.
The first display interface in the present application further includes a tool menu bar, that is, the a area, the B area, and the C area in fig. 2, wherein the a area, the B area, and the C area can set various setting items in each area according to a user's requirement. Note that the setting items in the respective areas are not repeatable.
Referring to fig. 7, an example of a tool menu bar disposed in the area a is shown, in which the Tool (TOOLS) menu bar includes, from left to right, a passive electronic component, a contact (BONDPAD), a print button, and a pull-back operation button.
In the case that a Tool (TOOLS) menu bar includes a resistor and a contact (BONDPAD), a view of any tool is displayed at a cursor in response to a selection operation performed by the cursor for any tool in a tool menu, and then a mark corresponding to any tool is displayed at any pin in response to the cursor moving to any pin in the m target chips and the n element modules in the interposer and then in response to a trigger operation performed for any pin.
When any tool is a resistor, by clicking the resistor icon shown in fig. 7, the resistor icon is displayed at the cursor, and simultaneously popping up the resistor resistance value setting window shown in fig. 8, after 10000 (i.e., 10 k) is input, the cursor is moved to the pin D2 of the chip U12, and it can be seen that a resistor with a resistance value of 10k is connected to the pin D2 shown in fig. 9, and the resistor icon and the identifier RN _1 are displayed.
When any tool is a BONDPAD, by clicking the icon of the BONDPAD shown in FIG. 6, the icon of the BONDPAD is displayed at the cursor, and the icon of the BONDPAD is directly moved to the pin B4 of the chip U12, so that it can be seen that a BONDPAD is connected to the pin B4 shown in FIG. 9, and the icon of the BONDPAD and the identifier BONDPAD _2 are displayed.
After the BONDPAD is set on the corresponding pin in the above manner, when the target display interface is jumped to, the previously set BONDPAD and the name corresponding to the BONDPAD are displayed on the interposer displayed in the target display interface. Therefore, the name corresponding to the BONDPAD needs to be set on the first display interface, and the specific implementation manner is as follows: and in response to a trigger operation executed aiming at the identifier corresponding to the contact displayed at any pin, displaying a contact setting window in a floating mode on the first display interface, and then in response to a selection operation executed aiming at a contact name list in the contact setting window, displaying the names of the contacts, wherein the names of the contacts correspond to the names of the contacts on the interposer on the target display interface one by one.
Through the above operation, a BONDPAD is connected to the pin B4 shown in FIG. 9, and an icon and an identifier BONDPAD _2 of the BONDPAD are displayed. Then, clicking on BONDPAD at B4 pops up a contact setup window as shown in FIG. 10, and clicking on the contact setup window displays a contact name list as shown in FIG. 11, where a plurality of contact names, such as Padio _ I _0/12, padio _ I _1/20, padio _ I _2/28, etc., are displayed in the contact name list. The corresponding contact name is selected by clicking on the box in front of the contact name. When the box in front of Padio _ I _4/44 is clicked, the contact name list is hidden or collapsed, and then Padio _ I _4/44 is displayed in the contact setting window as shown in fig. 12. And finally, clicking a confirmation button Save.
Step S102: and in response to the triggering operation executed by the target control in the first display interface, displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface.
In the wiring diagram, the wiring between the pins of the m target chips and the pins of the n component modules in the interposer and the wiring between the pins of the m target chips are displayed in a differentiated manner.
The target display interface comprises a second display interface and a third display interface, the target control comprises a first control and a second control, and the first control and the second control can be controls arranged in any area of an area A, an area B and an area C in the first display interface shown in fig. 2.
Based on the distinction between the wirings between the pins of the m target chips and the pins of the n element modules in the interposer (hereinafter, may be simply referred to as "inter-chip interconnection wirings"), and the wirings between the pins of the m target chips (hereinafter, may be simply referred to as "inter-chip wirings"), the differently distinguished wirings may be displayed in different display interfaces. For example, interchip wiring may be displayed in the second display interface and interchip wiring may be displayed in the third display interface.
The second display interface is used for displaying connecting lines which belong to the same target netlist name and are between the pins of the m target chips and the pins of the n element modules in the intermediate layer. The specific implementation steps are as follows: and responding to the triggering operation executed by the first control in the first display interface, displaying the second display interface, wherein,
and the second display interface displays m target chips and the intermediate layer, and connecting lines which belong to the same target netlist name are arranged between the pins of the m target chips and the pins of the n element modules in the intermediate layer.
Illustratively, clicking a first control arranged in the first display interface, and jumping to the second display interface. As shown in fig. 13, a chip layer 1201 (including a chip U15) and an interposer 1202 are sequentially displayed on the second display interface from top to bottom, where a pin C2 of the device module S4 in the interposer and a pin A1 of the chip U15 belong to the same netlist name (e.g., GPIO 0), and a connection line between the pin C2 and the pin A1 is displayed on the interposer 1202. In addition, pin C1 of component module S4 in the interposer belongs to the same netlist name (e.g., GPIO 1) as pin A3 of chip U15, and then the connection line between pin C1 and pin A3 is shown in interposer 1202.
According to the above example, further, a menu bar may be further disposed on the right side of the second display interface, and a route view button is disposed in the menu bar; clicking a first control arranged in a first display interface, jumping to a second display interface, and only displaying a chip layer 1201 and a middle layer 1202 at the moment, wherein connecting lines among pins are not displayed; responding to a cursor connection operation for the pins C1 and A3 and the pins C2 and A1, or responding to a trigger operation executed for a routing view button in a menu bar in the second display interface; the pin C1 and the pin A3 and the pin C2 and the pin A1 are connected by a connection line.
Optionally, as shown in fig. 14, an area 12021 may be further disposed on the interposer 1202, and the area 12021 is connected to the component module in the interposer 1202. Connection to the component module in the interposer 1202 can be achieved by routing to the area 12021 on the interposer 1202 when the target chip needs to be connected to the component module in the interposer 1202. If pin A1 of the chip U15 needs to be connected to pin C2 of the component module S4, then pin A1 can be routed to area 12021, and area 12021 is in communication with pin C2 of the component module S4 in the interposer 1202.
And the third display interface is used for displaying connecting lines among the pins of the m target chips, which belong to the same target netlist name. The specific execution steps are as follows: and responding to a triggering operation executed by a first control in the first display interface, and displaying a third display interface, wherein m target chips and a medium layer are displayed in the third display interface, and connecting lines which belong to the same target netlist name are arranged among pins of the m target chips.
Illustratively, clicking a second control arranged in the first display interface jumps to a third display interface. As shown in fig. 15, a chip layer 1201 (including a chip U12 and a chip U15) and an interposer 1202 are sequentially displayed in the third display interface from top to bottom, where a pin C3 of the chip U12 and a pin A2 of the chip U15 belong to the same netlist name (e.g., I2C0_ SDA), and then a connection relationship between the pin C3 and the pin A2 is displayed on the interposer 1202. In addition, pin C1 of the chip U12 and pin A3 of the chip U15 belong to the same netlist name (e.g., I3C1_ SDA), and the connection relationship between pin C1 and pin A3 is shown.
Optionally, the second display interface may also be configured to display connecting lines, which belong to the same target netlist name and to the same wiring type, between the pins of the m target chips and the pins of the n component modules in the interposer, that is, to control display of the connecting lines according to the wiring type, for example, only the connecting lines of the first wiring type or only the connecting lines of the second wiring type are displayed.
Further, in the second display interface, a first control and a second control may be further provided, and the wiring type of the displayed connecting line is controlled through the first control and the second control. For example, when the first control in the second display interface is triggered, only the connecting lines belonging to the same target netlist name and the first wiring type between the pins of the m target chips and the pins of the n component modules in the interposer may be displayed in the second display interface, and when the second control in the second display interface is triggered, only the connecting lines belonging to the same target netlist name and the second wiring type between the pins of the m target chips and the pins of the n component modules in the interposer may be displayed in the second display interface.
Optionally, the third display interface may also be configured to display connecting lines between pins of the m target chips, which belong to the same target netlist name and are of the same wiring type, that is, to control display of the connecting lines according to the wiring type, for example, only the connecting lines of the first wiring type or only the connecting lines of the second wiring type are displayed.
Further, in the third display interface, a first control and a second control may be further provided, and the wiring type of the displayed connecting line is controlled through the first control and the second control. For example, when the first control in the third display interface is triggered, only the connecting lines belonging to the same target netlist name and the first wiring type among the pins of the m target chips may be displayed in the third display interface, and when the second control in the third display interface is triggered, only the connecting lines belonging to the same target netlist name and the second wiring type among the pins of the m target chips may be displayed in the third display interface.
In the embodiment of the invention, the connection relationship between the pins and the external bonding pads can be set and displayed in the interface.
As shown in fig. 16, a chip layer 1201 (including a chip U15), an interposer 1202, a component module S4 in the interposer 1202, and a substrate 1205 may be displayed in the second display interface, wherein the chip layer 1201, the interposer 1202, the component module S4 in the interposer 1202, and the substrate 1205 are arranged in sequence from top to bottom, contact pads 1204 are uniformly arranged on the periphery of the substrate 1205, each contact pad 1204 corresponds to a respective code, and the number and the arrangement of the contact pads in fig. 15 are only examples. In addition to the pin connection relationship of fig. 13, the following pad connection relationship is also provided: the contacts 11 on the interposer 1202 are connected to the contact pads 21 on the substrate 1205, and the contacts 13 on the interposer 1202 are connected to the contact pads 23 on the substrate 1205. At this time, the connection lines between the contact 11 on the interposer 1202 and the contact pad 21 on the substrate 1205, and the connection lines between the contact 13 on the interposer 1202 and the contact pad 23 on the substrate 1205 are displayed in the second display interface. If the leads A1, C2 are configured to connect to contacts 11 on the interposer 1202, the leads A1, C2 will be able to connect to the outside of the chip via contact pads 21.
As shown in fig. 17, a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202, and a substrate 1205 may be displayed in the third display interface, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 16 are only examples. In addition to the pin connection relationship of fig. 14, the following pad connection relationship is also provided: the contacts 11 on the interposer 1202 are connected to the contact pads 21 on the substrate 1205, and the contacts 13 on the interposer 1202 are connected to the contact pads 23 on the substrate 1205. At this time, the connection lines between the contact 11 on the interposer 1202 and the contact pad 21 on the substrate 1205, and the connection lines between the contact 13 on the interposer 1202 and the contact pad 23 on the substrate 1205 are displayed in the third display interface. If pins A2, C3 are provided to connect with contacts 11 on interposer 1202, pins A2, C3 will be able to connect to the outside of the chip through contact pads 21.
In the embodiment of the invention, a menu bar can be arranged on the right side of the third display interface, and an edit list is arranged on the menu bar; and (3) checking a flying wire control (EnforceTilemap) in three controls of a pin C3 and a pin C1 in a lower right corner of a window on a first display interface, clicking a second control arranged in the first display interface, and jumping to a third display interface, wherein the third display interface can display flying wires between the pin C3 and the pin A2 as well as between the pin C1 and the pin A3, and when a target display interface needs to edit connecting wires between the pin C3 and the pin A2 as well as between the pin C1 and the pin A3, pins with the same net list name can be identified through the flying wires between the pins. Selecting editable options in an edit list in a menu bar in a third display interface; connecting lines are formed by connecting the cursor between the pin C3 and the pin A2 and between the pin C1 and the pin A3, or by clicking an automatic connecting line button in a menu bar in the third display interface, connecting lines between the pin C3 and the pin A2 and between the pin C1 and the pin A3 are formed.
Note that, the four sides of the periphery of the interposer 1202 are uniformly distributed with connection pads (BONDPADs) 1203, and each BONDPAD is labeled with its own code. Among these, the BONDPAD shown in fig. 13, 14, and 15 is merely an example.
In addition, the first display interface, the second display interface and the third display interface can be jumped or switched through the first interface control, the second interface control and the third interface control. The first interface control can be a "schema View" button, the second interface control can be represented by an "Optimize" button and the like, and the third interface control can be represented by a "Package View" button and the like. The buttons corresponding to the three interface controls are only examples, and may be represented by other identifiers.
Because the menu bars above the first display interface, the second display interface and the third display interface all comprise the three interface controls, the corresponding display interface is automatically jumped to by clicking any one of the three interface controls. The first display interface is set to display m target chips and intermediate layers at present, and connecting lines belonging to the same target netlist name pin on the m target chips and the intermediate layers.
In addition, the target display interface of the present application may be only one, that is, the second display interface and the third display interface are both displayed on one interface, and the views are switched by arranging a first routing button, a second routing button and a third routing button in a toolbar on the right side of the target display interface, wherein the first routing button, the second routing button and the third routing button may be arranged as routing switching buttons (wires) as shown in fig. 18.
The embodiment of the invention provides a wiring method, which comprises the following steps: the method comprises the steps of firstly setting net list names and wiring types of pins in n element modules in m target chips and an intermediate layer on a first display interface, and responding to trigger operation executed by a target control in the first display interface to display a wiring diagram generated according to the pin net list names and the wiring types on the target display interface. The invention determines the connection relation of each pin by automatically identifying the netlist name and the signal type of the pin, thereby directly displaying the corresponding wiring diagram on the target display interface based on the connection relation between the pins, realizing the automatic connection between the chip and the interposer and improving the wiring efficiency. In addition, different wiring diagrams are generated according to the netlist names and the signal types of the different pins by setting the netlist names and the signal types of the different pins, so that wiring between the chip and the interposer is clear, and user experience is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The following are embodiments of the apparatus of the invention, reference being made to the corresponding method embodiments described above for details which are not described in detail therein.
Fig. 19 is a schematic structural diagram of a wiring device according to an embodiment of the present invention, which only shows portions related to the embodiment of the present invention for convenience of description, and the wiring device includes a setting module 1801 and a wiring module 1802, specifically as follows:
a setting module 1801, configured to set, on a first display interface, netlist names and wiring types of pins in n component modules in m target chips and a interposer, where m and n are integers greater than 1;
a wiring module 1802, configured to display, on a target display interface, a wiring diagram generated according to the pin netlist name and the wiring type in response to a trigger operation executed by a target control in the first display interface;
in the wiring diagram, the wirings between the pins of the m target chips and the pins of the n component modules in the interposer and the wirings between the pins of the m target chips are distinguished and displayed.
For the specific description of the wiring device, reference may be made to the specific description of the wiring method, and details are not repeated one by one in order to avoid repetition.
Fig. 20 is a schematic diagram of a terminal according to an embodiment of the present invention. As shown in fig. 20, the terminal 19 of this embodiment includes: a processor 1901, a memory 1902, and a computer program 1903 stored in the memory 1902 and executable on the processor 1901. The processor 1901, when executing the computer program 1903, implements the steps in the various routing method embodiments described above, such as steps 101 through 102 shown in fig. 1. Alternatively, the processor 1901, when executing the computer program 1903, implements the functionality of the various modules/units in the wiring device embodiments described above, such as the modules/units 1801 to 1802 shown in fig. 19.
The invention also provides a readable storage medium, wherein a computer program is stored in the readable storage medium, and the computer program is used for realizing the wiring method provided by the various embodiments described above when being executed by a processor.
The readable storage medium may be a computer storage medium or a communication medium. Communication media includes any medium that facilitates transfer of a computer program from one place to another. Computer storage media may be any available media that can be accessed by a general purpose or special purpose computer. For example, a readable storage medium is coupled to the processor such that the processor can read information from, and write information to, the readable storage medium. Of course, the readable storage medium may also be an integral part of the processor. The processor and the readable storage medium may reside in an Application Specific Integrated Circuits (ASIC). Additionally, the ASIC may reside in user equipment. Of course, the processor and the readable storage medium may also reside as discrete components in a communication device. The readable storage medium may be a read-only memory (ROM), a random-access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
The present invention also provides a program product comprising execution instructions stored in a readable storage medium. The at least one processor of the device may read the execution instructions from the readable storage medium, and the execution of the execution instructions by the at least one processor causes the device to implement the wiring method provided by the various embodiments described above.
In the above embodiments of the apparatus, it is understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (15)
1. A wiring method, characterized by comprising:
setting net list names and wiring types of pins in n element modules in m target chips and a middle layer on a first display interface, wherein m and n are integers larger than 1;
responding to a trigger operation executed by a target control in a first display interface, and displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface;
in the wiring diagram, the wirings between the pins of the m target chips and the pins of the n component modules in the interposer and the wirings between the pins of the m target chips are distinguished and displayed.
2. The routing method according to claim 1, wherein the setting of the netlist names and the routing types of the pins in the n component modules in the m target chips and the interposer on the first display interface comprises:
in response to a trigger operation executed on any pin of the m target chips and the n element modules in the interposer, displaying a pin setting window in a floating manner on the first display interface;
in response to a trigger operation executed for a netlist name and a wiring type in a pin setting window displayed in a floating mode on the first display interface, displaying a netlist name input box or a netlist name list and a wiring type list in the pin setting window;
in response to an input operation executed for the netlist name input box or a selection operation executed for a netlist name list and a selection operation executed for a routing type list, displaying a target netlist name identification corresponding to the target netlist name at any pin in the first display interface;
and in response to the selection operation of the cursor for any target pin which displays the target netlist name identification, and in response to the selection operation of the cursor for a pin which needs to be connected with the target pin, the pin selected by the cursor displays the target netlist name identification which is the same as the target pin and is defined as the netlist name and the wiring type which are the same as the target pin.
3. The routing method of claim 1 or 2, wherein the routing types include a first routing type characterizing routing through an interposer and a second routing type characterizing routing through a re-routing layer.
4. The wiring method according to claim 3, wherein in response to an operation of selecting a wiring type performed for the wiring type list, the pin setting window displays a pin signal type list; the pin signal types include: the device comprises a digital signal, an analog signal and a power supply signal, wherein the type of the pin signal is selected by clicking a cursor.
5. The wiring method according to claim 4, wherein in response to an operation of selecting a first wiring type performed for the wiring type list and an operation of selecting a digital signal performed for a pin signal type, a driving pin is selected among pins of the same netlist name, and a window is set at a pin of the driving pin to hook a driving control.
6. The wiring method as recited in claim 1, wherein said first display interface further comprises a tool menu bar;
in response to a selection operation performed by a cursor for any tool in the tool menu, displaying a view of the any tool at the cursor;
responding to the cursor moving to any pin in the m target chips and the n element modules in the interposer;
and displaying the corresponding identification of any tool at any pin in response to the trigger operation executed for any pin.
7. The wiring method of claim 6 wherein said tool menu includes at least passive electronic components or contacts.
8. The routing method according to claim 7, wherein the responding to the triggering operation executed for the any pin, after displaying the corresponding identifier of the any tool at the any pin, further comprises:
under the condition that any tool is the contact, in response to a trigger operation executed for the identifier corresponding to the contact displayed at any pin, displaying a contact setting window in a floating mode on the first display interface;
and responding to a selection operation executed aiming at the contact name list in the contact setting window, and displaying the names of the contacts, wherein the names of the contacts correspond to the names of the contacts on the intermediate layer on the target display interface one by one.
9. The routing method of claim 1, wherein the target display interface comprises a second display interface and a third display interface, and the target control comprises a first control and a second control;
the step of displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface in response to the trigger operation executed by the target control in the first display interface comprises the following steps:
displaying the second display interface in response to a trigger operation executed by the first control in the first display interface, wherein the m target chips and the interposer are displayed in the second display interface,
connecting lines which belong to the same target netlist name are arranged between the pins of the m target chips and the pins of the n element modules in the interposer;
responding to a trigger operation executed by a second control in the first display interface, and displaying a third display interface, wherein the third display interface displays the m target chips and the intermediate layer,
and connecting lines among the pins of the m target chips, which belong to the same target netlist name.
10. The routing method of claim 3, wherein the target display interface comprises a second display interface and a third display interface, the target control comprises a first control and a second control;
the step of displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface in response to the trigger operation executed by the target control in the first display interface comprises the following steps:
displaying the second display interface in response to a trigger operation executed by the first control in the first display interface, wherein the m target chips and the interposer are displayed in the second display interface,
connecting lines which belong to the same target netlist name and the same wiring type are arranged between the pins of the m target chips and the pins of the n element modules in the interposer;
responding to a trigger operation executed by a second control in the first display interface, and displaying a third display interface, wherein the third display interface displays the m target chips and the intermediate layer,
and connecting lines which belong to the same target netlist name and the same wiring type are arranged among the pins of the m target chips.
11. The wiring method of claim 10, wherein the method further comprises:
in response to a triggering operation executed by a first control in a second display interface, displaying the m target chips and the interposer in the second display interface, and connecting lines, which belong to the same target netlist name and belong to a first routing type, between pins of the m target chips and pins of n element modules in the interposer;
in response to a triggering operation executed by a second control in a second display interface, displaying the m target chips and the interposer in the second display interface, and connecting lines, which belong to the same target netlist name and belong to a second routing type, between pins of the m target chips and pins of n element modules in the interposer;
in response to a trigger operation executed by a first control in a third display interface, displaying the m target chips, the interposer and connecting lines, which belong to the same target netlist name and a first wiring type, among pins of the m target chips in the third display interface;
and in response to a triggering operation executed by a second control in a third display interface, displaying the m target chips, the intermediate layer and connecting lines, which belong to the same target netlist name and a second wiring type, among pins of the m target chips in the third display interface.
12. The routing method of claim 8, wherein the target display interface comprises a second display interface and a third display interface, and the target control comprises a first control and a second control;
displaying the second display interface in response to a trigger operation executed by the first control of the first display interface, wherein the m target chips, an interposer and a substrate are displayed in the second display interface, wherein contacts are displayed on the interposer, and contact pads connectable with the contacts are displayed on the substrate,
connecting lines which belong to the same target netlist name and are arranged between the pins of the m target chips and the pins of the n element modules in the interposer, and connecting lines between the joints and the joint pads;
displaying the third display interface in response to a trigger operation performed by the second control of the first display interface, wherein the third display interface displays the m target chips, an interposer and a substrate, wherein contacts are displayed on the interposer and contact pads connectable with the contacts are displayed on the substrate,
and connecting lines among the pins of the m target chips, which belong to the same target netlist name, and connecting lines of the contact and the contact pad.
13. A wiring device, comprising:
the device comprises a setting module, a setting module and a control module, wherein the setting module is used for setting net list names and wiring types of pins in n element modules in m target chips and a middle layer on a first display interface, and m and n are integers larger than 1;
the wiring module is used for responding to triggering operation executed by a target control in the first display interface and displaying a wiring diagram generated according to the pin netlist name and the wiring type on the target display interface;
in the wiring diagram, the wirings between the pins of the m target chips and the pins of the n component modules in the interposer and the wirings between the pins of the m target chips are distinguished and displayed.
14. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the steps of the wiring method according to any of claims 1 to 12 are implemented by the processor when executing the computer program.
15. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the wiring method according to any one of claims 1 to 12.
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| CN115688671B (en) | 2023-11-03 |
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