CN115688672B

CN115688672B - Display method, device, terminal and storage medium

Info

Publication number: CN115688672B
Application number: CN202211419988.6A
Authority: CN
Inventors: 许荣峰; 邵钏; 卢萧; 林哲民
Original assignee: Shanghai Chipler Chip Technology Co ltd; Shenzhen Qipule Chip Technology Co ltd
Current assignee: Shanghai Chipler Chip Technology Co ltd; Shenzhen Qipule Chip Technology Co ltd
Priority date: 2022-11-14
Filing date: 2022-11-14
Publication date: 2024-03-08
Anticipated expiration: 2042-11-14
Also published as: CN115688672A

Abstract

The application discloses a display method, a device, a terminal and a storage medium, wherein the method comprises the following steps: responding to the m target chips and the intermediary layer to be arranged in canvas of the first display interface; responding to a triggering operation executed for a first control in the first display interface, and displaying the m target chips and the interposer on a second display interface; and responding to the triggering operation executed for the target control in the second display interface, and displaying the wiring diagram on the target display interface. According to the invention, the position relation and the pin relation of the m target chips and the interposer are set through the first display interface and the second display interface in sequence, so that the automatic connection between the chips and the interposer is realized, and the wiring efficiency is improved. In addition, the invention also generates different wiring patterns according to the set pin relation, namely the netlist names and the signal types of the pins, so as to lead the wiring between the chip and the intermediary layer to be clear and improve the user experience.

Description

Display method, device, terminal and storage medium

Technical Field

The present application relates to the field of EDA technologies, and in particular, to a display method, device, terminal, and storage medium.

Background

Chiplet technology refers to decomposing a Soc (System on Chip) into a plurality of smaller chiplets, where the chiplets can have different functions and processes, and then packaging the modular chiplets together using a novel packaging technology to achieve interconnection of the chiplets, i.e., to form a heterogeneous integrated Chip.

To realize the wide application of the Chiplet technology, chiplet technology is applied to EDA (electronic design automation ). Currently, aiming at applying the Chiplet technology to EDA, operations such as small chip selection, placement, wiring and the like are mainly realized by manual operation, namely, experienced designers manually realize the operations such as small chip selection, placement, wiring and the like based on customer requirements.

However, the above-mentioned operations of applying the Chiplet technology to EDA cannot be automated, so that the cost of resources such as manpower and time increases, and the cost of resources is high.

Disclosure of Invention

The main objective of the present application is to provide a display method, a device, a terminal and a storage medium, so as to solve the problem of high resource cost in the related art.

In order to achieve the above object, in a first aspect, the present application provides a display method, including:

responding to the setting of m target chips and an intermediary layer in a canvas of a first display interface, wherein m is an integer greater than 1;

responding to a triggering operation executed for a first control in a first display interface, and displaying m target chips and an intermediary layer on a second display interface;

and responding to the triggering operation executed for the target control in the second display interface, and displaying a wiring diagram on the target display interface, wherein the wiring diagram is generated based on the netlist names and the wiring types of the pins corresponding to the m target chips and the interposer.

In one possible implementation, before the m target chips are set in the canvas of the first display interface, the method further includes:

for each target chip of the m target chips, responding to a selection operation executed for the chip name in the chip selection list in the toolbar in the first display interface, and acquiring the target chip;

responding to a first interaction event of a cursor, and displaying an angle placement menu of a target element, wherein the angle placement menu comprises a plurality of preset placement angles;

responding to a first selection event of a cursor, and displaying a preview image of a target chip under a target placement angle, wherein the target placement angle is one of a plurality of preset placement angles;

And responding to a second selection event of the cursor, and generating a design diagram of the target chip under the target placement angle at the target position in the canvas area.

In one possible implementation, before the obtaining the target chip, in response to a selection operation performed for a chip name in a chip type list in a toolbar in the first display interface, the method further includes:

in response to an import operation performed on parameters of the chip, a chip library is established, wherein the parameters include at least the electrical, shape, size, name of the chip.

In one possible implementation, the target placement position is an initial placement position of the target chip in the canvas;

after the m target chips are arranged in the canvas of the first display interface, the method further comprises the following steps:

detecting the initial placement position of the target chip in the canvas in response to the target chip being arranged in the canvas, wherein the canvas comprises a plurality of grid cells arranged in an array, each grid cell in the plurality of grid cells is provided with a contact point, and the contact points are used for representing contact points of the interposer;

and determining a target placement position corresponding to the target chip based on the initial placement position, and adjusting the target chip to the target placement position.

In one possible implementation manner, determining the target placement position corresponding to the target chip based on the initial placement position includes:

detecting whether the initial placement position is aligned with a preset reference position;

and if the initial placement position is aligned with the preset reference position, taking the initial placement position as a target placement position corresponding to the target chip.

determining a plurality of candidate placement positions based on the initial placement positions, wherein the plurality of candidate placement positions are obtained by taking the initial placement positions as starting points and moving the target chip by a second offset;

the target pose location is determined based on the initial pose location and the plurality of candidate pose locations.

In one possible implementation manner, after the m target chips and the interposer are displayed on the second display interface in response to a triggering operation performed on the first control in the first display interface, the method further includes:

and setting netlist names and wiring types of pins in n element modules in m target chips and an interposer in a second display interface, wherein n is an integer greater than 1.

In one possible implementation, setting netlist names and routing types of pins in n component modules in the interposer and m target chips at the second display interface includes:

responding to a triggering operation executed for any pin of n element modules in the m target chips and the intermediate layer, and suspending a display pin setting window on a second display interface;

responding to trigger operation executed for netlist names and wiring types in a pin setting window displayed in a floating manner on a second display interface, and displaying a netlist name input frame or a netlist name list and a wiring type list in the pin setting window;

and displaying a target netlist name identifier corresponding to the target netlist name at any pin in the second display interface in response to an input operation performed for the netlist name input box or a selection operation performed for the netlist name list and a selection operation performed for the routing type list.

In one possible implementation, the routing types include:

a first wiring type, a second wiring type, and a third wiring type,

wherein the first wire type is used for characterizing routing through the interposer, the second wire type is used for characterizing routing through the rewiring layer, and the third wire type is used for characterizing routing through the rewiring layer and/or the interposer.

In one possible implementation, the second display interface further includes a tool menu bar;

displaying a view of any tool at the cursor in response to a selection operation performed by the cursor for any tool in the tool menu;

responding to cursor movement to any pin of n element modules in the m target chips and the intermediate layer;

and in response to the triggering operation executed for any pin, displaying the identification corresponding to any tool at any pin.

In one possible implementation, the tool menu includes at least passive electronic components or contacts.

In one possible implementation, the target display interface includes a third display interface and a fourth display interface, and the target control includes a second control and a third control;

and in response to a triggering operation performed on the target control in the second display interface, displaying the wiring diagram on the target display interface, including:

responding to the triggering operation executed by the second control in the second display interface, displaying a third display interface, wherein m target chips, an intermediate layer and a substrate are displayed in the third display interface, wherein the intermediate layer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

Connecting wires of pins with wiring types set as a first wiring type and connecting wires of joints and contact pads, which belong to the same target netlist name on m target chips and an interposer;

responding to the triggering operation executed by the third control in the second display interface, displaying a fourth display interface, wherein the fourth display interface displays m target chips, an intermediate layer and a substrate, the intermediate layer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

connecting wires of pins with the wiring type set as a second wiring type and connecting wires of joints and contact pads on the m target chips and the interposer layer belong to the same target netlist name.

In one possible implementation, the trigger operation performed in response to the third wiring type in the pin setup window for floating display in the second display interface;

responding to a selection operation executed for a contact name list in a contact setting window;

and responding to a triggering operation executed for a second control in the second display interface, displaying a third display interface, wherein m target chips and connecting wires which belong to the same target netlist name and are arranged as pins of a third wiring type and are routed through the interposer on the same target netlist name and the interposer on the third display interface.

In one possible implementation manner, m target chips and connecting wires which belong to the same target netlist name and are routed through the interposer, of pins with the routing type set as a third routing type, are displayed in a third display interface;

and displaying the connecting wires of pins which belong to the same target netlist name and are set as the third wiring type and are routed through the rewiring layer on the m target chips and the interposer in the fourth display interface.

In one possible implementation, the interposer includes at least a power management module, a communication interface module, a control module, and a level shifter.

In one possible implementation, the method further includes:

displaying a component thumbnail at a cursor in response to a selection operation performed for a component name in a component selection list on a toolbar in a second display interface;

and responding to the triggering operation of the cursor to the intermediate layer, and arranging the components in the intermediate layer.

In one possible implementation, the method further includes:

responding to the selection operation of the execution of the components or modules on the medium layer;

the component or module is deleted from the interposer in response to a delete operation performed for the selected component or module.

In one possible implementation, the method further includes:

and responding to the triggering operation executed for the fourth control in the second display interface, and displaying the stereoscopic view corresponding to the wiring diagram in the target display interface.

In one possible implementation, the method further includes:

and responding to the triggering operation executed for the fifth control in the first display interface, and outputting different types of files corresponding to the wiring diagram.

In a second aspect, an embodiment of the present invention provides a display apparatus, including:

the setting module is used for responding to the setting of m target chips in the canvas of the first display interface, wherein m is an integer greater than 1;

the first display module is used for responding to the triggering operation executed for the first control in the first display interface and displaying m target chips and the intermediary layer on the second display interface;

and the second display module is used for responding to the triggering operation executed for the target control in the second display interface and displaying a wiring diagram on the target display interface, wherein the wiring diagram is generated based on the netlist names and the wiring types of the pins corresponding to the m target chips and the interposer.

In a third aspect, an embodiment of the present invention provides a terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps of any one of the display methods described above when the computer program is executed by the processor.

In a fourth aspect, embodiments of the present invention provide a computer readable storage medium storing a computer program which, when executed by a processor, performs the steps of any one of the display methods described above.

The embodiment of the invention provides a display method, a display device, a terminal and a storage medium, comprising the following steps: the method comprises the steps of firstly responding to the setting of m target chips and an intermediate layer in canvas of a first display interface, then responding to trigger operation executed for a first control in the first display interface, displaying the m target chips and the intermediate layer on a second display interface, and then responding to trigger operation executed for the target control in the second display interface, and displaying a wiring diagram on the target display interface. According to the invention, the position relation and the pin relation of the m target chips and the interposer are set through the first display interface and the second display interface in sequence, so that the automatic connection between the chips and the interposer is realized, and the wiring efficiency is improved. In addition, the invention also generates different wiring patterns according to the set pin relation, namely the netlist names and the signal types of the pins, so as to lead the wiring between the chip and the intermediary layer to be clear and improve the user experience.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, are included to provide a further understanding of the application and to provide a further understanding of the application with regard to the other features, objects and advantages of the application. The drawings of the illustrative embodiments of the present application and their descriptions are for the purpose of illustrating the present application and are not to be construed as unduly limiting the present application. In the drawings:

FIG. 1 is a schematic diagram of a chip library menu bar provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a design page of existing EDA software provided by an embodiment of the present invention;

FIG. 3 is a flowchart of an implementation of a method for placing components according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a setup page of an angle placement menu of a target element according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a preview button provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram of a setting page with 180 degrees of a target element as a setting angle according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a preview of a target element provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of a canvas provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of generating a design drawing of a target element in a canvas provided by an embodiment of the present invention;

FIG. 10 is a schematic diagram of a design page of an active silicon substrate with components according to an embodiment of the present invention;

FIG. 11 is a physical diagram of an element disposed on an active silicon substrate according to an embodiment of the present invention;

FIG. 12 is a flowchart of a method for adjusting a chip position according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a chiplet U9 provided in an embodiment of the present invention;

FIG. 14 is a schematic diagram of a chiplet U2 provided in an embodiment of the present invention;

FIG. 15 is a schematic diagram of a chiplet U23 provided according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of a chiplet U1 provided in an embodiment of the present invention;

FIG. 17 is a schematic diagram of the positional relationship of the chiplet U9 and canvas provided by an embodiment of the present invention;

FIG. 18 is a schematic illustration of a chiplet U9 misaligned with a reference position provided in an embodiment of the present invention;

FIG. 19 is a schematic view of a chiplet U9 aligned with a datum position according to an embodiment of the present invention

FIG. 20 is a schematic diagram of the positional relationship of a chiplet U9 and a plurality of reference positions provided in an embodiment of the present invention;

FIG. 21 is a schematic diagram of a chiplet U2 according to an embodiment of the present invention disposed at an initial placement position E;

FIG. 22 is a schematic diagram of a chiplet U2 according to an embodiment of the present invention disposed at a first candidate placement location F;

FIG. 23 is a schematic diagram of a chiplet U2 according to an embodiment of the present invention disposed at a second candidate placement position G;

FIG. 24 is a flowchart of an implementation of a display method according to an embodiment of the present invention;

FIG. 25 is a schematic diagram of a first display interface according to an embodiment of the present invention;

FIG. 26 is a schematic diagram of a pin setup window according to an embodiment of the present invention;

FIG. 27 is a schematic diagram of a pin setup window provided by another embodiment of the present invention;

FIG. 28 is a schematic diagram of a pin setup window provided by another embodiment of the present invention;

FIG. 29 is a schematic view of a chiplet U12 provided in accordance with an embodiment of the present invention;

FIG. 30 is a schematic diagram of a tool menu bar provided by an embodiment of the present invention;

FIG. 31 is a schematic diagram of a resistance setting window according to an embodiment of the present invention;

FIG. 32 is a schematic diagram of a chiplet U12 provided in accordance with another embodiment of the present invention;

FIG. 33 is a schematic view of a contact setting window according to an embodiment of the present invention;

FIG. 34 is a schematic diagram of a contact name list provided by an embodiment of the present invention;

fig. 35 is a schematic view of a contact setting window according to another embodiment of the present invention;

FIG. 36 is a schematic diagram of a second display interface according to an embodiment of the present invention;

FIG. 37 is a diagram of a third display interface according to an embodiment of the present invention;

FIG. 38 is a schematic diagram of a second display interface provided in accordance with another embodiment of the present invention;

FIG. 39 is a schematic diagram of a third display interface according to another embodiment of the present invention;

FIG. 40 is a schematic view of a wiring switching button provided by an embodiment of the present invention;

FIG. 41 is a schematic diagram of an interposer provided by an embodiment of the present invention;

fig. 42 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 43 is a schematic diagram of a terminal according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.

It should be understood that, in various embodiments of the present invention, the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

It should be understood that in the present invention, "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in the present invention, "plurality" means two or more. "and/or" is merely an association relationship describing an association object, and means that three relationships may exist, for example, and/or B may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. "comprising A, B and C", "comprising A, B, C" means that all three of A, B, C comprise, "comprising A, B or C" means that one of the three comprises A, B, C, and "comprising A, B and/or C" means that any 1 or any 2 or 3 of the three comprises A, B, C.

It should be understood that in the present invention, "B corresponding to a", "a corresponding to B", or "B corresponding to a" means that B is associated with a, from which B can be determined. Determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information. The matching of A and B is that the similarity of A and B is larger than or equal to a preset threshold value.

As used herein, "if" may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context.

The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the following description will be made by way of specific embodiments with reference to the accompanying drawings.

The display method is applied to an EDA tool, and is mainly realized through four steps of chip selection, chip placement, chip position adjustment and wiring, and the four steps are executed in sequence.

In the present application, an EDA tool is provided with a chip Library (chip Library) as shown in fig. 1, and the chip Library includes various chips, such as a power chip, a processor chip, and the like, where the chip Library is mainly established by importing parameters of each chip, such as an electrical, a shape, a size, a name, and the like of the chip, then mapping the parameters of each chip to the chip, forming chip information of each chip, and storing the chip information of each chip to form the chip Library.

And when the user selects the chip by adopting an EDA tool, namely, responding to the selection operation executed for the chip names in the chip selection list in the toolbar in the first display interface, acquiring the target chip. The names of the chips are displayed in the chip type selection list, and the chip can be selected by clicking a certain chip name.

Referring to fig. 1, a chip Library (chip Library) is provided in the first display interface, and an MCU (controller) can be clicked, i.e., various types of MCU chips can be displayed for a user to select. Meanwhile, because the space of the first display interface is limited, if the chip which the user wants to select is not displayed on the first display interface, the user can also search through the search box.

When the chip is selected, the selected chip is required to be arranged in canvas to realize the placement of the chip.

Existing EDA software, as shown in FIG. 2, contains few controls in the EDA software page, where electrical toolbars and drawing bars are essential, in which various types of elements are provided, and a user can click on an element that wants to be placed on a canvas and then place it in the canvas by dragging for subsequent hardware design.

However, since the existing EDA software does not have a setting control for the component placement angle, the component placement angle is usually zero degrees by default, and the default angle cannot be changed. If the arrangement angle of the elements is required to be adjusted, the elements can be arranged on the canvas, and then the arrangement angle of the elements can be manually adjusted on the canvas. That is, the current component placement process can be simply expressed as: after the element is selected, displaying a preview graph of the selected element at the cursor, moving the cursor to a position where the element is to be placed, clicking the cursor to place the element at the position, and finally manually adjusting the placing angle of the element.

For example, the user needs to place an element with a length of 30×20 and a placement angle of 90 degrees, if the user selects an element, then the size of the preview image of the element displayed at the cursor is found to be 40×20, and the user is required to reselect an element if the size of the reselected element is not yet right, and if the size of the reselected element is still not right, the user is required to continue to select the element, which is not friendly to the user and affects the user experience of EDA.

Therefore, the above-mentioned component placement process is not friendly in some application scenarios requiring the placement angle of the component and the appearance of the component, and is complex to operate.

Based on the above problems, the application provides a method for placing elements, which is convenient to operate, and can improve the efficiency of element placement and the user experience.

In one embodiment, as shown in fig. 3, a method for placing components is provided, including the following steps:

step S301: and responding to the first interaction event of the cursor, and displaying an angle placement menu of the target element.

The cursor is a mouse arrow used for identifying the position of the mouse on the graphical interface, wherein the mouse arrow can comprise various modes, such as an arrow mode, an I mode during text input, a small hand mode and the like.

The interaction event includes, but is not limited to, a dwell, a select, a click, etc., where the first interaction event is a dwell event, the dwell event is that a cursor is displayed on a preview button of the target element. The dwell time may be set for a dwell event, that is, a dwell event is responded to after the cursor has been held in the preview button of the target element for a preset period of time; when the cursor is simply slid quickly over the preview button of the target element and the preset duration is not reached, the event is not responded to. The preset time period may be set according to specific situations, and is not limited herein.

When a user clicks a target element through a cursor, a preview of the target element at a default angle (0 degrees) is generated. If the angle of placement of the target element in the canvas is desired to be other angles, then an angle placement menu of the target element is presented at the preview button in response to a dwell event of the cursor on the preview button of the target element.

After the angle placement menu is unfolded, the angle placement menu can be a single angle list or a list of angles can be displayed through a plurality of angle areas. The angle areas are used for displaying a plurality of preset placement angles, and the angle areas correspond to the preset placement angles one by one. That is, a plurality of angle areas are disposed in the angle placement menu, and each angle area corresponds to one placement angle (i.e. a preset angle). The preset placement angles are different, and the preset placement angles can be 5, 7 and the like, are not particularly limited, and can be set according to specific requirements.

Illustratively, when the cursor is moved onto the preview button (as shown in fig. 5) in fig. 4 and the dwell time exceeds the preset dwell time, in response to this dwell event, the angle drop menu of the target element may be presented (popped up) at the preview button.

If a preview of the target element at the target angle is to be displayed at the cursor, then the preview of the target element at the target angle needs to be displayed in response to the second interaction event of the cursor.

And if the second interaction event refers to the stay event of the cursor at the target placement angle, displaying a preview image of the target element at the target placement angle at the cursor in response to the stay event of the cursor at the target placement angle. Wherein the preview image moves with the cursor around the position of the cursor.

Illustratively, in connection with FIG. 6, the angle placement menu lists placement angles of 4 selectable elements, such as 0 degrees, 90 degrees, 180 degrees, and 270 degrees. When the cursor is moved to an angle area corresponding to 180 degrees in the angle placement menu, namely, a stay event of the cursor at 180 degrees, the aspect ratio of the target element is adjusted through the selected 180 degrees, and then a preview image of the element under 180 degrees is displayed at the cursor.

The aspect ratio of the target element is set according to specific situations, for example, when the height-width ratio is 0 degree, the vertical edge pixels and the horizontal edge pixels of the target element are respectively 200 and 100, and when the height-width ratio is 90 degrees, the vertical edge pixels and the horizontal edge pixels of the target element are changed to 100 and 200, and the like.

In addition, if the angle setting menu is to be hidden, only the second interaction event is required to be stopped, namely, the angle setting menu of the target element is hidden in response to the moving-away event of the cursor at the target setting angle.

Step S302: and responding to the first selection event of the cursor, and displaying a preview image of the target element under the target placement angle.

The first selection event refers to an event selected by a cursor clicking manner, wherein the cursor clicking manner includes a left click, a right click, a left click, and the like.

And under the condition that the mode of clicking the cursor is left-click, responding to a selection event of the target placement angle through the left-click of the cursor, and displaying a preview image of the target element under the target placement angle at the cursor, wherein the preview image moves along with the cursor by taking the position of the cursor as the center.

For example, in connection with fig. 7, taking a target element as a chip and a target placement angle as 90 degrees as an example, when a cursor is moved to an angle area corresponding to 90 degrees in an angle placement menu, and then the placement angle 90 degrees is selected by clicking a left key of the cursor, a preview of the chip under 90 degrees is displayed at the cursor, and the model of the chip, that is, TMP108 aiyft, is displayed in the preview.

Of course, after the preview of the target element under the target setting angle is displayed after the selection is clicked by the left key of the cursor, if the preview under the target setting angle is hidden, the preview of the target element under the target setting angle needs to be displayed at the cursor in response to the event of canceling the selection of the target setting angle by the right key of the cursor.

Illustratively, taking the target placement angle as 90 degrees as an example, when the placement angle of 90 degrees is selected by left-click of the cursor, a preview of the target element at 90 degrees is displayed at the cursor. Then, clicking at 90 degrees through the right key of the cursor, namely canceling the selection, and hiding the preview image of the display target element at the cursor at 90 degrees.

Step S303: in response to a second selection event of the cursor, a design drawing of the target element at the target placement angle is generated at the target position in the canvas area.

The second selection event is similar to the first selection event, and also refers to an event selected by clicking a cursor, but the objects acted by the two selection events are different. The cursor clicking mode includes left click, right click, left click, and the like.

And under the condition that the mode of clicking the cursor is left-click, responding to a selection event of the left-click of the cursor on the target position in the canvas area, and generating a design drawing of the target element under the target placement angle at the target position in the canvas area.

Taking the example that the target placement angle is 90 degrees as an example, when the left key of the cursor is clicked at 90 degrees, a preview image of the target element under 90 degrees can be displayed at the cursor, then the cursor is moved to a physical view (canvas) as shown in fig. 8, and a position in the canvas is clicked by the left key of the cursor, then the position is selected as the target position, and then a design image of the target element under the target placement angle is automatically generated at the target position in the canvas area, and the design image is shown in fig. 9.

When the element placement method is applied to EDA software based on the chiplet technology, a user can preview the preview images of target elements to be placed under various angles through the method, and then select the target elements under the appropriate angles to be placed on the drawing board. The drawing board can be mapped to one surface of the active silicon substrate for placing the elements, and the position of the target element placed on the drawing board and the placing angle of the target element during placing can be mapped to the position of the target element placed on the active silicon substrate and the placing angle of the target element placed on the active silicon substrate in actual chip packaging. For example, in EDA software, with reference to FIG. 10, component A is placed in the upper left corner of the canvas at a placement angle of 0 degrees by the present method, i.e., component A will be placed in the upper left corner of the active silicon substrate at a placement angle of 0 degrees in the final chip fabricated according to the EDA design. A chip real-world diagram as shown in fig. 11 was produced according to the design drawing of EDA in fig. 10.

In addition, if the current target element is not selected for the first time, after the target element is set in the canvas and a design diagram of the target element at the target placement angle is generated, the historical placement condition of the target element is displayed on the design diagram, so that the placement angle, the position and the like before the target element are displayed.

If other elements exist in the canvas when the target element is selected, providing recommendations of placement angles, positions and the like for the target element according to the placement conditions of the other elements.

After the selected chip is arranged in the canvas, whether the placement position of the chip is proper or not needs to be confirmed, and if not, the position of the chip needs to be adjusted.

Existing EDA software, as shown in FIG. 2, contains few controls in the EDA software page, where electrical toolbars and drawing bars are essential, in which various types of elements are provided, and a user can click on an element that wants to be placed on a canvas and then place it in the canvas by dragging for subsequent hardware design. Wherein the components include, but are not limited to, chiplets.

However, since the existing EDA software does not have the function of automatically detecting and adjusting the placement position of the chiplet, a designer is generally required to place the chiplet according to accumulated experience, so as to achieve the accuracy of the placement position of the chiplet. However, for inexperienced designers, after the designer sets the chiplet in the canvas of the EDA software, it is necessary to observe whether the placement position is accurate, and if the placement position is inaccurate, the designer needs to manually adjust the placement position of the chiplet.

Therefore, a designer spends a lot of time completing the placement of the chiplet, reducing the work efficiency.

Based on the above problems, the application provides a method for adjusting the chip position, which can automatically detect and adjust the placement position of the chip, and improves the working efficiency of designers.

In one embodiment, as shown in fig. 12, a method for adjusting a chip position is provided, including the following steps:

step S1201: and detecting the initial placement position of the target chip in the canvas in response to the target chip being arranged in the canvas.

The target chip refers to a chiplet or core particle with any function, and comprises an outer frame and a plurality of chip joints, wherein the type and the name of the chiplet are displayed around the outer frame, and the type of the chiplet is U9 and the name of the chiplet is TMP108AIYFFT as shown in fig. 13.

For different types of chiplets, the parameters of the chip contacts corresponding to the chiplets are different, and the parameters of the chip contacts can be set in a chip library of an EDA tool. The parameters of the chip contacts at least comprise the arrangement mode of the chip contacts, the number of the chip contacts and the radius of the chip contacts.

Referring to fig. 13-16, the arrangement of the chip contacts in the chiplet U9 of fig. 13 is a regular arrangement (i.e., 2*3 arrangement), and the number of chip contacts is 6; the arrangement of the chip contacts in the chiplet U2 of fig. 14 is irregular, and the number of the chip contacts is 12; the arrangement of the chip contacts in the chiplet U23 of fig. 15 is a regular arrangement (i.e., 4*5 arrangement), and the number of chip contacts is 20; the arrangement of the chip contacts in the chiplet U1 in fig. 16 is a regular arrangement (i.e., a 2 x 2 arrangement). Furthermore, it is possible to provide a device for the treatment of a disease. The radii of the die attach points in the chiplets shown in fig. 13-16 are different, the radii of the die attach points in the chiplet shown in fig. 16 are the largest and the radii of the die attach points in the chiplet shown in fig. 13 are the smallest.

Wherein the canvas comprises a plurality of grid cells arranged in an array, each grid cell of the plurality of grid cells being provided with a contact, wherein the contact is used to characterize the contact point of the active silicon substrate.

As shown in fig. 17, the plurality of contacts arranged in an array in the canvas of the EDA tool are metal bumps (i.e., contact points) on the active silicon substrate. The active silicon substrate is provided with a programmable routing network, and the programmable routing is programmed, so that the connection between the metal bumps on the active silicon substrate can be freely set.

Taking a target chip as a small chip U9 as an example, after a designer selects the small chip U9 from a chip library, the small chip U9 is dragged into a canvas by manually operating a mouse. At this time, when the small chip U9 is detected to be arranged in the canvas, the initial placing position of the small chip U9 in the canvas is automatically detected, wherein the initial placing position can be the coordinate of a certain point in the small chip in the canvas.

The coordinate of a certain point in the small chip in the canvas is used as the initial placement position, and the reason is as follows: since the coordinates of a point in the chiplet in the canvas are known under the determination of the chiplet type, the coordinates of each point in the chiplet in the canvas can be continuously determined. For example, the coordinates of each point on the chiplet, and even the center coordinates of the chip joints, can be deduced based on the type of the chiplet after determining the coordinates of the bottom left corner of the chiplet, using only the coordinates of the bottom left corner of the chiplet as the initial placement position. The position of the small chip is represented by adopting the coordinate of a certain point, and subsequent calculation processing is carried out, so that the data processing amount is reduced, and the processing speed is improved.

In addition, when the chiplet U9 is placed in the canvas, the chip contacts in the chiplet U9 will contact (achieve a communicating relationship) with the metal bumps on the active silicon substrate, so that signals can be transmitted between the chiplet and the active silicon substrate.

It should be noted that, due to the different types of chiplets, the radii of the chip contacts in the chiplets are different, so that when the chiplets are disposed in the canvas, the overlapping areas of the chip contacts in the chiplets and the contacts in the canvas are different.

Step S1202: and determining a target placement position corresponding to the target chip based on the initial placement position, and adjusting the target chip to the target placement position.

When the EDA tool is used for designing the placement positions of the chiplets, when a designer drags the target chip through a mouse, the chip contacts of the chiplets and the metal bumps of the active silicon substrate cannot be aligned well or have better placement positions, so that the target placement positions need to be determined based on the initial placement positions, the automatic adjustment function of the placement positions of the chiplets is realized, the improvement of design efficiency and design effect is facilitated, and the design difficulty is reduced.

The target placement position of the target chip is determined in two ways, and the method specifically comprises the following steps:

The first way is: detecting whether the initial placement position is aligned with a preset reference position, and if so, taking the initial placement position as a target placement position corresponding to the target chip; if the initial placement position is not aligned with the preset reference position, determining the target placement position in a mode of defining a search area based on the initial placement position.

For example, in connection with fig. 18, assuming that the target chip is a chiplet U9, taking the vertex a of the lower left corner of the outer frame of the chiplet U9 as the initial placement position of the chiplet U9 and taking the grid point B closest to the initial placement position in the canvas as the preset reference position, as can be seen from fig. 18, if the vertex a of the lower left corner of the outer frame of the chiplet U9 is not aligned with the grid point B closest thereto, the target placement position may be determined by defining the search area based on the initial placement position, that is, searching for whether the reference position exists in the search area formed by taking the initial placement position as the center and taking the first offset as the radius, and if the reference position exists in the search area, determining the target placement position based on the number of the reference positions and the initial placement position. The first offset may be set according to the specific situation, and is not limited herein.

Further, referring to fig. 18 to 19, if the number of reference positions is one, that is, the grid point B shown in fig. 8, the reference position is set as the target placement position, and then the vertex a of the lower left corner of the outer frame of the chiplet U9 is adjusted to the grid point B, so that the vertex of the lower left corner of the outer frame of the chiplet U9 coincides with the grid point B as shown in fig. 19.

If the number of reference positions is plural, as shown in fig. 20, including 3, including grid point B, grid point C, and grid point D, then from the 3 reference positions: the closest position to the apex a of the lower left corner of the outer frame of the chiplet U9 is selected as the target reference point, that is, grid point B, and grid point D, and grid point B is taken as the target placement position. The vertex a of the lower left corner of the outer rim of the chiplet U9 is then adjusted to grid point B, as shown in fig. 19, such that the vertex of the lower left corner of the outer rim of the chiplet U9 coincides with grid point B.

In addition, if the reference position does not exist in the search area, the first offset is enlarged until the reference position is found in the search area formed by taking the initial placement position as the center and taking the enlarged first offset as the radius, and the step of determining the target placement position based on the number of the reference positions and the initial placement position is executed.

For example, when the first offset amount a is set as a radius, and the reference position is not found when the search is performed, the first offset amount a may be expanded by a preset multiple, where the preset multiple may be 2, 3, and the like, and is not specifically limited herein. And when the preset multiple is 2, the expanded first offset is 2a, the initial placement position is taken as the center, and searching is performed in a search area formed by taking 2a as the radius, if the reference position is found, the target placement position is determined based on the number of the reference positions and the initial placement position, if one reference position is found, the reference position is taken as the target placement position, and if a plurality of reference positions are found, the reference position closest to the initial placement position is selected as the target placement position. Optionally, when multiple reference positions are found, an appropriate reference position may be selected as a target placement position according to preset rules, for example, as far as possible from an existing chiplet, as far as possible from an edge of the active silicon substrate, and so on.

If the reference position is not found in the search area formed by taking the initial placement position as the center and taking 2a as the radius, the offset is further enlarged, namely, the reference position is found in the search area formed by taking the initial placement position as the center and taking 4a as the radius, and if the reference position is not found, the offset is further enlarged until the reference position is found.

In this embodiment, this application not only automated inspection target chip's initial placement position to look for the reference position through initial placement position is automatic, and then confirm target chip's target placement position, realized that target chip put's automation, need not designer and carry out manual operation, save designer's time, and then improved chip position adjustment, put work's efficiency.

The second way is: and determining a plurality of candidate placement positions based on the initial placement position, wherein the plurality of candidate placement positions are obtained by moving the target chip by taking the initial placement position as a starting point and a second offset, and then determining the target placement position based on the initial placement position and the plurality of candidate placement positions. The second offset may be set according to the specific situation, and is not limited herein.

By way of example, in connection with fig. 21-23, assuming the target chip as a chiplet U2, the initial placement position of the chiplet U2 as a point E in the canvas, moving the chiplet U2 with a second offset from the point E may result in two candidate placement positions, a first candidate placement position, i.e., point F shown in fig. 22, and a second candidate placement position, i.e., point G shown in fig. 23. Then, the target placement position may be determined by the initial placement position E, the first candidate placement position F, and the second candidate placement position G.

After the initial placement position and the candidate placement positions are determined, the target placement position needs to be determined by calculating the overlapping areas of all chip joints in the target chip and all joints corresponding to the initial placement position and the candidate placement positions. Specifically, the overlapping areas of all chip contacts in the target chip and all contacts corresponding to the initial placement positions are calculated to obtain a first overlapping area, then the overlapping areas of all chip contacts in the target chip and all contacts corresponding to each candidate placement position in the candidate placement positions are calculated to obtain a plurality of candidate overlapping areas, the candidate placement positions and the candidate overlapping areas are in one-to-one correspondence, and then the first overlapping area and the candidate overlapping areas are compared to determine the target placement position.

Comparing the first overlapping area with the plurality of candidate overlapping areas to determine a target placement position, wherein the first overlapping area is larger than each of the plurality of candidate overlapping areas, and the initial placement position is taken as the target placement position; and sequencing the first overlapping area and the plurality of candidate overlapping areas according to forward sequencing to obtain all the sequenced overlapping areas, selecting the last overlapping area in all the sequenced overlapping areas as a target overlapping area, and taking the placement position corresponding to the target overlapping area as a target placement position.

For example, in conjunction with fig. 21-23, the overlapping areas of all the 22 chip contacts in the chiplet U2 corresponding to the initial placement position E, the first candidate placement position F, and the second candidate placement position G are calculated to obtain a first overlapping area S1, a first candidate overlapping area S2, and a second candidate overlapping area S3, respectively. If the first overlapping area S1 is larger than the first candidate overlapping area S2 and the second candidate overlapping area S3, taking the initial placement position E corresponding to the first overlapping area S1 as a target placement position; if the first overlapping area S1 is smaller than the first candidate overlapping area S2 and smaller than the second candidate overlapping area S3, the second candidate placement position G corresponding to the area maximum, i.e., the second candidate overlapping area S3 is taken as the target placement position.

Further, for calculating the overlapping area of all the chip joints in the target chip and all the joints corresponding to the initial placement position, a first overlapping area is obtained, a plurality of joints corresponding to the chip joints are required to be obtained for each of all the chip joints in the target chip, the overlapping area of each of the chip joints and each of the joints is determined based on the distance between the circle center of the chip joint and the circle center of each of the joints, then the overlapping area of each of the chip joints and each of the joints is summarized and calculated, the overlapping area corresponding to the chip joints is obtained, and then the overlapping area corresponding to all the chip joints is summed and calculated, so that the first overlapping area is obtained.

The overlapping area of the chip contact and each contact of the plurality of contacts is determined based on the distance between the center of the chip contact and the center of each contact of the plurality of contacts, a distance interval to which the distance between the center of the chip contact and the center of the contact belongs is determined for each contact of the plurality of contacts, then an area corresponding to the distance interval is obtained, and the area is used as the overlapping area of the chip contact and the contact. By calculating the overlapping area in such a way, the calculation speed of a certain degree can be ensured under the condition of ensuring the calculation accuracy of a certain overlapping area, and the calculation amount is reduced to a certain degree, so that the speed of determining the target placement position is improved.

Illustratively, in connection with FIG. 21, taking the first chip contact in the upper left corner of chiplet U2 as an example, it can be seen from FIG. 21 that the first chip contact in the upper left corner covers a plurality of contacts in the canvas. Because the first chip contact at the upper left corner is only partially covered with some contacts in the canvas, the overlapping area is difficult to calculate accurately, and therefore, the overlapping area is determined by the distance interval of the distance between the center of the first chip contact at the upper left corner and the center of the contact in the canvas.

Specifically, a first distance interval is set to be 0-1.5cm, and the corresponding area is set to be L1; the second distance interval is [1.6-2cm ], and the corresponding area is L2; the third distance interval is [2.1-2.5cm ], and the corresponding area is L3; the fourth distance interval is [2.6-3cm ], and the corresponding area is L4, wherein L1> L2> L3> L4. As can be seen from fig. 21, the first chip contact in the upper left corner overlaps 7 contacts in the canvas, with 3 contacts fully covered and the other 4 contacts partially covered. That is, the distance between the 3 contacts completely covered and the center of the first chip contact at the upper left corner falls within the first distance interval [0-1.5cm ], then the corresponding area is 3L1, the distance between the 3 contacts of the other 4 contacts and the center of the first chip contact at the upper left corner falls within the third distance interval [2.1-2.5cm ], then the corresponding area is 3L3, and the distance between the other contact and the center of the first chip contact at the upper left corner falls within the fourth distance interval [2.6-3cm ], then the corresponding area is L4. By summing all areas, the overlapping area y1=3l1+3l3+l4 of the first chip contact in the upper left corner and the plurality of contacts in the covered canvas is obtained.

By the above way, the overlapping area of the other chip contacts in the small chip U2 and the contacts in the covered canvas can be calculated, and then the overlapping area of all chip contacts in the small chip U2 and the contacts in the covered canvas is calculated, so that the first overlapping area S1 can be obtained.

It should be noted that, in the present application, the method for determining the plurality of candidate overlapping areas by calculating the overlapping areas of all chip contacts in the target chip and all contacts corresponding to each candidate placement position in the plurality of candidate placement positions is similar to the method for calculating the first overlapping area, and will not be described herein.

Alternatively, the determination of the target placement position of the target chip may be achieved by a combination of the first manner and the second manner, and specifically, when the plurality of reference positions are determined in the manner of defining the search area based on the initial placement position mentioned in the first manner, the overlapping areas of all the chip contacts in the target chip and all the contacts corresponding to the plurality of reference positions are calculated in the manner of calculating the overlapping areas mentioned in the second manner, and finally, one reference position is selected from the plurality of reference positions as the target placement position according to the overlapping area corresponding to each reference position. The determining process of the reference position, the calculating process of the overlapping area and the selecting process of the target placement position are similar to the first mode and the second mode, and are not repeated.

When the number of chips is m, the selection and position adjustment of m target chips can be realized through the steps, wherein m is an integer greater than 1.

After the m target chips are selected and the positions of the m target chips are adjusted, the m target chips and the intermediate layers are displayed in canvas of the first display interface, the first control is triggered to realize the jump of the interface, and the corresponding wiring patterns are displayed based on the m target chips and the intermediate layers in other display interfaces.

Based on the above-mentioned idea, as shown in fig. 24, a display method is provided, which includes the following steps:

step S2401: the m target chips and the interposer are disposed in a canvas of the first display interface.

Wherein m is an integer greater than 1.

The target chip can be any chip, and is selected according to the requirements of clients, such as a sensor chip, a power management module, a communication interface module, a control module, a level converter and the like. The component module in the interposer is preset, wherein the component module is set based on the type of the interposer, and the component module can comprise any electronic device, circuit and combination of the electronic device and the circuit, wherein the electronic device can be an amplifier device, a power chip, an MCU and the like.

Step S2402: and responding to a triggering operation executed for a first control in the first display interface, and displaying the m target chips and the interposer on a second display interface.

After the m target chips and the interposer are arranged in the canvas on the first display interface, the first control in the first display interface can be triggered, namely, the m target chips and the interposer are displayed on the second display interface in response to the triggering operation executed on the first control in the first display interface.

The interposer includes n element modules, where n is an integer greater than 1. After the second display interface displays the n component modules in the m target chips and the interposer, netlist names and routing types of pins in the n component modules in the m target chips and the interposer may be set in the second display interface.

As shown in fig. 25, the second display interface 251 displays an interposer 252 and 2 target chips, wherein 2 component modules, respectively S4 and S5, are provided in the interposer 252, and the target chips, respectively U12 and U15, are provided on the right side of the interposer 252.

As can be seen from fig. 25, whether the component modules on the interposer 252 or some pins of the target chip on the right side thereof are required to be set according to customer requirements, the set items include netlist names of pins, wiring types, and Extended Tiles. The set operation method for the pins in the n element modules in the m target chips and the interposer is the same.

Further, the operations performed for setting netlist names and routing types of pins in n component modules in the m target chips and interposer at the second display interface mainly include: the method comprises the steps of firstly suspending and displaying a pin setting window on a second display interface in response to trigger operation executed on any pin of n element modules in m target chips and an intermediate layer, then displaying a netlist name input frame or a netlist name list and a wiring type list on the pin setting window in response to trigger operation executed on netlist names and wiring types in the pin setting window which are displayed in a suspending mode on the second display interface, and then displaying target netlist name identifiers corresponding to target netlist names on any pin in the second display interface in response to selection operation executed on the netlist name input frame or the netlist name list and selection operation executed on the wiring type list.

Wherein the wiring types include: a first routing type for characterizing routing through an interposer, a second routing type for characterizing routing through a rewiring Layer (RDL, reDistribution Layer), and a third routing type for characterizing routing through a rewiring Layer and/or an interposer.

After selecting the wiring types corresponding to the pins, the pin signal types corresponding to different wiring types can be selected. Namely, according to the selection operation performed in response to the input operation performed for the netlist name input box or the netlist name list and the selection operation performed for the wiring type list in the above steps, then in response to the operation performed for the wiring type list to select the wiring type, the pin setting window displays the pin signal type list; the pin signal types include: the pin signal type is selected by clicking a cursor.

In one possible implementation, in response to an operation performed for the routing type list to select the first routing type or the third routing type and an operation performed for the pin signal type to select the digital signal, a drive pin is selected from pins of the same netlist name, and a window is set for the drive pin to select the drive control.

Specifically, as shown in fig. 26, when clicking the C3 pin on the chip U12, a pin setting window is displayed in a floating manner on the chip U12, where the pin setting window includes three boxes, and the upper box on the left side is a netlist name input box or a netlist name list, and the netlist name setting of the pin C3 can be achieved by inputting a netlist name (e.g., the Enter Netname shown in fig. 26) in the netlist name input box. In addition, the upper left box can also be a netlist name list, and the netlist name setting of the pin C3 is realized through selecting any one netlist name in the netlist name list.

The right frame in the pin setting window is mainly used for setting the wiring types of pins, and for pins which are not subjected to wiring type setting, the Unassign is displayed in the frame first, and after clicking the Unassign, a wiring type list is directly displayed, wherein the wiring type list comprises three wiring types, namely a first wiring type (Programmable), a second wiring type (Metal Only) and a third wiring type (Metal Programmable). By clicking any wiring type, the setting of the wiring type of the pin C3 can be realized.

With reference to fig. 27, after setting the wiring type of the pin C3 to the first wiring type (Programmable), the pin signal type corresponding to the Programmable, that is, the Digital signal (Digital), the Analog signal (Analog), and the Power signal (Power), may be displayed by clicking the Programmable.

By setting the netlist name of the pin C3 as U12 DEC3 in the above manner, after the wiring type is set as Programmable, clicking a confirmation key in the pin setting window, wherein the confirmation key can be represented by Save, ok and the like, and the pin setting window is hidden or retracted. Accordingly, an identification corresponding to the netlist name, namely U12 DEC3, is displayed at pin C3. Wherein, the U12 DEC3 is displayed with a preset highlighting color, which can be defined by a customer or selected through a color setting menu.

Referring to fig. 25 and 29, after setting both the netlist name and the routing type of the pin C3, responding to a selection operation of the cursor for the target pin C3, responding to a selection operation of the cursor for the other pins, for example, the D2 pin on the U15 chip, and selecting the D2 pin to be connected with the pin C3; the same netlist name as pin C3 is displayed at the selected pin and the same highlighting color as pin C3 is displayed, at which point the D2 pin has been defined as the same netlist name and routing type as C3.

Referring to fig. 28, if the C3 wiring type is the first wiring type (Programmable) or the third wiring type (metal Programmable), the signal type is selected as the Digital signal (Digital) type, and one of the pins with the same netlist name, i.e., pin C3 and pin D2, needs to be selected as a driving pin, and the driving control (driver) in the three lower right-hand corner controls is checked. This is because the driver pins need to be selected when the digital signal lines are routed through the interposer.

Referring to fig. 28, if the C3 wiring type is the second wiring type (metal Programmable) or the third wiring type (metal only), a flying lead control (performance title) in the three controls at the lower right corner may be checked, then the target display interface may display a flying lead between the pins routed through the re-routing layer, and when the target display interface needs to edit the pin connection line routed through the re-routing layer, the pins with the same name of the netlist may be identified by the flying lead between the pins.

In addition, the lower left box in the pin setting window is Extended Tiles. The input frame is used for communicating the wiring of the rewiring layer with the inside of the interposer; in the target display interface, the interposer is divided into grids (tiles) of 44×64 or other specifications by grid lines; when the wiring type of a certain pin is the second wiring type or the third wiring type, the number of rows and columns of a certain grid (tile) on the interposer of the target display interface are input in the Extended Tiles frame. The connection lines on the rewiring layer for the pins whose name is the same as that of the netlist are connected to the interposer through the mesh (tile).

The second display interface in the present application further includes a tool menu bar, that is, an a area, a B area, and a C area in fig. 25, where the a area, the B area, and the C area may set various setting items in each area according to a user requirement. It should be noted that the setting items in the respective areas are not repeatable.

Referring to fig. 30, a tool menu bar is set in the area a, where the tool (tool) menu bar includes passive electronic components, contacts (bond pads), print buttons, and withdraw operation buttons from left to right.

In the case where the Tool (TOOLS) menu bar includes a resistor, a contact (BONDPAD), a view of any tool is displayed at the cursor in response to a selection operation performed by the cursor for any tool in the tool menu, then a corresponding identification of any tool is displayed at any pin in response to movement of the cursor to any pin in the n component modules in the m target chips and interposer, and then in response to a triggering operation performed for any pin.

When any tool is a resistor, by clicking the icon of the resistor shown in fig. 30, the icon of the resistor is displayed at the cursor, and simultaneously the resistor resistance setting window shown in fig. 31 is popped up, when 10000 (i.e. 10 k) is input, the cursor is moved to the pin D2 of the chip U12, and then it can be seen that a resistor with a resistance of 10k is connected to the pin D2 shown in fig. 32, and the icon of the resistor and the mark rn_1 are displayed.

When any tool is bond pad, by clicking the bond pad icon shown in fig. 29, the bond pad icon is displayed at the cursor, and the bond pad icon is directly moved to the pin B4 of the chip U12, then it can be seen that a bond pad is connected to the pin B4 shown in fig. 32, and the bond pad icon and the identification bond pad_2 are displayed.

After the bond pad is set on the corresponding pin in the above manner, when the bond pad jumps to the target display interface, the bond pad set before and the name corresponding to the bond pad are displayed on the interposer displayed in the target display interface. Therefore, the name corresponding to the bond pad needs to be set on the second display interface, and the specific implementation manner is as follows: and displaying the names of the contacts in a floating manner on the second display interface in response to a triggering operation executed for the identifier corresponding to the contact displayed at any pin, and displaying the names of the contacts in response to a selecting operation executed for the contact name list in the contact setting window, wherein the names of the contacts are in one-to-one correspondence with the names of the contacts on the interposer on the target display interface.

Through the above operation, a bond pad is connected to the pin B4 shown in fig. 32, and an icon of the bond pad and the identifier bond pad_2 are displayed. Then click on the bond pad at B4, pop up the contact setup window shown in fig. 33, and click on the contact setup window, display the contact name list shown in fig. 34, where the contact name list displays a plurality of contact names, such as pacdio_i_0/12, pacdio_i_1/20, pacdio_i_2/28, and so on. The corresponding contact name is selected by clicking on the box in front of the contact name. After clicking on the box in front of the Padio_I_4/44, the contact name list is hidden or collapsed, after which Padio_I_4/44 is displayed in the contact setup window as shown in FIG. 35. Finally, clicking the confirm button Save.

Step S2403: and responding to the triggering operation executed for the target control in the second display interface, and displaying the wiring diagram on the target display interface.

The wiring diagram is generated based on netlist names and wiring types of pins corresponding to the m target chips and the interposer.

The target display interface includes a third display interface and a fourth display interface, and the target control includes a second control and a third control, where the second control and the third control may be controls disposed in any of the area a, the area B, and the area C in the second display interface shown in fig. 25.

Based on the three wiring types, the connecting wires of the pins of the different wiring types can be displayed in different display interfaces, so that the connecting wires of the pins of the three wiring types are displayed in the third display interface and the fourth display interface.

The third display interface is used for displaying the m target chips and connecting wires of pins belonging to the same target netlist name and having the wiring types set as the first wiring type and the third wiring type on the interposer. The specific implementation steps are as follows: and responding to the triggering operation executed by the second control in the second display interface, displaying a third display interface, wherein m target chips and intermediaries are displayed in the third display interface, connecting wires of pins which belong to the same target netlist name and are set to be of a first wiring type on the m target chips and intermediaries, and connecting wires of pins which belong to the same target netlist name and are set to be of a third wiring type on the m target chips and intermediaries are arranged through intermediaries.

Illustratively, clicking on a second control disposed in the second display interface jumps to the third display interface. As shown in fig. 36, a chip layer 1201 (including a chip U12 and a chip U15) and an interposer 1202 are displayed in the third display interface from top to bottom, where a pin C2 of the chip U12 and a pin A1 of the chip U15 belong to the same netlist name (i.2c0_sda), and a connection line between the pin C2 and the pin A1 is displayed in the interposer 1202. In addition, the pin C1 of the chip U12 and the pin A3 of the chip U15 belong to the same netlist name (i.e. i3c1_sda), and the pin C1 and the pin A3 are both of the third wiring type, so that the connection lines of the pin C1 and the pin A3 are displayed on the interposer 1202.

According to the above example, further, a menu bar may be further disposed on the right side of the second display interface, where a route view button is disposed; clicking a second control arranged in the second display interface, and jumping to a third display interface, wherein only the chip layer 1201 and the interposer 1202 are displayed at the moment, and connecting wires between pins are not displayed; responding to the cursor for connection operation of the pin C1 and the pin A3 and the pin C2 and the pin A1 or responding to triggering operation executed for a route view button in a menu bar in a second display interface; pin C1 and pin A3 and pin C2 and pin A1 are connected by a connecting wire.

The fourth display interface is used for displaying the m target chips and connecting wires of pins belonging to the same target netlist name and having the wiring types set as the second wiring type and the third wiring type on the interposer. The specific implementation steps are as follows: and responding to the triggering operation executed by the third control in the second display interface, displaying a fourth display interface, wherein m target chips and an intermediate layer, connecting wires of pins which belong to the same target netlist name and are set as a second wiring type on the m target chips and the intermediate layer, and connecting wires which belong to the same target netlist name and are routed through a rerouting layer, of pins which are set as a third wiring type, on the m target chips and the intermediate layer.

Illustratively, clicking on a third control disposed in the second display interface jumps to the fourth display interface. As shown in fig. 36, a chip layer 1201 (including a chip U12 and a chip U15) and an interposer 1202 are displayed in the fourth display interface from top to bottom, where a pin C3 of the chip U12 and a pin A2 of the chip U15 belong to the same netlist name (I2 c0_sda, for example), and the pin C3 and the pin A2 are both of the second wiring type, and then a connection relationship between the pin C3 and the pin A2 is displayed in the interposer 1202. In addition, the pin C1 of the chip U12 and the pin A3 of the chip U15 belong to the same netlist name (i.e. i3c1_sda), and the pin C1 and the pin A3 are both of the third wiring type, so that the connection relationship between the pin C1 and the pin A3 is displayed in the redistribution layer.

According to the above example, further, a menu bar may be further set on the right side of the fourth display interface, where an edit list is set; and selecting a flying wire control (performance Tilemap) in three controls at the right lower corners of the pin C3 and the pin C1 pin setting window on the second display interface, clicking a third control arranged in the second display interface, and jumping to a fourth display interface, wherein the fourth display interface can display flying wires between the pin C3 and the pin A2 and between the pin C1 and the pin A3, and when the target display interface needs to edit connecting wires between the pin C3 and the pin A2 and between the pin C1 and the pin A3, the pins with the same names of netlists can be identified through the flying wires between the pins. Selecting editable options in an edit list in a menu bar in a fourth display interface; connecting wires are formed by connecting the pins C3 and A2 with the pins A1 and A3 through a cursor, or connecting wires between the pins C3 and A2 and between the pins C1 and A3 are formed by clicking an automatic connecting button in a menu bar in a fourth display interface.

As shown in fig. 41, the second display interface and the third display interface can both display the mesh diagram of the interposer, and at this time, the chip layer 1201 does not display the outer frame, only displays the outer frames of the chip U12 and the chip U15, and this view can clearly see that the chip pins occupy several meshes 12021 (tiles). The interposer 1202 of the third display interface is divided into a grid (tile) view of 44×64 or other specifications, and a rowbit display view 1301 is further provided on the right side of the interposer 1202 or the substrate 1205; the row bit display view 1301 is used to show the occupation situation of the common transverse analog channels of each row of the grids (tile) of the interposer, as shown in fig. 41, which shows that the grids 12021 (tile) of each row of the interposer have seven common transverse analog channels, and when one of them is occupied, the grid of the row bit display view 1301 corresponding to the common transverse analog channel in the transverse direction is highlighted, as shown in 13011, and as shown in black mark of fig. 41.

Note that, the four sides of the periphery of the interposer 1202 are uniformly provided with contacts (bond pads) 1203, and each bond pad is marked with a respective code. Among them, the BONDPAD shown in fig. 36 and 37 is only an example.

In addition, the jump or switch of the second display interface, the third display interface and the fourth display interface can be respectively realized through the first interface control, the second interface control and the third interface control. The first interface control may be a "scheme View" button, the second interface control may be an "Optimize" button, etc., and the third interface control may be a "Package View" button, etc. The buttons corresponding to the three interface controls are only examples, and can be represented by other identifiers.

Because the menu bars above the second display interface, the third display interface and the fourth display interface all comprise the three interface controls, the user can automatically jump to the corresponding display interface by clicking any one of the three interface controls. The second display interface is provided with m target chips and an intermediate layer, and connecting wires belonging to the same target netlist name pin on the m target chips and the intermediate layer.

When clicking the second interface control "Optimize" button, that is, in response to a triggering operation performed on the "Optimize" button in the menu bar above the second display interface, m target chips and intermediaries are displayed on the third display interface, connecting lines of pins belonging to the same target netlist name and having a wiring type set as the first wiring type are connected to the m target chips and intermediaries, and connecting lines of pins belonging to the same target netlist name and having a wiring type set as the third wiring type are routed through the intermediaries.

When clicking a third interface control (Package view), that is, responding to the triggering operation executed by the third interface control, m target chips and intermediaries are displayed on a fourth display interface, connecting lines of pins belonging to the same target netlist name and having the wiring type set as a second wiring type on the m target chips and intermediaries, and connecting lines of pins belonging to the same target netlist name and having the wiring type set as a third wiring type and being routed through a rerouting layer on the m target chips and intermediaries.

When the m target chips and the connecting wires of the pins on the interposer are displayed on the target display interface, the connecting wires are displayed on different display interfaces based on the wiring types of the pins. In addition, the connection wire needs to be connected with the pins of the external equipment through the contact of the interposer and the connection wire of the substrate, so that more functions are realized.

Therefore, for the third display interface, it is used for displaying m target chips and connecting wires belonging to the same target netlist name and having the wiring type set as the pins of the first wiring type and connecting wires of the contacts and the contact pads on the interposer, the specific implementation steps are as follows: responding to the triggering operation executed by the second interface control 'Optimize' or the first control of the second display interface, displaying a third display interface, wherein m target chips are displayed in the third display interface, an interposer and a substrate are displayed on the interposer, contacts are displayed on the interposer, and contact pads capable of being connected with the contacts are displayed on the substrate; and displaying connecting wires which belong to the same target netlist name and are provided with pins of the first wiring type on the m target chips and the interposer, connecting wires which belong to the same target netlist name and are provided with pins of the third wiring type and are provided with pins of the second wiring type on the m target chips and the interposer and connecting wires of the contact pads through the interposer.

Illustratively, the second interface control "Optimize" or the second control button of the second display interface is clicked first, and the process jumps to the third display interface. As shown in fig. 38, the third display interface includes a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202 and a substrate 1205 sequentially arranged from top to bottom, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 38 are only examples.

Since the pin C2 of the chip U12 and the pin A1 of the chip U15 belong to the same netlist name (i.e. i2c0_sda), and the pin C2 and the pin A1 are both of the first wiring type, the connection relationship between the pin C2 and the pin A1 is displayed on the interposer 1202. In addition, the corresponding external leads of the connection lines of the pins belonging to the first wiring type may also be simultaneously displayed on the third display interface, that is, the connection lines of the pin C2 and the pin A1 are connected through the contact pads 21 on the contacts 11 and 1205 on the interposer 1202 as the external leads of the pin C2 and the pin A1.

Aiming at a fourth display interface, the fourth display interface is used for displaying the m target chips and the connecting wires of pins belonging to the same target netlist name and having the wiring type set as a second wiring type and the connecting wires of joints and joint pads, and the specific implementation steps are as follows: responding to the triggering operation of a third control of the second display interface or the third interface control, displaying a fourth display interface, wherein the fourth display interface displays m target chips, an intermediate layer and a substrate, the intermediate layer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts; the fourth display interface displays the m target chips and the connecting lines of pins belonging to the same target netlist name and having the wiring type set as the second wiring type and the connecting lines of the contact points and the contact pads on the interposer.

Illustratively, clicking on the third interface control "Package view" button or clicking on the third control button on the second display interface jumps to the fourth display interface. As shown in fig. 39, the fourth display interface includes a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202 and a substrate 1205 sequentially arranged from top to bottom, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 39 are only examples.

Since pin C3 of chip U12 and pin A2 of chip U15 belong to the same netlist name (i.e., i2c0_sda), and pin C3 and pin A2 are both of the second routing type, the connection relationship between pin C3 and pin A2 is shown in interposer 1202. In addition, the corresponding external leads of the connection lines of the pins belonging to the second wiring type may also be simultaneously displayed on the fourth display interface, that is, the connection lines of the pin C3 and the pin A2 are connected through the contact pads 23 on the contacts 13 and 1205 on the interposer 1202 as the external leads of the pin C2 and the pin A1.

In addition, only one target display interface may be provided, that is, the third display interface and the fourth display interface are displayed on one interface, and the view is switched by providing a first Wiring button, a second Wiring button and a third Wiring button in a toolbar on the right side of the target display interface, where the first Wiring button, the second Wiring button and the third Wiring button may be provided as a Wiring switching button (wire) as shown in fig. 40.

Clicking a first wiring diagram button in a target display interface, and responding to a triggering operation executed for the first wiring button, the target display interface displays m target chips and intermediaries, connecting wires of pins which belong to the same target netlist name and are set to be of a first wiring type on the m target chips and intermediaries, and wiring connecting wires of pins which belong to the same target netlist name and are set to be of a third wiring type on the m target chips and intermediaries through intermediaries.

Clicking a second wiring diagram button in a target display interface, and responding to a triggering operation executed for the second wiring button, the target interface displays m target chips and intermediaries, connecting wires which belong to the same target netlist name and are provided with pins of a second wiring type on the m target chips and intermediaries, and connecting wires which belong to the same target netlist name and are provided with pins of a third wiring type on the m target chips and intermediaries and are routed through a rewiring layer.

Clicking a third wiring diagram button in a target display interface, and responding to a triggering operation executed for the third wiring button, wherein the target interface displays m target chips and an intermediate layer, and connecting lines of all pins belonging to the same target netlist name on the m target chips and the intermediate layer.

Therefore, aiming at the target display interface, the method is used for displaying the m target chips and the connecting wires belonging to the same name pin of the target netlist and the connecting wires of the contact points and the contact pads on the interposer, and specifically comprises the following steps:

in response to a trigger operation performed for a first wiring diagram button in the target display interface, displaying at the target display interface:

the chip comprises m target chips, an intermediate layer and a substrate, wherein the intermediate layer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

and connecting wires of pins which belong to the same target netlist name and are set as a first wiring type on the m target chips and the interposer, connecting wires of wires which belong to the same target netlist name and are set as a third wiring type on the m target chips and the interposer and are connected through the interposer, and connecting wires of contacts and contact pads.

Illustratively, clicking the target control of the second display interface first jumps to the target display interface and clicks the first routing button. As shown in fig. 38, the target display interface includes a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202, and a substrate 1205 sequentially arranged from top to bottom, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 38 are only examples.

Since the pin C2 of the chip U12 and the pin A1 of the chip U15 belong to the same netlist name (i.e. i2c0_sda), and the pin C2 and the pin A1 are both of the first wiring type, the connection relationship between the pin C2 and the pin A1 is displayed on the interposer 1202. In addition, the corresponding external leads of the connection lines of the pins belonging to the first wiring type may also be simultaneously displayed on the target display interface, that is, the connection lines of the pin C2 and the pin A1 are connected through the contact pads 21 on the contacts 11 and 1205 on the interposer 1202 as the external leads of the pin C2 and the pin A1.

In response to a trigger operation performed for the second wiring diagram button in the target display interface, the target interface displays:

and connecting wires of pins belonging to the same target netlist name and having a wiring type set as a second wiring type on the m target chips and the interposer, connecting wires of pins belonging to the same target netlist name and having a wiring type set as a third wiring type on the m target chips and the interposer, and connecting wires of contacts and contact pads through the rewiring layer.

Illustratively, clicking the target control of the second display interface first jumps to the target display interface and clicks the second routing button of the target display interface. As shown in fig. 39, the target display interface includes a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202 and a substrate 1205 sequentially arranged from top to bottom, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 39 are only examples.

Since pin C3 of chip U12 and pin A2 of chip U15 belong to the same netlist name (i.e., i2c0_sda), and pin C3 and pin A2 are both of the second routing type, the connection relationship between pin C3 and pin A2 is shown in interposer 1202. In addition, the corresponding external leads of the connection lines of the pins belonging to the second wiring type may also be simultaneously displayed on the target display interface, that is, the connection lines of the pin C3 and the pin A2 are connected through the contact pads 23 on the contacts 13 and 1205 on the interposer 1202 as the external leads of the pin C2 and the pin A1.

In addition, the application may further operate the components disposed on the interposer, that is, first, display a component thumbnail at a cursor in response to a selection operation performed on a component name in a component selection list on a toolbar in the second display interface, and then dispose the components in the interposer in response to a triggering operation performed by the cursor on the interposer.

Specifically, the selection operation is responded to the execution of the components or modules on the medium layer;

Further, the application may further generate a stereoscopic view, that is, respond to a triggering operation performed on the fourth control in the second display interface, and display a stereoscopic view corresponding to the wiring diagram in the target display interface, where the stereoscopic view may be a 2D, 3D, 4D, or other stereoscopic view.

Furthermore, the wiring diagram can be exported, that is, different types of files corresponding to the wiring diagram are output in response to the triggering operation executed for the fifth control in the first display interface.

Among other types of files that may be exported include, but are not limited to, GDS files, SIP files, DXF files, STP files, ODB++ files, gerber files, IPC files, SPICE netlist files, API/SDK files, VHDL/Verilog hardware description language files, schdulic files, report files, bump list files, ballmap files, POD files, CSV/EXCEL/TXT files, ZEF files, process information.

In addition, files may be imported into the first display interface, where the imported file types include, but are not limited to, GDS files, SIP files, DXF files, STP files, odb++ files, gerber files, IPC files, SPICE netlist files, API/SDK files, VHDL/Verilog hardware description language files, schema files, report files, bump list files, ballmap files, POD files, CSV/EXCEL/TXT files, ZEF files, process information, and chiplets or silicon bridges, schematic diagrams of the connection between chiplets and chiplets, circuit description languages, baseboard files, two-dimensional/three-dimensional structures, rewiring layers, intermediaries, netlists (connection relationships in netlists are presented in text), design parameters (line width, line spacing, etc.) design rule, export +report +software interfaces.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.

The following are device embodiments of the invention, for details not described in detail therein, reference may be made to the corresponding method embodiments described above.

Fig. 42 shows a schematic structural diagram of a display device according to an embodiment of the present invention, and for convenience of explanation, only a portion related to the embodiment of the present invention is shown, and the display device includes a setting module 4201, a first display module 4202, and a second display module 4203, which are specifically as follows:

a setting module 4201, configured to respond to setting m target chips in a canvas of a first display interface, where m is an integer greater than 1;

a first display module 4202, configured to display the m target chips and the interposer on a second display interface in response to a trigger operation performed on a first control in the first display interface;

and a second display module 4203, configured to display, on a target display interface, a wiring pattern in response to a trigger operation performed on a target control in the second display interface, where the wiring pattern is generated based on netlist names and wiring types of pins corresponding to the m target chips and the interposer.

In a possible implementation manner, before the setting module 4201, the method further includes a placement module, where the placement module is configured to, for each of the m target chips, obtain the target chip in response to a selection operation performed on a chip name in a chip selection list in a toolbar in the first display interface;

responding to a first interaction event of a cursor, and displaying an angle placement menu of the target element, wherein the angle placement menu comprises a plurality of preset placement angles;

responding to a first selection event of the cursor, and displaying a preview image of the target chip under a target placement angle, wherein the target placement angle is one of the preset placement angles;

and responding to a second selection event of the cursor, and generating a design diagram of the target chip under the target placement angle at a target position in a canvas area.

In one possible implementation, before the setting module 4201, a chip library building module is further included, where the chip library building module is configured to build a chip library in response to an import operation performed on parameters of a chip, where the parameters include at least an electrical, a shape, a size, and a name of the chip.

after the setting module 4201, the system further includes a position adjustment module, configured to detect an initial placement position of the target chip in a canvas in response to the target chip being set in the canvas, where the canvas includes a plurality of grid cells arranged in an array, each grid cell in the plurality of grid cells being provided with a contact, and the contact is configured to characterize a contact point of an interposer;

In a possible implementation manner, the position adjustment module is further configured to detect whether the initial placement position is aligned with a preset reference position;

In a possible implementation manner, the position adjustment module is further configured to determine a plurality of candidate placement positions based on the initial placement position, where the plurality of candidate placement positions are obtained by taking the initial placement position as a starting point and moving the target chip by a second offset;

In one possible implementation, after the first display module 4202, a pin setting module is further included, where n is an integer greater than 1, for setting netlist names and routing types of pins in n component modules in the m target chips and interposer at the second display interface.

In one possible implementation, the pin setting module is further configured to hover display a pin setting window on the second display interface in response to a trigger operation performed for any of the n element modules in the m target chips and the interposer;

responding to trigger operation executed for netlist names and wiring types in a pin setting window which is displayed in a floating way on the second display interface, and displaying a netlist name input box or a netlist name list and a wiring type list in the pin setting window;

and responding to the input operation executed for the netlist name input box or the selection operation executed by the netlist name list and the selection operation executed by the wiring type list, and displaying a target netlist name identifier corresponding to the target netlist name at any pin in the second display interface.

In one possible implementation, the routing type includes:

a first wiring type, a second wiring type, and a third wiring type,

wherein the first wire type is used for characterizing routing through an interposer, the second wire type is used for characterizing routing through a rewiring layer, and the third wire type is used for characterizing routing through a rewiring layer and/or an interposer.

the device also comprises a tool selection module, wherein the tool selection module is used for responding to the selection operation executed by a cursor on any tool in the tool menu, and displaying the view of any tool at the cursor;

responsive to the cursor moving to any pin of the m target chips and n element modules in the interposer;

and responding to the triggering operation executed for any pin, and displaying the identification corresponding to any tool at any pin.

In one possible implementation, at least passive electronic components or contacts are included in the tool menu.

In one possible implementation manner, the target display interface includes a third display interface and a fourth display interface, and the target control includes a second control and a third control;

The second display module 4203 is configured to display the third display interface in response to a triggering operation performed by the second control in the second display interface, where the m target chips, an interposer, and a substrate are displayed in the third display interface, where a contact is displayed on the interposer, and a contact pad connectable to the contact is displayed on the substrate;

connecting wires of pins with the wiring type set as a first wiring type, and connecting wires of the contact points and the contact pads, which belong to the same target netlist name on the m target chips and the interposer;

responding to the triggering operation executed by the third control in the second display interface, displaying a fourth display interface, wherein the fourth display interface displays the m target chips, an interposer and a substrate, wherein the interposer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

and connecting wires of pins with the wiring type set as a second wiring type, and connecting wires of the contact points and the contact pads, wherein the m target chips and the interposer belong to the same target netlist name.

In one possible implementation of the present invention,

The device also comprises a fourth display module, wherein the fourth display module is used for responding to a triggering operation executed for a third wiring type in a pin setting window which is displayed in a floating way in the second display interface;

responding to a selection operation executed for a contact name list in the contact setting window;

and responding to a triggering operation executed for a second control in a second display interface, and displaying a third display interface, wherein the m target chips and connecting wires which belong to the same target netlist name and are arranged as pins of a third wiring type and are routed through an interposer are displayed in the third display interface.

In one possible implementation manner, the m target chips and connecting wires which belong to the same target netlist name and are routed through the interposer, of pins with the routing type set as a third routing type, are displayed in the third display interface;

and the fourth display interface displays the m target chips and the connecting wires which belong to the same target netlist name and are arranged as pins of a third wiring type and are routed through the rewiring layer on the intermediate layer.

In one possible implementation manner, the apparatus further includes a component setting module, where the component setting module is configured to

Responding to the selection operation executed for the component names in the component selection list on the toolbar in the second display interface, and displaying the component thumbnail at the cursor;

and responding to the triggering operation of the cursor to the intermediate layer, and setting the component in the intermediate layer.

In one possible implementation manner, the apparatus further includes a component operation module, where the component operation module is configured to respond to a selection operation performed on a component or a module on the interposer;

In one possible implementation manner, the apparatus further includes a stereoscopic view display module, where the stereoscopic view display module is configured to display a stereoscopic view corresponding to the wiring diagram in the target display interface in response to a triggering operation performed on the fourth control in the second display interface.

In a possible implementation manner, the device further includes a file generation module, where the file generation module is configured to respond to a triggering operation performed on a fifth control in the first display interface, and output different types of files corresponding to the wiring diagram.

Fig. 43 is a schematic diagram of a terminal according to an embodiment of the present invention. As shown in fig. 43, the terminal 43 of this embodiment includes: a processor 4301, a memory 4302, and a computer program 4303 stored in the memory 4302 and executable on the processor 4301. The processor 4301, when executing the computer program 4303, implements the steps of the various display method embodiments described above, such as steps 2401 to 2403 shown in fig. 24. Alternatively, the processor 4301, when executing the computer program 4303, performs the functions of the modules/units in the display apparatus embodiment described above, such as the functions of modules/units 4201 through 4203 shown in fig. 42.

The present invention also provides a readable storage medium having stored therein a computer program for implementing the display method provided in the above-described various embodiments when the computer program is executed by a processor.

The readable storage medium may be a computer storage medium or a communication medium. Communication media includes any medium that facilitates transfer of a computer program from one place to another. Computer storage media can be any available media that can be accessed by a general purpose or special purpose computer. For example, a readable storage medium is coupled to the processor such that the processor can read information from, and write information to, the readable storage medium. In the alternative, the readable storage medium may be integral to the processor. The processor and the readable storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC). In addition, the ASIC may reside in a user device. The processor and the readable storage medium may reside as discrete components in a communication device. The readable storage medium may be read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tape, floppy disk, optical data storage device, etc.

The present invention also provides a program product comprising execution instructions stored in a readable storage medium. The at least one processor of the device may read the execution instructions from the readable storage medium, and execution of the execution instructions by the at least one processor causes the device to implement the display methods provided by the various embodiments described above.

In the above described embodiments of the apparatus, it is understood that the processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims

1. A display method, comprising:

m target chips and an interposer are arranged in a canvas of a first display interface, wherein m is an integer greater than 1;

responding to a triggering operation executed for a first control in the first display interface, and displaying the m target chips and the interposer on a second display interface;

responding to a triggering operation executed for a target control in the second display interface, displaying a wiring diagram on a target display interface, wherein the wiring diagram is generated based on netlist names and wiring types of pins corresponding to the m target chips and an interposer, and the wiring diagram displayed on the target display interface is used for displaying connecting wires of pins which belong to the same target netlist name and are set to be of the same wiring type on the m target chips and the interposer;

the responding to the triggering operation executed for the first control in the first display interface, after the m target chips and the intermediary layers are displayed on the second display interface, further comprises:

setting netlist names and wiring types of pins in n element modules in the m target chips and the interposer on the second display interface, wherein n is an integer greater than 1;

The setting, on the second display interface, netlist names and routing types of pins in n element modules in the m target chips and the interposer includes:

suspending a display pin setup window at the second display interface in response to a trigger operation performed for any pin of the n element modules in the m target chips and the interposer;

and displaying a target netlist name identifier corresponding to the target netlist name at any pin in the second display interface in response to an input operation performed on the netlist name input box or a selection operation performed on a netlist name list and a selection operation performed on a wiring type list.

2. The display method of claim 1, wherein the responding to the m target chips being disposed in the canvas of the first display interface further comprises:

for each target chip of the m target chips, responding to a selection operation executed for a chip name in a chip type selection list in a toolbar in the first display interface, and acquiring the target chip;

3. The display method of claim 2, wherein the obtaining the target chip in response to a selection operation performed for a chip name in a chip-type list in a toolbar in the first display interface further comprises:

in response to an import operation performed on parameters of a chip, a chip library is established, wherein the parameters at least comprise the electrical, shape, size, name of the chip.

4. The display method of claim 3, wherein the target placement position is an initial placement position of the target chip in the canvas;

after the m target chips are set in the canvas of the first display interface, the method further comprises the following steps:

Detecting an initial placement position of the target chip in a canvas in response to the target chip being arranged in the canvas, wherein the canvas comprises a plurality of grid cells arranged in an array, each grid cell in the plurality of grid cells is provided with a contact point, and the contact point is used for representing a contact point of an interposer;

5. The display method of claim 4, wherein determining the target placement position corresponding to the target chip based on the initial placement position comprises:

6. The display method of claim 5, wherein determining the target placement position corresponding to the target chip based on the initial placement position comprises:

determining a plurality of candidate placement positions based on the initial placement positions, wherein the candidate placement positions are obtained by taking the initial placement positions as starting points and moving the target chip by a second offset;

7. The display method of claim 1, wherein the wiring type comprises:

a first wiring type, a second wiring type, and a third wiring type,

8. The display method of claim 7, wherein the second display interface further comprises a tool menu bar;

displaying a view of any tool in the tool menu at a cursor in response to a selection operation performed by the cursor for the any tool;

9. The display method of claim 8, wherein the tool menu includes at least passive electronic components or contacts.

10. The display method of claim 9, wherein the target display interface comprises a third display interface and a fourth display interface, and the target control comprises a second control and a third control;

the responding to the triggering operation executed for the target control in the second display interface displays a wiring diagram on the target display interface, and the method comprises the following steps:

responding to the triggering operation executed by the second control in a second display interface, displaying a third display interface, wherein the m target chips, an interposer and a substrate are displayed in the third display interface, the interposer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

11. The display method of claim 10, wherein,

responding to a trigger operation executed for a third wiring type in a pin setting window which is displayed in a floating mode in the second display interface;

12. The display method of claim 11, wherein,

the m target chips and connecting wires which belong to the same target netlist name and are routed through the interposer, wherein the routing type of the connecting wires is set as pins of a third routing type, are displayed in the third display interface;

13. The display method of claim 1, wherein the interposer includes at least a power management module, a communication interface module, a control module, and a level shifter.

14. The display method of claim 1, wherein the method further comprises:

15. The display method of claim 14, wherein the method further comprises:

16. The display method of claim 15, wherein the method further comprises:

17. The display method of claim 1, wherein the method further comprises:

18. A display device, comprising:

the setting module is used for setting m target chips and an intermediate layer in canvas of the first display interface, wherein m is an integer greater than 1;

the first display module is used for responding to the triggering operation executed for the first control in the first display interface and displaying the m target chips and the intermediary layers on the second display interface;

the second display module is used for responding to the triggering operation executed for the target control in the second display interface and displaying a wiring diagram on the target display interface, wherein the wiring diagram is generated based on the netlist names and the wiring types of the pins corresponding to the m target chips and the interposer, and the wiring diagram displayed on the target display interface is used for displaying connecting wires of the pins which belong to the same target netlist name and are set to be of the same wiring type on the m target chips and the interposer;

19. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the display method according to any one of claims 1 to 17 when the computer program is executed.

20. A computer readable storage medium storing a computer program, characterized in that the computer program realizes the steps of the display method according to any one of claims 1 to 17 when the computer program is executed by a processor.