CN115688672A

CN115688672A - Display method, display device, terminal and storage medium

Info

Publication number: CN115688672A
Application number: CN202211419988.6A
Authority: CN
Inventors: 许荣峰; 邵钏; 卢萧; 林哲民
Original assignee: Shanghai Chipler Chip Technology Co ltd; Shenzhen Qipule Chip Technology Co ltd
Current assignee: Shanghai Chipler Chip Technology Co ltd; Shenzhen Qipule Chip Technology Co ltd
Priority date: 2022-11-14
Filing date: 2022-11-14
Publication date: 2023-02-03
Anticipated expiration: 2042-11-14
Also published as: CN115688672B

Abstract

The application discloses a display method, a display device, a terminal and a storage medium, wherein the method comprises the following steps: responding to that the m target chips and the intermediate layer are arranged in the canvas of the first display interface; in response to a trigger operation executed for a first control in the first display interface, displaying the m target chips and the interposer on a second display interface; and displaying the wiring diagram on the target display interface in response to the triggering operation executed aiming at the target control in the second display interface. According to the invention, the position relations and the pin relations between the m target chips and the interposer are sequentially set through the first display interface and the second display interface, so that the automatic connection between the chips and the interposer is realized, and the wiring efficiency is improved. In addition, the invention also generates different wiring diagrams aiming at the netlist name and the signal type of different pins through the set pin relation, namely the netlist name and the signal type of the pin, so that the wiring between the chip and the intermediate layer is clear, and the user experience is improved.

Description

Display method, display device, terminal and storage medium

Technical Field

The present application relates to the field of EDA technologies, and in particular, to a display method, an apparatus, a terminal, and a storage medium.

Background

The chipset technology is to decompose Soc (System on Chip) into a plurality of smaller chiplets, wherein the chiplets can have different functions and processes, and then package the modularized chiplets together by using a novel packaging technology to realize interconnection of the chiplets, i.e. to form a heterogeneous integrated Chip.

In order to realize wide application of the chipset technology, the chipset technology is applied to EDA (Electronic design automation). At present, the application of the chipset technology to the EDA mainly includes the operations of selecting, placing, and wiring the chiplets, which are basically realized manually, that is, an experienced designer manually realizes the operations of selecting, placing, and wiring the chiplets based on the customer requirements.

However, the above-mentioned application of the chipset technology to the EDA cannot be automated, so that the resource cost such as labor and time is increased, and further the resource cost is high.

Disclosure of Invention

The present application mainly aims to provide a display method, device, terminal and storage medium to solve the problem of high resource cost in the related art.

In order to achieve the above object, in a first aspect, the present application provides a display method comprising:

responding to that m target chips and a middle layer are arranged in a canvas of a first display interface, wherein m is an integer larger than 1;

in response to a trigger operation executed for a first control in a first display interface, displaying m target chips and a middle layer on a second display interface;

and in response to a trigger operation executed for the target control in the second display interface, displaying a wiring diagram on the target display interface, wherein the wiring diagram is generated based on the net list names and the wiring types of the m target chips and the pins corresponding to the intermediate layers.

In one possible implementation manner, in response to that the m target chips are arranged in front of the canvas of the first display interface, the method further includes:

for each target chip in the m target chips, responding to a selection operation executed for a chip name in a chip type selection list in a toolbar in the first display interface, and acquiring the target chip;

responding to a first interaction event of a cursor, and displaying an angle placing menu of a target element, wherein the angle placing menu comprises a plurality of preset placing angles;

responding to a first selection event of a cursor, and displaying a preview of a target chip under a target placing angle, wherein the target placing angle is one of a plurality of preset placing angles;

and responding to a second selection event of the cursor, and generating a design drawing of the target chip at the target placing angle at the target position in the canvas area.

In a possible implementation manner, before acquiring the target chip in response to the selection operation performed on the chip name in the chip type list in the toolbar in the first display interface, the method further includes:

a chip library is established in response to an import operation performed on parameters of a chip, wherein the parameters include at least an electrical property, a shape, a size, a name of the chip.

In one possible implementation manner, the target placement position is an initial placement position of the target chip in the canvas;

after the m target chips are set in the canvas of the first display interface, the method further comprises the following steps:

responding to the target chip arranged in the canvas, and detecting the initial placement position of the target chip in the canvas, wherein the canvas comprises a plurality of grid units arranged in an array, each grid unit in the grid units is provided with a joint, and the joints are used for representing the contact points of the interposer;

and determining a target placing position corresponding to the target chip based on the initial placing position, and adjusting the target chip to the target placing position.

In one possible implementation manner, determining a target placement position corresponding to a target chip based on an initial placement position includes:

detecting whether the initial placing position is aligned with a preset reference position;

and if the initial placing position is aligned with the preset reference position, taking the initial placing position as a target placing position corresponding to the target chip.

determining a plurality of candidate placing positions based on the initial placing position, wherein the candidate placing positions are obtained by taking the initial placing position as a starting point and moving the target chip by using a second offset;

based on the initial pose position and the plurality of candidate pose positions, a target pose position is determined.

In one possible implementation, after the m target chips and the interposer are displayed on the second display interface in response to a trigger operation performed on the first control in the first display interface, the method further includes:

and setting net list names and wiring types of pins in n element modules in the m target chips and the intermediate layers on a second display interface, wherein n is an integer larger than 1.

In one possible implementation, setting netlist names and wiring types of pins in n component modules in m target chips and interposer on a second display interface includes:

in response to a trigger operation executed on any pin of the n element modules in the m target chips and the interposer, displaying a pin setting window in a floating mode on a second display interface;

in response to a trigger operation executed for the netlist name and the wiring type in the pin setting window displayed in a floating mode on the second display interface, displaying a netlist name input box or a netlist name list and a wiring type list in the pin setting window;

and in response to the input operation executed for the netlist name input box or the selection operation executed for the netlist name list and the selection operation executed for the routing type list, displaying the target netlist name identification corresponding to the target netlist name at any pin in the second display interface.

In one possible implementation, the wiring types include:

a first wiring type, a second wiring type and a third wiring type,

the first routing type is used for representing routing through the interposer, the second routing type is used for representing routing through the rewiring layer, and the third routing type is used for representing routing through the rewiring layer and/or the interposer.

In one possible implementation, the second display interface further includes a tool menu bar;

displaying a view of any tool at the cursor in response to a selection operation performed by the cursor for any tool in the tool menu;

responding to the cursor moving to any pin in the m target chips and the n element modules in the intermediate layer;

and displaying the corresponding identification of any tool at any pin in response to the trigger operation executed for any pin.

In one possible implementation, at least passive electronic components or contacts are included in the tool menu.

In one possible implementation manner, the target display interface includes a third display interface and a fourth display interface, and the target control includes a second control and a third control;

in response to a trigger operation executed for a target control in the second display interface, displaying a wiring diagram on the target display interface, wherein the method comprises the following steps:

responding to a trigger operation executed by a second control in the second display interface, and displaying a third display interface, wherein m target chips, an intermediate layer and a substrate are displayed in the third display interface, wherein joints are displayed on the intermediate layer, and joint pads which can be connected with the joints are displayed on the substrate;

the m target chips and the intermediate layer belong to the same target netlist name, and the wiring type is set as the connecting line of the first wiring type pin, and the connecting line of the contact and the contact pad;

responding to a trigger operation executed by a third control element in the second display interface, and displaying a fourth display interface, wherein the fourth display interface displays m target chips, an intermediate layer and a substrate, the intermediate layer displays a contact, and the substrate displays a contact pad which can be connected with the contact;

the m target chips and the connecting lines of the pins which belong to the same target netlist name and have wiring types set as second wiring types on the intermediate layer, and the connecting lines of the contacts and the contact pads.

In one possible implementation, in response to a trigger operation performed for a third wiring type in a pin setting window that is floating displayed in the second display interface;

responding to a selection operation executed aiming at a contact name list in the contact setting window;

and in response to a trigger operation executed for a second control in the second display interface, displaying a third display interface, wherein the third display interface displays m target chips and connecting lines of pins which belong to the same target netlist name and are arranged in a third wiring type on the intermediate layer and are routed through the intermediate layer.

In one possible implementation manner, connecting lines which belong to the same target netlist name and have wiring types set as pins of a third wiring type and are routed through the interposer on the m target chips and the interposer are displayed in a third display interface;

and displaying the m target chips and the connecting lines of the pins which belong to the same target netlist name and have the wiring types set as the third wiring types and are wired through the rewiring layer on the intermediate layer in the fourth display interface.

In a possible implementation manner, the intermediary layer at least internally comprises a power management module, a communication interface module, a control module and a level shifter.

In one possible implementation, the method further includes:

displaying a component thumbnail at a cursor in response to a selection operation performed on a component name in a component selection list on a toolbar in the second display interface;

and setting the component in the intermediate layer in response to a trigger operation performed by the cursor on the intermediate layer.

In one possible implementation, the method further includes:

responding to a selection operation executed for a component or a module on the intermediate layer;

components or modules are deleted from the interposer in response to a delete operation performed on the selected component or module.

In one possible implementation, the method further includes:

and responding to the triggering operation executed aiming at the fourth control in the second display interface, and displaying the stereoscopic view corresponding to the wiring diagram in the target display interface.

In one possible implementation, the method further comprises:

and outputting different types of files corresponding to the wiring diagram in response to the triggering operation executed for the fifth control in the first display interface.

In a second aspect, an embodiment of the present invention provides a display device, including:

the setting module is used for responding to the setting of m target chips in the canvas of the first display interface, wherein m is an integer larger than 1;

the first display module is used for responding to a trigger operation executed aiming at a first control in a first display interface and displaying m target chips and a medium layer on a second display interface;

and the second display module is used for responding to a trigger operation executed aiming at a target control in the second display interface and displaying a wiring diagram on the target display interface, wherein the wiring diagram is generated based on the net list names and the wiring types of the pins corresponding to the m target chips and the intermediate layers.

In a third aspect, an embodiment of the present invention provides a terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of any one of the display methods when executing the computer program.

In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above display methods are implemented.

The embodiment of the invention provides a display method, a display device, a terminal and a storage medium, wherein the display method comprises the following steps: the method comprises the steps of firstly responding to the fact that m target chips and a middle layer are arranged in a canvas of a first display interface, then responding to a trigger operation executed aiming at a first control in the first display interface, displaying the m target chips and the middle layer on a second display interface, and then responding to the trigger operation executed aiming at the target control in the second display interface, and displaying a wiring diagram on the target display interface. The invention sets the position relation and the pin relation of the m target chips and the medium layer sequentially through the first display interface and the second display interface, realizes the automatic connection between the chips and the medium layer and improves the wiring efficiency. In addition, the invention also generates different wiring diagrams aiming at the netlist name and the signal type of different pins through the set pin relation, namely the netlist name and the signal type of the pin, so that the wiring between the chip and the intermediate layer is clear, and the user experience is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, serve to provide a further understanding of the application and to enable other features, objects, and advantages of the application to be more apparent. The drawings and the description of the exemplary embodiments of the present application are provided for explaining the present application and do not constitute an undue limitation on the present application. In the drawings:

FIG. 1 is a diagram of a chip library menu bar according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a design page of existing EDA software provided by an embodiment of the present invention;

fig. 3 is a flowchart illustrating an implementation of a component placement method according to an embodiment of the present invention;

FIG. 4 is a diagram of a setup page of an angle put menu of a target element according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a preview button provided by embodiments of the present invention;

FIG. 6 is a schematic diagram of a setup page with a target element selected to have 180 degrees as a placing angle according to an embodiment of the present invention;

FIG. 7 is a diagram of a preview of a target element provided by an embodiment of the invention;

FIG. 8 is a diagram of a canvas provided by an embodiment of the present invention;

FIG. 9 is a diagram of generating a target element plan within a canvas according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a design page with components placed on an active silicon substrate according to an embodiment of the invention;

FIG. 11 is a schematic diagram of an embodiment of the present invention showing a device placed on an active silicon substrate;

fig. 12 is a flowchart illustrating an implementation of a method for adjusting a chip position according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a chiplet U9 provided by an embodiment of the present invention;

FIG. 14 is a schematic diagram of a chiplet U2 provided with an embodiment of the present invention;

FIG. 15 is a schematic diagram of a chiplet U23 provided with an embodiment of the present invention;

FIG. 16 is a schematic diagram of a chiplet U1 provided with an embodiment of the present invention;

FIG. 17 is a schematic diagram of a positional relationship between a chiplet U9 and a canvas according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of a chiplet U9 misaligned from a reference position provided by an embodiment of the present invention;

FIG. 19 is a schematic diagram of alignment of a chiplet U9 with a reference location provided by an embodiment of the present invention

FIG. 20 is a schematic diagram of the positional relationship of a chiplet U9 with multiple reference locations provided by an embodiment of the present invention;

FIG. 21 is a schematic diagram of a chiplet U2 disposed at an initial placement position E according to an embodiment of the present invention;

FIG. 22 is a schematic diagram of a chiplet U2 disposed at a first candidate placement position F according to an embodiment of the present invention;

FIG. 23 is a schematic diagram of a chiplet U2 disposed at a second candidate placement position G according to an embodiment of the present invention;

FIG. 24 is a flowchart illustrating an implementation of a display method according to an embodiment of the present invention;

FIG. 25 is a schematic diagram of a first display interface provided by an embodiment of the invention;

FIG. 26 is a diagram illustrating a pin setup window according to an embodiment of the invention;

FIG. 27 is a diagram illustrating a pin setup window according to another embodiment of the invention;

FIG. 28 is a diagram illustrating a pin setup window according to another embodiment of the invention;

FIG. 29 is a schematic diagram of a chiplet U12 provided in accordance with an embodiment of the present invention;

FIG. 30 is a diagram of a tool menu bar provided by an embodiment of the present invention;

fig. 31 is a schematic diagram of a resistance value setting window according to an embodiment of the present invention;

FIG. 32 is a schematic diagram of a chiplet U12 provided in accordance with another embodiment of the present invention;

fig. 33 is a schematic view of a contact placement window provided in accordance with an embodiment of the present invention;

FIG. 34 is a diagram illustrating a contact name list provided by an embodiment of the invention;

fig. 35 is a schematic view of a contact placement window provided in accordance with another embodiment of the present invention;

FIG. 36 is a diagram illustrating a second display interface provided by an embodiment of the invention;

FIG. 37 is a schematic diagram of a third display interface provided in accordance with an embodiment of the invention;

FIG. 38 is a schematic view of a second display interface provided in accordance with another embodiment of the present invention;

FIG. 39 is a schematic diagram of a third display interface provided in accordance with another embodiment of the invention;

fig. 40 is a schematic diagram of a wiring switching button provided by an embodiment of the present invention;

FIG. 41 is a schematic diagram of an interposer provided by an embodiment of the invention;

fig. 42 is a schematic structural diagram of a display device according to an embodiment of the present invention;

fig. 43 is a schematic diagram of a terminal according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.

It should be understood that, in various embodiments of the present invention, the sequence numbers of the processes do not mean the execution sequence, and the execution sequence of the processes should be determined by the functions and the internal logic of the processes, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

It should be understood that in the present application, "comprising" and "having" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that, in the present invention, "a plurality" means two or more. "and/or" is merely an association describing an associated object, meaning that three relationships may exist, for example, and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "comprising a, B and C", "comprising a, B, C" means that all three of a, B, C are comprised, "comprising a, B or C" means comprising one of three of a, B, C, "comprising a, B and/or C" means comprising any 1 or any 2 or 3 of three of a, B, C.

It should be understood that in the present invention, "B corresponding to a", "a corresponds to B", or "B corresponds to a" means that B is associated with a, and B can be determined from a. Determining B from a does not mean determining B from a alone, but may also be determined from a and/or other information. And the matching of A and B means that the similarity of A and B is greater than or equal to a preset threshold value.

As used herein, the term "if" may be interpreted as "at \8230; …" or "in response to a determination" or "in response to a detection" depending on the context.

The technical solution of the present invention will be described in detail below with specific examples. These several specific embodiments may be combined with each other below, and details of the same or similar concepts or processes may not be repeated in some embodiments.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description is made by way of specific embodiments with reference to the accompanying drawings.

The display method is applied to an EDA tool and mainly realized through four steps of chip selection, chip placement, chip position adjustment and wiring, and the four steps are executed according to a sequence.

In the EDA tool of the present application, a chip Library (chip Library) as shown in fig. 1 is provided, and the chip Library includes various chips, such as a power chip, a processor chip, and the like, and the chip Library is mainly established by importing parameters of each chip, such as electrical, shape, size, name, and the like of the chip, and then corresponding the parameters of each chip to the chip to form chip information of each chip, and storing the chip information of each chip to form a chip Library.

And when a user selects a chip by adopting an EDA tool, responding to the selection operation executed on the chip name in the chip selection list in the toolbar in the first display interface to obtain the target chip. The chip type selection list displays the names of all chips, and the chips can be selected by clicking the name of a certain chip.

With reference to fig. 1, a chip Library (chip Library) is disposed in the first display interface, and the MCU (controller) can be clicked to display various types of MCU chips for user selection. Meanwhile, due to the fact that the space of the first display interface is limited, if the chip which the user wants to select is not displayed on the first display interface, searching can be conducted through the search box.

After the chips are selected, the selected chips need to be arranged in the canvas, so that the chips are placed.

Existing EDA software, as shown in fig. 2, contains few controls on an EDA software page, where what is essential is an electrical toolbar and a drawing bar, where various types of elements are arranged in the electrical toolbar, and a user may click on an element that is to be placed on the canvas and then place the element in the canvas by dragging to perform subsequent hardware design.

However, because the existing EDA software does not have a setting control for the element placement angle, the placement angle of the element is usually zero degree by default, and the default angle may not be changed. If the placing angle of the element is required to be adjusted, the element can only be placed on the canvas firstly, and then the placing angle of the element is manually adjusted on the canvas. That is, the current component placement process can be simply expressed as: after the element is selected, a preview graph of the selected element is displayed at the cursor, then the cursor is moved to the position where the element is to be placed, the element can be placed at the position by clicking the cursor, and finally the placing angle of the element is manually adjusted.

For example, the user needs to place an element with a length of 30 × 20, the placement angle is rotated by 90 degrees, after the user selects an element, the user is not aware that the size of the preview graphic of the element displayed at the cursor is 40 × 20, and the user's requirement cannot be met, the user is required to re-select an element, and if the size of the re-selected element is still not right, the user is required to continue to select the element, and the whole process is not user-friendly, which affects the user experience of the EDA.

Therefore, the above-mentioned element placing process is not friendly in some application scenarios that have requirements on the placing angle of the element and the shape of the element, and is complex to operate.

Based on the above problems, the application provides a component placing method, which is convenient and fast to operate, and can improve component placing efficiency and improve user experience.

In one embodiment, as shown in fig. 3, there is provided a method for placing components, comprising the steps of:

step S301: and displaying the angle placing menu of the target element in response to the first interaction event of the cursor.

The cursor is a mouse arrow used for identifying a mouse position on the graphical interface, wherein the mouse arrow may include a plurality of forms, such as an arrow form, an I form during text input, a little hand form, and the like.

The interaction events include, but are not limited to, a dwell, a selection, a click, etc., and in the case where the first interaction event is a dwell event, the dwell event means that a cursor is displayed on a preview button of the target element. For the stay event, the stay time can be set, that is, when the cursor stays on the preview button of the target element for a preset time, the cursor will respond to the stay event; when the cursor simply slides quickly over the preview button of the target element and does not reach the preset duration, no response is made to the event. The preset time period may be set according to specific situations, and is not limited herein.

According to the method and the device, after a user clicks the target element through a cursor, a preview of the target element with a default angle (0 degree) is generated. If the target element is desired to be placed at other angles in the canvas, the angular placement menu of the target element is presented at the preview button in response to a cursor dwell event on the preview button of the target element.

After the angle placing menu is expanded, the list of the angles can be displayed for a single angle list or through a plurality of angle areas. The angle areas are used for displaying a plurality of preset placing angles, and the angle areas correspond to the preset placing angles one to one. That is, a plurality of angle areas are set in the angle-placing menu, and each angle area corresponds to one placing angle (i.e. a preset angle). Wherein, a plurality of preset put the angle inequality, a plurality of can be 5, 7 etc. do not do specific limit here, can set up according to specific demand.

Illustratively, when the cursor is moved over the preview button in FIG. 4 (as shown in FIG. 5) and the dwell time exceeds the preset dwell time period, the angular drop menu of the target element may be presented (popped up) at the preview button in response to the dwell event.

If the preview of the target element at the target placing angle is to be displayed at the cursor, the preview of the target element at the target placing angle needs to be displayed in response to the second interaction event of the cursor.

And under the condition that the second interaction event refers to the stopping event of the cursor at the target placing angle, if the stopping event of the cursor at the target placing angle is responded, displaying a preview of the target element at the target placing angle at the cursor. Wherein, the preview picture takes the position of the cursor as the center to move along with the cursor.

Illustratively, in conjunction with fig. 6, the angular placement menu lists the placement angles of 4 selectable elements, such as 0 degrees, 90 degrees, 180 degrees, and 270 degrees. When the cursor is moved to an angle area corresponding to 180 degrees in the angle placing menu, namely a cursor staying event at 180 degrees, the aspect ratio of the target element is adjusted through the selected 180 degrees, and a preview of the element at 180 degrees is displayed at the cursor.

The aspect ratio of the target element is set according to specific conditions, for example, at 0 degree, the vertical edge pixels and the horizontal edge pixels of the target element are respectively 200 and 100, and at 90 degrees, the vertical edge pixels and the horizontal edge pixels of the target element are changed to be 100 and 200, and the like.

In addition, if the angle placing menu is desired to be hidden, only the second interaction event needs to be stopped, that is, the angle placing menu of the target element is hidden in response to the moving-away event of the cursor at the target placing angle.

Step S302: and responding to a first selection event of the cursor, and displaying a preview of the target element under the target placing angle.

The first selection event refers to an event which is selected in a cursor clicking mode, wherein the cursor clicking mode comprises left key clicking, right key clicking, left key one-click clicking, left key two-click clicking and the like.

And in the case that the cursor clicking mode is left key clicking, responding to a selection event of the target placing angle through the left key of the cursor, and displaying a preview of the target element at the target placing angle at the cursor, wherein the preview moves along with the cursor by taking the position of the cursor as a center.

Exemplarily, referring to fig. 7, taking the target element as a chip and the target placement angle as 90 degrees as an example, when the cursor is moved to an angle area corresponding to 90 degrees in the angle placement menu and then the placement angle 90 degrees is selected by clicking the left key of the cursor, a preview of the chip at 90 degrees is displayed at the cursor, and the model of the chip, that is, the TMP108AIYFFT, is displayed in the preview.

Of course, after the preview of the target element at the target placement angle is displayed after the selection is clicked through the left key of the cursor, if the preview of the target element at the target placement angle is hidden, the preview of the target element at the target placement angle needs to be hidden and displayed at the cursor in response to the event of canceling the selection of the target placement angle through the right key of the cursor.

Illustratively, taking the target placement angle as 90 degrees as an example, when the placement angle is 90 degrees is selected by left key click of the cursor, a preview of the target element at 90 degrees is displayed at the cursor. Then, clicking at 90 degrees through the right button of the cursor, namely deselecting, can hide the preview image of the display target element at 90 degrees at the cursor.

Step S303: and responding to a second selection event of the cursor, and generating a design drawing of the target element at the target placing angle at the target position in the canvas area.

The second selection event is similar to the first selection event, and also refers to an event that is selected by clicking a cursor, but objects acted by the two selection events are different. The cursor clicking mode comprises left click, right click, one-click left click, two-click left click and the like.

And under the condition that the cursor clicking mode is left key clicking, responding to a selection event of the left key of the cursor on the target position in the canvas area, and generating a design drawing of the target element at the target placing angle at the target position in the canvas area.

For example, taking the target placement angle as 90 degrees as an example, when a left key of the cursor is clicked at 90 degrees, a preview of the target element at 90 degrees can be displayed at the cursor, then the cursor is moved into a physical view (canvas) as shown in fig. 8, and a certain position in the canvas is clicked by the left key of the cursor, then the position is selected as the target position, and then the target position in the canvas area automatically generates a design diagram of the target element at the target placement angle, wherein the design diagram is shown in fig. 9.

When the element placing method in the application is applied to the chiplet technology-based EDA software, a user can preview a preview image of a target element to be placed at each angle through the method, and then select the target element at a proper angle to place the target element on the drawing board. The drawing board may be mapped to a surface of the active silicon substrate on which the target element is placed, and the position of the target element on the drawing board and the placement angle of the target element when the target element is placed may be mapped to the position of the target element on the active silicon substrate and the placement angle of the target element when the target element is placed on the active silicon substrate in an actual chip package. For example, referring to fig. 10, in the EDA software, the component a is placed at the upper left corner of the canvas at a placement angle of 0 degree by the method, that is, in the chip finally manufactured according to the design of EDA, the component a will be placed at the upper left corner of the active silicon substrate at a placement angle of 0 degree. The design of EDA in FIG. 10 is used to make the chip object diagram shown in FIG. 11.

In addition, if the current target element is not selected for the first time, after the target element is arranged in the canvas and a design drawing of the target element at the target placing angle is generated, the historical placing condition of the target element, such as the previous placing angle, the previous placing position and the like of the target element, is displayed on the design drawing.

If other elements are already present in the canvas when the target element is selected, recommendations of placing angles, positions and the like are provided for the target element according to the placing conditions of the other elements which are present.

After the selected chip is arranged in the canvas, whether the position where the chip is placed is proper or not needs to be confirmed, and if not, the position of the chip needs to be adjusted.

Existing EDA software, as shown in fig. 2, contains few controls on an EDA software page, where what is essential is an electrical toolbar and a drawing bar, where various types of elements are arranged in the electrical toolbar, and a user may click on an element that is to be placed on the canvas and then place the element in the canvas by dragging to perform subsequent hardware design. Wherein the component includes, but is not limited to, a chiplet.

However, because the existing EDA software does not have the functions of automatically detecting and adjusting the placement position of the chiplets, the design personnel is generally required to place the chiplets according to the accumulated experience to achieve the accuracy of the placement position of the chiplets. However, for inexperienced designers, after the designers set the chiplets in the canvas of the EDA software, the designers need to observe whether the placement positions of the chiplets are accurate, and if the placement positions are not accurate, the designers need to manually adjust the placement positions of the chiplets.

Therefore, a great deal of time is needed for designers to finish placing the small chips, and the working efficiency is reduced.

Based on the above problems, the application provides a chip position adjusting method, which can automatically detect and adjust the placement position of a chip, and improve the working efficiency of designers.

In one embodiment, as shown in fig. 12, there is provided a chip position adjusting method, including the steps of:

step S1201: and responding to the target chip arranged in the canvas, and detecting the initial placing position of the target chip in the canvas.

The target chip refers to a small chip or a core particle with any function, and includes an outer frame and a plurality of chip contacts, and the type and name of the small chip are displayed around the outer frame, and the type of the small chip is U9 and the name of the small chip is TMP108AIYFFT as shown in fig. 13.

For different types of chiplets, the parameters of the chip contacts corresponding to the chiplets are different, and the parameters of the chip contacts can be set in a chip library of the EDA tool. The parameters of the chip contacts at least include the arrangement mode of the chip contacts, the number of the chip contacts and the radius of the chip contacts.

Referring to fig. 13-16, the arrangement of the chip contacts in the chiplet U9 in fig. 13 is a regular arrangement (i.e. 2 × 3 arrangement), and the number of the chip contacts is 6; the arrangement of the chip contacts in the chiplet U2 in fig. 14 is irregular and the number of the chip contacts is 12; the arrangement of the chip contacts in the chiplet U23 in fig. 15 is a regular arrangement (i.e. 4 by 5 arrangement), the number of the chip contacts is 20; the arrangement of the die contacts in the chiplet U1 in fig. 16 is a regular arrangement (i.e. 2 x 2 arrangement). Furthermore. The radii of the chip contacts in the chiplets shown in FIGS. 13-16 are different, with the radius of the chip contact in the chiplet shown in FIG. 16 being the largest and the radius of the chip contact in the chiplet shown in FIG. 13 being the smallest.

The canvas comprises a plurality of grid units which are arranged in an array, each grid unit in the grid units is provided with a contact point, and the contact points are used for representing contact points of the active silicon substrate.

As shown in fig. 17, the plurality of contact points arranged in an array in the canvas of the EDA tool are metal bump (i.e., contact points) on the active silicon substrate. The active silicon substrate is provided with a programmable routing network, and the connection between the metal bump on the active silicon substrate can be freely set by programming the programmable routing.

Taking the target chip as the chiplet U9 as an example, after the designer selects the chiplet U9 in the chip library, the designer drags the chiplet U9 into the canvas by manually operating the mouse. At this time, when it is detected that the chiplet U9 is set in the canvas, a response is made, that is, an initial placement position of the chiplet U9 in the canvas is automatically detected, where the initial placement position may be a coordinate of a certain point in the chiplet in the canvas.

This application adopts the coordinate of a certain point in the chiplet in the canvas as initial locating position, and the reason is as follows: in the case of determining the type of the chiplet, knowing the coordinates of a certain point in the chiplet in the canvas allows the coordinates of the points in the chiplet in the canvas to be determined continuously. For example, only the coordinates of the lower left corner of the chiplet are used as the initial placement position, and after the coordinates of the lower left corner of the chiplet are determined, the coordinates of each point on the chiplet, even the coordinates of the center of the chip contact, can be calculated based on the type of the chiplet. The position of the small chip is represented by the coordinate of a certain point, and subsequent calculation processing is performed, so that the data processing amount is reduced, and the processing speed is improved.

In addition, when the chiplet U9 is placed in the canvas, the chip contacts in the chiplet U9 contact (communicate) with the metal bumps on the active silicon substrate so that signals can be transmitted between the chiplet and the active silicon substrate.

It should be noted that, because the radius of the chip contacts in the chiplet is different due to the different types of chiplets, the overlapping area of the chip contacts in the chiplet and the contacts in the canvas is different when the chiplet is disposed in the canvas.

Step S1202: and determining a target placing position corresponding to the target chip based on the initial placing position, and adjusting the target chip to the target placing position.

When the design of the small chip placing position is carried out by using the EDA tool, when a designer pulls a target chip through a mouse, the chip contact of the small chip and the metal bump of the active silicon substrate cannot be well aligned or have a better placing position, so the target placing position needs to be determined based on the initial placing position, the automatic adjustment function aiming at the placing position of the small chip is set in the EDA tool, the design efficiency and the design effect are improved, and the design difficulty is reduced.

The target placing position of the target chip is determined through two modes, specifically as follows:

the first mode is as follows: detecting whether the initial placing position is aligned with a preset reference position, and if the initial placing position is aligned with the preset reference position, taking the initial placing position as a target placing position corresponding to a target chip; and if the initial placing position is not aligned with the preset reference position, determining the target placing position in a mode of defining a search area based on the initial placing position.

Exemplarily, referring to fig. 18, a target chip is set as a chiplet U9, a vertex a of a lower left corner of an outer frame of the chiplet U9 is set as an initial placement position of the chiplet U9, and a grid point B closest to the initial placement position in a canvas is set as a preset reference position, and then, as can be seen from fig. 18, the vertex a of the lower left corner of the outer frame of the chiplet U9 is not aligned with the closest grid point B thereof, a search area can be defined based on the initial placement position to determine the target placement position, that is, whether a reference position exists in the search area formed by taking the initial placement position as a center and taking a first offset as a radius, and if a reference position exists in the search area, the target placement position is determined based on the number of reference positions and the initial placement position. The first offset may be set according to specific situations, and is not limited herein.

Further, with reference to fig. 18 to 19, if the number of the reference positions is one, that is, as shown in fig. 8, at grid point B, the reference position is set as the target placement position, and then the vertex a at the lower left corner of the outer frame of the chiplet U9 is adjusted to grid point B, as shown in fig. 19, so that the vertex at the lower left corner of the outer frame of the chiplet U9 coincides with grid point B.

If the number of reference positions is plural, as shown in fig. 20 as 3, including grid point B, grid point C, and grid point D, from the 3 reference positions: and selecting a position closest to the vertex A at the lower left corner of the outer frame of the small chip U9 from the grid points B, C and D as a target reference point, namely the grid point B, and taking the grid point B as a target placing position. Then, the vertex a of the lower left corner of the outer frame of the chiplet U9 is adjusted to grid point B, as shown in fig. 19, so that the vertex of the lower left corner of the outer frame of the chiplet U9 coincides with grid point B.

In addition, if no reference position exists in the search area, the first offset is expanded until the reference position is found in the search area formed by taking the initial placement position as the center and the expanded first offset as the radius, and the step of determining the target placement position based on the number of the reference positions and the initial placement position is performed.

Exemplarily, assuming that the first offset is a, when a search is performed by using the first offset a as a radius, the reference position is not found, and the first offset a may be enlarged by a preset multiple, where the preset multiple may be 2, 3, and the like, and is not limited herein. And when the preset multiple is 2, searching in a search area formed by taking the initial placing position as the center and taking 2a as the radius if the expanded first offset is 2a, if the reference position is found, determining the target placing position based on the number of the reference positions and the initial placing position, if one reference position is found, taking the reference position as the target placing position, and if a plurality of reference positions are found, selecting the reference position closest to the initial placing position as the target placing position. Optionally, when a plurality of reference positions are found, a suitable reference position may be selected as the target placement position according to various preset rules, for example, as far as possible away from an existing chiplet, as far as possible away from an edge of the active silicon substrate, and the like.

In addition, if the reference position is not found in the search area formed by taking the initial placing position as the center and taking the radius of 2a as the radius, the offset is continuously expanded, namely the reference position is found in the search area formed by taking the initial placing position as the center and taking the radius of 4a as the radius, and if the reference position is not found, the offset is continuously expanded until the reference position is found.

In this embodiment, this application not only automated inspection target chip's initial locating position to seek the reference position through initial locating position is automatic, and then confirm target chip's target locating position, realized the automation that target chip put, need not the designer and carry out manual operation, save designer's time, and then improved chip position adjustment, put the efficiency of work.

The second mode is as follows: and determining a plurality of candidate placing positions based on the initial placing position, wherein the plurality of candidate placing positions are obtained by moving the target chip by taking the initial placing position as a starting point and a second offset, and then determining the target placing position based on the initial placing position and the plurality of candidate placing positions. The second offset amount may be set according to specific situations, and is not limited herein.

For example, referring to fig. 21 to 23, assuming that the target chip is the chiplet U2, the initial placement position of the chiplet U2 is the point E in the canvas, and moving the chiplet U2 by using the second offset with the point E as the starting point, two placement position candidates can be obtained, the first placement position candidate being the point F shown in fig. 22 and the second placement position candidate being the point G shown in fig. 23. Then, the target placement position can be determined from the initial placement position E, the first placement position candidate F, and the second placement position candidate G.

After the initial placement position and the candidate placement positions are determined, the target placement position needs to be determined by calculating the overlapping area of all chip contacts in the target chip and all contacts corresponding to the initial placement position and the candidate placement positions. Specifically, the overlapping area of all chip contacts in the target chip and all contacts corresponding to the initial placement positions is calculated to obtain a first overlapping area, then the overlapping area of all chip contacts in the target chip and all contacts corresponding to each candidate placement position in the candidate placement positions is calculated to obtain a plurality of candidate overlapping areas, wherein the candidate placement positions are in one-to-one correspondence with the candidate overlapping areas, and then the first overlapping area and the candidate overlapping areas are compared to determine the target placement position.

Comparing the first overlapping area with the multiple candidate overlapping areas to determine a target placing position, wherein the two situations comprise that if the first overlapping area is larger than each candidate overlapping area in the multiple candidate overlapping areas, an initial placing position is used as the target placing position; and sequencing the first overlapping area and the plurality of candidate overlapping areas according to forward sequencing to obtain all sequenced overlapping areas, selecting the last overlapping area in all sequenced overlapping areas as a target overlapping area, and taking the placing position corresponding to the target overlapping area as a target placing position.

Exemplarily, with reference to fig. 21 to 23, the overlapping areas of 22 chip contacts in the chiplet U2 and all contacts corresponding to the initial placement position E, the first placement position candidate F, and the second placement position candidate G are calculated to obtain a first overlapping area S1, a first overlapping area candidate S2, and a second overlapping area candidate S3, respectively. If the first overlapping area S1 is larger than the first candidate overlapping area S2 and the second candidate overlapping area S3, taking an initial placing position E corresponding to the first overlapping area S1 as a target placing position; if the first overlap area S1< the first candidate overlap area S2< the second candidate overlap area S3, the second placement position candidate G corresponding to the second candidate overlap area S3, which is the maximum area, is used as the target placement position.

Further, a first overlapping area is obtained by calculating the overlapping area of all chip contacts in the target chip and all contacts corresponding to the initial placement position, multiple contacts corresponding to the chip contacts are obtained for each of the chip contacts in the target chip, the overlapping area of the chip contacts and each of the multiple contacts is determined based on the distance between the center of the chip contact and the center of the chip of each of the multiple contacts, the overlapping areas of the chip contacts and each of the multiple contacts are summarized and calculated to obtain the overlapping area corresponding to the chip contacts, and the overlapping areas corresponding to all the chip contacts are summed and calculated to obtain the first overlapping area.

The overlapping area of the chip contact and each contact in the plurality of contacts is determined based on the distance between the circle center of the chip contact and the circle center of each contact in the plurality of contacts, a distance interval to which the distance between the circle center of the chip contact and the circle center of the contact belongs needs to be determined for each contact in the plurality of contacts, then the area corresponding to the distance interval is obtained, and the area is used as the overlapping area of the chip contact and the contact. The overlapping area is calculated in such a way, the calculation speed can be guaranteed to a certain degree under the condition that the calculation accuracy of the overlapping area is guaranteed, the calculation amount is reduced to a certain degree, and therefore the speed of determining the target placement position is improved.

Illustratively, referring to fig. 21, taking the first chip contact in the upper left corner of the chiplet U2 as an example, it can be seen from fig. 21 that the first chip contact in the upper left corner covers a plurality of contacts in the canvas. Because the first chip contact in the upper left corner only partially covers some contacts in the canvas, the overlapping area at this moment is difficult to calculate accurately, therefore, the overlapping area is determined through the distance interval to which the distance between the circle center of the first chip contact in the upper left corner and the circle center of the contact in the canvas belongs.

Specifically, a first distance interval is set to be [0-1.5cm ], and the corresponding area is L1; the second distance interval is [1.6-2cm ], and the corresponding area is L2; the third distance interval is [2.1-2.5cm ], and the corresponding area is L3; the fourth distance interval is [2.6-3cm ], and the corresponding area is L4, wherein L1> L2> L3> L4. As can be seen from fig. 21, the first chip contact in the upper left corner overlaps with 7 contacts in the canvas, where 3 contacts are completely covered and the other 4 contacts are partially covered. That is, the distance between the completely covered 3 contacts and the center of the first chip contact at the upper left corner belongs to a first distance interval [0-1.5cm ], so the corresponding area at this point is 3L1, the distance between 3 contacts of the other 4 contacts and the center of the first chip contact at the upper left corner belongs to a third distance interval [2.1-2.5cm ], so the corresponding area at this point is 3L3, the distance between the other contact and the center of the first chip contact at the upper left corner belongs to a fourth distance interval [2.6-3cm ], so the corresponding area at this point is L4. And calculating the sum of all the areas to obtain the overlapping area Y1=3L1+3L3+ L4 of the first chip contact at the upper left corner and a plurality of contacts in the covered canvas.

By the method, the overlapping area of the other chip contacts in the small chip U2 and the contacts in the covered canvas can be calculated, and then the overlapping area of all the chip contacts in the small chip U2 and the contacts in the covered canvas is calculated to obtain the first overlapping area S1.

It should be noted that, in the present application, the overlapping areas of all chip joints in the target chip and all joints corresponding to each candidate placement position in the multiple candidate placement positions are calculated, and a manner of determining the multiple candidate overlapping areas is similar to a manner of calculating the first overlapping area, and details are not repeated here.

Alternatively, the determination of the target placement position of the target chip may be implemented by combining the first and second manners, specifically, when the plurality of reference positions are determined in a manner that the search region is defined based on the initial placement position as mentioned in the first manner, the overlapping area of all chip contacts in the target chip and all contacts corresponding to the plurality of reference positions may be calculated in a manner of calculating the overlapping area as mentioned in the second manner, and finally, one reference position is selected from the plurality of reference positions as the target placement position according to the overlapping area corresponding to each reference position. The determination process of the reference position, the calculation process of the overlapping area, and the selection process of the target placement position are all similar to the first and second manners, and are not repeated one by one to avoid repetition.

When the number of the chips is m, the selection and the position adjustment of m target chips can be realized through the steps, wherein m is an integer larger than 1.

After the selection and the position adjustment of the m target chips, the m target chips and the intermediate layer are displayed in the canvas of the first display interface, the jump of the interface can be realized by triggering the first control, and the corresponding wiring diagram can be displayed on the basis of the m target chips and the intermediate layer in other display interfaces.

Based on the above idea, as shown in fig. 24, there is provided a display method including the steps of:

step S2401: the response m target chips and the interposer are disposed in a canvas of the first display interface.

Wherein m is an integer greater than 1.

The target chip can be any chip and is selected according to the requirements of customers, such as a sensor chip, a power supply management module, a communication interface module, a control module, a level converter and the like. The component modules in the interposer are preset, wherein the component modules are set based on the type of the interposer, and the component modules may include any electronic device, circuit, and a combination thereof, wherein the electronic device may be an amplifier device, a power chip, an MCU, or the like.

Step S2402: and in response to a trigger operation executed for a first control in the first display interface, displaying the m target chips and the interlayer on a second display interface.

After the m target chips and the interposer are arranged in the canvas on the first display interface, the first control in the first display interface can be triggered, namely, the m target chips and the interposer are displayed on the second display interface in response to the triggering operation executed on the first control in the first display interface.

It is assumed that the interposer includes n device modules, where n is an integer greater than 1. After the m target chips and the n component modules in the interposer are displayed on the second display interface, the net list names and the wiring types of the pins in the m target chips and the n component modules in the interposer may be set on the second display interface.

As shown in fig. 25, the second display interface 251 has an interposer 252 and 2 target chips, wherein the interposer 252 has 2 component modules S4 and S5, respectively, and the target chips on the right side of the interposer 252 have U12 and U15, respectively.

As can be seen from fig. 25, whether the component module on the interposer 252 or a part of the pins of the target chip on the right side thereof needs to be set according to customer requirements, and the set items include netlist names, routing types, and Extended Tiles (Extended grids) of the pins. The setting operation method for the pins in the n component modules in the m target chips and the interposer is the same.

Further, the operations performed for setting the netlist names and the wiring types of the pins in the m target chips and the n component modules in the interposer on the second display interface mainly include: the method comprises the steps of firstly responding to a trigger operation executed for any pin in m target chips and n element modules in an interposer, displaying a pin setting window in a floating mode on a second display interface, then responding to a trigger operation executed for a net list name and a wiring type in the pin setting window displayed in the floating mode on the second display interface, displaying a net list name input box or a net list name list and a wiring type list on the pin setting window, responding to an input operation executed for the net list name input box or a selection operation executed for the net list name list and a selection operation executed for the wiring type list, and displaying a target net list name identification corresponding to the target net list name at any pin in the second display interface.

Wherein the wiring type includes: the routing module comprises a first routing type, a second routing type and a third routing type, wherein the first routing type is used for representing routing through an interposer, the second routing type is used for representing routing through a ReDistribution Layer (RDL), and the third routing type is used for representing routing through a ReDistribution Layer and/or an interposer.

And after the wiring type corresponding to the pin is selected, the pin signal types corresponding to different wiring types can be selected. After the selection operation executed according to the input operation executed aiming at the netlist name input box or the netlist name list and the selection operation executed according to the wiring type list in the steps are performed, and then the operation executed according to the wiring type is selected according to the wiring type list, and the pin signal type list is displayed by the pin setting window; the pin signal types include: digital signals, analog signals and power signals, wherein the pin signal type is selected by cursor clicking.

In one possible implementation manner, in response to an operation of selecting a first wiring type or a third wiring type performed on the wiring type list and an operation of selecting a digital signal performed by a pin signal type, a driving pin is selected from pins with the same netlist name, and a window is set for the driving pin to hook a driving control.

Specifically, as shown in fig. 26, when a C3 pin on the chip U12 is clicked, a pin setting window is displayed in a floating manner on the chip U12, where the pin setting window includes three frames, a left upper frame is a netlist name input frame or a netlist name list, and the netlist name setting of the pin C3 can be realized by inputting a netlist name (e.g., enter Netname shown in fig. 26) into the netlist name input frame. In addition, the upper left box can also be a netlist name list, and the netlist name setting of the pin C3 is realized by selecting any netlist name in the netlist name list.

The right frame in the pin setting window is mainly used for setting the wiring type of the pin, for the pin which is not set by the wiring type, unassigned is displayed in the frame, and after the Unassigned is clicked, a wiring type list is directly displayed, wherein the wiring type list comprises three wiring types, namely a first wiring type (Programmable), a second wiring type (Metal Only) and a third wiring type (Metal Programmable). By clicking any wiring type, the setting of the wiring type of the pin C3 can be realized.

Referring to fig. 27, after the wiring type of the pin C3 is set to the first wiring type (Programmable), the pin signal types corresponding to the Programmable, that is, the Digital signal (Digital), the Analog signal (Analog), and the Power signal (Power), can be displayed by clicking the Programmable.

Through the method, the netlist name of the pin C3 is set to be U12_ DEC3, after the wiring type is set to be Programmable, a confirmation key in the pin setting window is clicked, wherein the confirmation key can be represented by Save, ok and the like, and then the pin setting window is hidden or retracted. Accordingly, the identification corresponding to the netlist name, i.e., U12_ DEC3, is displayed at pin C3. The U12_ DEC3 is displayed by using a preset highlight color, where the highlight color may be defined by a customer or selected through a color setting menu.

With reference to fig. 25 and fig. 29, after the netlist name and the wiring type of the pin C3 are set, in response to the selection operation of the cursor for the target pin C3, and in response to the selection operation of the cursor for the remaining pins, for example, the D2 pin on the U15 chip, the D2 pin to be connected to the pin C3 is selected; the selected pin displays the same netlist name as pin C3 and displays the same highlight color as pin C3, at which time the D2 pin has been defined to be the same netlist name and wiring type as C3.

Referring to fig. 28, if the C3 wiring type is the first wiring type (Programmable) or the third wiring type (metal Programmable), and the signal type is selected as the Digital signal (Digital) type, it is necessary to select one of the two pins with the same netlist name, i.e., the pin C3 and the pin D2, as a driving pin, and select a driving control (driver) in the three controls at the bottom right corner. This is because the digital signal lines need to be routed through the interposer, with the drive-side pins selected.

With reference to fig. 28, if the C3 wiring type is the second wiring type (metal Programmable) or the third wiring type (metal only), the flying lead control (implementation timeout) in the three controls at the lower right corner can be selected, the target display interface can display the flying leads between the pins wired by the redistribution layer, and when the target display interface needs to edit the pin connection line wired by the redistribution layer, the pins with the same netlist name can be identified by the flying leads between the pins.

Further, the lower left frame in the pin setting window is Extended Tiles. The input frame is used for communicating the routing of the rewiring layer with the interior of the intermediate layer; in the target display interface, the intermediate layer is divided into grids (tiles) of 44 × 64 specifications or other specifications by grid lines; when the wiring type of a certain pin is the second wiring type or the third wiring type, the number of rows and columns of a certain grid (tile) on the interposer of the target display interface are input in the Extended Tiles frame. The connection lines on the redistribution layer when the pin is pre-populated with the same netlist name are connected to the interposer through the mesh (tile).

The second display interface in the present application further includes a tool menu bar, that is, an a region, a B region, and a C region in fig. 25, where the a region, the B region, and the C region can set various setting items in each region according to a user's requirement. Note that the setting items in the respective areas are not repeatable.

Referring to fig. 30, an example of a tool menu bar disposed in the area a is shown, in which the Tool (TOOLS) menu bar includes, from left to right, a passive electronic component, a contact (BONDPAD), a print button, and a pull-back operation button.

In the case that a Tool (TOOLS) menu bar includes a resistor and a contact (BONDPAD), a view of any tool is displayed at a cursor in response to a selection operation performed by the cursor for any tool in a tool menu, and then a mark corresponding to any tool is displayed at any pin in response to the cursor moving to any pin in the m target chips and the n element modules in the interposer and then in response to a trigger operation performed for any pin.

In the case that any tool is a resistor, by clicking the icon of the resistor shown in fig. 30, the icon of the resistor is displayed at the cursor, and meanwhile, the resistor resistance value setting window shown in fig. 31 is popped up, after 10000 (i.e., 10 k) is input, the cursor is moved to the pin D2 of the chip U12, and it can be seen that a resistor with a resistance value of 10k is connected to the pin D2 shown in fig. 32, and the icon of the resistor and the identifier RN _1 are displayed.

When any tool is a BONDPAD, by clicking the BONDPAD icon shown in fig. 29, the icon of the BONDPAD is displayed at the cursor, and the icon of the BONDPAD is directly moved to the pin B4 of the chip U12, so that it can be seen that a BONDPAD is connected to the pin B4 shown in fig. 32, and the icon of the BONDPAD and the identifier BONDPAD _2 are displayed.

After the BONDPAD is set on the corresponding pin in the above manner, when the target display interface is jumped to, the previously set BONDPAD and the name corresponding to the BONDPAD are displayed on the interposer displayed in the target display interface. Therefore, the name corresponding to the BONDPAD needs to be set on the second display interface, and the specific execution mode is as follows: and in response to a trigger operation executed aiming at the identifier corresponding to the contact displayed at any pin, displaying a contact setting window in a floating mode on the second display interface, and then in response to a selection operation executed aiming at a contact name list in the contact setting window, displaying the names of the contacts, wherein the names of the contacts correspond to the names of the contacts on the interposer on the target display interface one by one.

Through the above operation, a BONDPAD is connected to the pin B4 shown in FIG. 32, and an icon and an identifier BONDPAD _2 of the BONDPAD are displayed. Then, clicking on BONDPAD at B4 pops up a contact setup window as shown in FIG. 33, and clicking on the contact setup window displays a contact name list as shown in FIG. 34, where a plurality of contact names, such as Padio _ I _0/12, padio _ I _1/20, padio _ I _2/28, etc., are displayed in the contact name list. The corresponding contact name is selected by clicking on the box in front of the contact name. When the box in front of Padio _ I _4/44 is clicked, the contact name list is hidden or collapsed, and then Padio _ I _4/44 is displayed in the contact setting window as shown in fig. 35. And finally, clicking a confirmation button Save.

Step S2403: and displaying the wiring diagram on the target display interface in response to the triggering operation executed aiming at the target control in the second display interface.

Wherein the wiring diagram is generated based on the net list names and the wiring types of the m target chips and the pins corresponding to the intermediate layers.

The target display interface includes a third display interface and a fourth display interface, the target control includes a second control and a third control, and the second control and the third control may be controls arranged in any region of the region a, the region B, and the region C in the second display interface shown in fig. 25.

Based on the three wiring types, the connecting lines of the pins of the different wiring types can be displayed on different display interfaces, so that the connecting lines of the pins of the three wiring types are displayed on the third display interface and the fourth display interface.

And the third display interface is used for displaying the m target chips and the connecting wires of the pins which belong to the same target netlist name and have the wiring types set as the first wiring type and the third wiring type on the intermediate layer. The specific implementation steps are as follows: and in response to a trigger operation executed by a second control in the second display interface, displaying a third display interface, wherein m target chips and intermediaries are displayed in the third display interface, the m target chips and the connecting lines of the pins belonging to the same target netlist name and with the wiring types set as the first wiring type on the intermediaries, and the m target chips and the connecting lines of the pins belonging to the same target netlist name and with the wiring types set as the third wiring type on the intermediaries are routed through the intermediaries.

Illustratively, clicking a second control arranged in the second display interface jumps to the third display interface. As shown in fig. 36, a chip layer 1201 (including a chip U12 and a chip U15) and an interposer 1202 are sequentially displayed in the third display interface from top to bottom, wherein a pin C2 of the chip U12 and a pin A1 of the chip U15 belong to the same netlist name (e.g., I2C0_ SDA), and a connection line between the pin C2 and the pin A1 is displayed on the interposer 1202. In addition, pin C1 of chip U12 and pin A3 of chip U15 belong to the same netlist name (e.g., I3C1_ SDA), and pin C1 and pin A3 are both of the third routing type, so the connection lines for pin C1 and pin A3 are shown in interposer 1202.

According to the above example, further, a menu bar may be further disposed on the right side of the second display interface, and a route view button is disposed in the menu bar; clicking a second control arranged in a second display interface, jumping to a third display interface, and only displaying the chip layer 1201 and the interlayer 1202 at the moment, wherein the connecting line between the pins is not displayed; responding to a cursor connection operation for the pins C1 and A3 and the pins C2 and A1, or responding to a trigger operation executed for a routing view button in a menu bar in the second display interface; the pin C1 and the pin A3, and the pin C2 and the pin A1 are connected by a connection line.

And the fourth display interface is used for displaying the m target chips and the connecting lines of the pins which belong to the same target netlist name and have the wiring types set as the second wiring type and the third wiring type on the intermediate layer. The specific execution steps are as follows: and in response to a trigger operation executed by a third control element in the second display interface, displaying a fourth display interface, wherein the m target chips and the intermediate layer, the m target chips and the intermediate layer are provided with connecting wires belonging to the same target netlist name and the wiring type is set as a pin of a second wiring type, and the m target chips and the intermediate layer are provided with connecting wires which are wired through the rewiring layer and belong to the same target netlist name and the wiring type is set as a pin of a third wiring type.

Illustratively, clicking a third control arranged in the second display interface jumps to a fourth display interface. As shown in fig. 36, a chip layer 1201 (including a chip U12 and a chip U15) and an interposer 1202 are sequentially displayed in the fourth display interface from top to bottom, where a pin C3 of the chip U12 and a pin A2 of the chip U15 belong to the same netlist name (e.g., I2C0_ SDA), and the pin C3 and the pin A2 are both of the second routing type, so that a connection relationship between the pin C3 and the pin A2 is displayed on the interposer 1202. In addition, the pin C1 of the chip U12 and the pin A3 of the chip U15 belong to the same netlist name (for example, I3C1_ SDA), and the pin C1 and the pin A3 are both of the third wiring type, so that the connection relationship between the pin C1 and the pin A3 is displayed on the redistribution layer.

According to the above example, further, a menu bar may be further disposed on the right side of the fourth display interface, and an edit list is disposed on the menu bar; and (3) checking a flying wire control (EnforceTilemap) in three controls at the right lower corner of a window on a pin C3 and a pin C1 of a second display interface, clicking a third control arranged in the second display interface, and jumping to a fourth display interface, wherein the fourth display interface can display flying wires between the pin C3 and the pin A2 as well as between the pin C1 and the pin A3, and when a target display interface needs to edit connecting wires between the pin C3 and the pin A2 as well as between the pin C1 and the pin A3, pins with the same net list name can be identified through the flying wires between the pins. Selecting editable options in an edit list in a menu bar in a fourth display interface; connecting lines are formed by connecting the cursor between the pin C3 and the pin A2 and between the pin C1 and the pin A3, or by clicking an automatic connecting line button in a menu bar in the fourth display interface, connecting lines between the pin C3 and the pin A2 and between the pin C1 and the pin A3 are formed.

As shown in fig. 41, the second display interface and the third display interface can both display the mesh diagram of the interposer, and at this time, the chip layer 1201 does not display the outer frame, but only the outer frames of the chips U12 and U15 are displayed, and this view can clearly see that the chip pins occupy several meshes 12021 (tiles). The interposer 1202 of the third display interface is divided into grid (tile) -like views of 44 × 64 specification or other specifications, and a rowbit display view 1301 is further disposed on the right side of the interposer 1202 or the substrate 1205; the row bit display view 1301 is used for displaying the occupation situation of the common transverse simulation channel of each row of grid (tile) of the interposer, as shown in fig. 41, which indicates that the grid 12021 (tile) of each row of the interposer has seven common transverse simulation channels, and when one of the seven common transverse simulation channels is occupied, the grid of the row bit display view 1301 corresponding to the common transverse simulation channel in the transverse direction is highlighted, as shown at 13011, as shown in fig. 41 with a black mark.

It should be noted that, four sides of the periphery of the interposer 1202 are uniformly distributed with bonding pads (BONDPADs) 1203, and each BONDPAD is marked with its own code. Among them, the BONDPAD shown in fig. 36 and 37 is only an example.

In addition, the second display interface, the third display interface and the fourth display interface can be jumped or switched through the first interface control, the second interface control and the third interface control respectively. The first interface control can be a "schema View" button, the second interface control can be represented by an "Optimize" button and the like, and the third interface control can be represented by a "Package View" button and the like. The buttons corresponding to the three interface controls are only examples, and may be represented by other identifiers.

Because the menu bar above the second display interface, the third display interface and the fourth display interface comprises the three interface controls, the corresponding display interface is automatically jumped to by clicking any one of the three interface controls. And setting a second display interface to currently display m target chips and intermediate layers, and m connecting lines belonging to the same target netlist name pin on the target chips and the intermediate layers.

When the "Optimize" button of the second interface control is clicked, that is, in response to a trigger operation performed on the "Optimize" button in the menu bar above the second display interface, m target chips and interposers are displayed on the third display interface, connection lines of pins belonging to the same target netlist name and having wiring types set as the first wiring type on the m target chips and interposers, and connection lines of pins belonging to the same target netlist name and having wiring types set as the third wiring type on the m target chips and interposers are routed through the interposers.

When a third interface control (Package view) is clicked, namely, in response to a triggering operation executed by the third interface control, m target chips and an intermediate layer are displayed on a fourth display interface, connecting wires of pins which belong to the same target netlist name and have wiring types set as a second wiring type on the m target chips and the intermediate layer, and connecting wires which belong to the same target netlist name and have wiring types set as a third wiring type on the m target chips and the intermediate layer and are wired through a rewiring layer.

When the connecting lines of the m target chips and the pins on the intermediate layer are displayed on the target display interface, the connecting lines are displayed on different display interfaces based on the wiring types of the pins. In addition, the connection lines need to pass through the connection points of the interposer and the connection lines of the substrate to achieve connection with the external device pins, thereby achieving more functions.

Therefore, for the third display interface, which is used for displaying the m target chips and the connecting wires of the pins which belong to the same target netlist name and have the wiring types set as the first wiring types on the intermediate layer, and the connecting wires of the contact points and the contact pads, the specific execution steps are as follows: responding to the trigger operation executed by the second interface control "Optimize" or the first control of the second display interface, and displaying a third display interface, wherein m target chips, an intermediate layer and a substrate are displayed in the third display interface, a contact is displayed on the intermediate layer, and a contact pad which can be connected with the contact is displayed on the substrate; and displaying the connecting lines of the pins belonging to the same target netlist name and the wiring type set as the first wiring type on the m target chips and the intermedium, the connecting lines of the pins belonging to the same target netlist name and the wiring type set as the third wiring type on the m target chips and the intermedium, which are routed through the interposer, and the connecting lines of the contact and the contact pad on a third display interface.

Illustratively, the user clicks the second interface control "Optimize" or a second control button of the second display interface first, and jumps to the third display interface. As shown in fig. 38, a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202, and a substrate 1205 are sequentially displayed in the third display interface from top to bottom, contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, each contact pad 1204 corresponds to a respective code, and the number and the arrangement of the contact pads in fig. 38 are only examples.

Since pin C2 of chip U12 and pin A1 of chip U15 belong to the same netlist name (e.g., I2C0_ SDA), and pin C2 and pin A1 are both of the first routing type, the connection relationship between pin C2 and pin A1 is shown in interposer 1202. In addition, the corresponding external leads of the connecting lines of the pins belonging to the first wiring type can also be displayed on the third display interface at the same time, that is, the connecting lines of the pin C2 and the pin A1 pass through the connecting lines of the contact 11 on the interposer 1202 and the contact pad 21 on the 1205 as the external leads of the pin C2 and the pin A1.

For the fourth display interface, which is used for displaying the connecting lines of the m target chips and the pins which belong to the same target netlist name and have the wiring types set as the second wiring types on the intermediate layer, and the connecting lines of the contact points and the contact pads, the specific execution steps are as follows: responding to triggering operation of a third interface control executed by a third control of the second display interface or the third interface control, and displaying a fourth display interface, wherein the fourth display interface displays m target chips, an intermediate layer and a substrate, the intermediate layer displays connection points, and the substrate displays connection pads which can be connected with the connection points; the fourth display interface displays the m target chips, the connecting wires of the pins which belong to the same target netlist name and have the wiring types set as the second wiring types on the intermediate layer, and the connecting wires of the contact points and the contact pads.

Illustratively, clicking a third interface control "Package view" button or clicking a third control button on the second display interface jumps to the fourth display interface. As shown in fig. 39, a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202, and a substrate 1205 are sequentially displayed in the fourth display interface from top to bottom, contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, each contact pad 1204 corresponds to a respective code, and the number and the arrangement of the contact pads in fig. 39 are only examples.

Since pin C3 of chip U12 and pin A2 of chip U15 belong to the same netlist name (e.g., I2C0_ SDA), and pin C3 and pin A2 are both of the second routing type, the connection relationship between pin C3 and pin A2 is shown in interposer 1202. In addition, the corresponding external leads of the connecting lines of the leads belonging to the second wiring type can also be displayed on the fourth display interface at the same time, that is, the connecting lines of the leads C3 and A2 pass through the connecting points of the contact 13 on the interposer 1202 and the connecting lines of the contact pads 23 on the 1205 as the external leads of the leads C2 and A1.

In addition, only one target display interface may be provided, that is, the third display interface and the fourth display interface are displayed on one interface, and the views are switched by providing the first, second and third routing buttons in the toolbar on the right side of the target display interface, where the first, second and third routing buttons may be provided as routing switching buttons (Wiring) as shown in fig. 40.

Clicking a first wiring diagram button in a target display interface, responding to a trigger operation executed aiming at the first wiring button, and displaying m target chips and an intermediate layer by the target display interface, connecting wires of pins which belong to the same target netlist name and have wiring types set as a first wiring type on the m target chips and the intermediate layer, and connecting wires of pins which belong to the same target netlist name and have wiring types set as a third wiring type on the m target chips and the intermediate layer through an intermediate layer.

Clicking a second wiring diagram button in the target display interface, responding to a trigger operation executed aiming at the second wiring button, and displaying m target chips and an intermediate layer by the target interface, connecting wires of pins which belong to the same target netlist name and have wiring types set as second wiring types on the m target chips and the intermediate layer, and connecting wires of pins which belong to the same target netlist name and have wiring types set as third wiring types on the m target chips and the intermediate layer and are wired through a rewiring layer.

And clicking a third wiring diagram button in the target display interface, and responding to a trigger operation executed aiming at the third wiring button, wherein the target interface displays the m target chips and the intermediate layer, and the m target chips and the connecting lines of all pins belonging to the same target netlist name on the intermediate layer.

When connecting lines of the m target chips and the pins on the intermediate layer are displayed on the target display interface, the connecting lines are displayed on different display interfaces based on the wiring types of the pins. In addition, the connection lines need to be connected to the pins of the external device through the connection points of the interposer and the connection lines of the substrate, so as to achieve more functions.

Therefore, for a target display interface, which is used for displaying connecting lines of m target chips and name pins belonging to the same target netlist on a middle layer and connecting lines of a contact and a contact pad, the specific implementation steps are as follows:

in response to a trigger operation performed on a first artwork button in the target display interface, displaying, on the target display interface:

the device comprises m target chips, an intermediate layer and a substrate, wherein the intermediate layer is provided with a contact, and the substrate is provided with a contact pad which can be connected with the contact;

and the m target chips and the connecting lines of the pins which belong to the same target netlist name and the wiring types of which are set to be the first wiring types on the intermediate layer, the m target chips and the connecting lines of the pins which belong to the same target netlist name and the wiring types of which are set to be the third wiring types on the intermediate layer, the connecting lines of the connecting points and the connecting pads, and the connecting lines of the connecting points and the connecting points.

Illustratively, clicking a target control of the second display interface to jump to the target display interface, and clicking a first wiring button. As shown in fig. 38, a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202, and a substrate 1205 are sequentially displayed on the target display interface from top to bottom, contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 38 are only examples.

Since pin C2 of chip U12 and pin A1 of chip U15 belong to the same netlist name (e.g., I2C0_ SDA), and pin C2 and pin A1 are both of the first routing type, the connection relationship between pin C2 and pin A1 is shown in the interposer 1202. In addition, the corresponding external leads of the connecting lines of the leads belonging to the first routing type can also be displayed on the target display interface at the same time, that is, the connecting lines of the lead C2 and the lead A1 pass through the connecting lines of the contact 11 on the interposer 1202 and the contact pad 21 on the 1205 as the external leads of the lead C2 and the lead A1.

In response to a triggering operation performed on a second artwork button in the target display interface, the target interface displays:

and the m target chips and the connecting wires of the pins which belong to the same target netlist name and the wiring type is set to be the second wiring type on the intermediate layer, the m target chips and the connecting wires which belong to the same target netlist name and the wiring type is set to be the third wiring type on the intermediate layer and are wired through the rewiring layer, and the connecting wires of the contact and the contact pad.

Illustratively, clicking a target control of the second display interface first jumps to the target display interface, and clicking a second wiring button of the target display interface. As shown in fig. 39, a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202, and a substrate 1205 are sequentially displayed on the target display interface from top to bottom, contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 39 are only examples.

Since pin C3 of chip U12 and pin A2 of chip U15 belong to the same netlist name (e.g., I2C0_ SDA), and pin C3 and pin A2 are both of the second routing type, the connection relationship between pin C3 and pin A2 is shown in the interposer 1202. In addition, the corresponding external leads of the connecting lines of the leads belonging to the second wiring type can also be displayed on the target display interface at the same time, that is, the connecting lines of the lead C3 and the lead A2 pass through the connecting lines of the contact 13 on the interposer 1202 and the contact pad 23 on the 1205 as the external leads of the lead C2 and the lead A1.

In addition, this application still can operate the components and parts that set up in the intermediate layer, respond to earlier promptly to the selection operation that the components and parts name in the component and parts selection list on the toolbar in the second display interface was carried out, show the components and parts thumbnail at the cursor, then respond to the cursor is to the trigger operation that the intermediate layer was carried out, will components and parts set up in the intermediate layer.

Specifically, in response to a selection operation performed on a component or module on the interposer;

in response to a delete operation being performed on a selected component or module, the component or module is deleted from the interposer.

Further, a stereoscopic view may also be generated, that is, in response to a trigger operation executed on a fourth control in the second display interface, a stereoscopic view corresponding to the wiring diagram in the target display interface is displayed, where the stereoscopic view may be a 2D, 3D, 4D, or other stereoscopic view.

Furthermore, the method can also export the wiring diagram, namely, in response to the triggering operation executed for the fifth control in the first display interface, different types of files corresponding to the wiring diagram are output.

The file types that can be exported include but are not limited to GDS files, SIP files, DXF files, STP files, ODB + + files, gerber files, IPC files, SPICE netlist files, API/SDK files, VHDL/Verilog hardware description language files, schema files, report files, bump list files, ballmap files, POD files, CSV/EXCEL/TXT files, ZEF files, and process information.

In addition, files can also be imported in the first display interface, and the types of files that can be imported include, but are not limited to, GDS files, SIP files, DXF files, STP files, ODB + + files, gerber files, IPC files, SPICE netlist files, API/SDK files, VHDL/Verilog hardware description language files, schema files, report files, bump files, ballmap files, POD files, CSV/EXCEL/TXT files, ZEF files, process information, and chiplets or silicon bridges, schematic diagrams of circuits connected between chiplets, circuit description languages, substrate files, two-dimensional/three-dimensional structures, rewiring layers, interposer layers, netlists (the connection relationships in the netlist are represented in words), design parameters (line width, line spacing, etc.), design rule, export + report + software interface.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

The following are embodiments of the apparatus of the invention, reference being made to the corresponding method embodiments described above for details which are not described in detail therein.

Fig. 42 is a schematic structural diagram of a display device according to an embodiment of the present invention, and for convenience of description, only a portion related to the embodiment of the present invention is shown, and the display device includes a setting module 4201, a first display module 4202, and a second display module 4203, which are specifically as follows:

a setting module 4201, configured to set, in response to m target chips in a canvas of a first display interface, where m is an integer greater than 1;

a first display module 4202, configured to display the m target chips and the interposer on a second display interface in response to a trigger operation performed on a first control in the first display interface;

a second display module 4203, configured to display, on a target display interface, a wiring diagram in response to a trigger operation performed on a target control in the second display interface, where the wiring diagram is generated based on netlist names and wiring types of pins corresponding to the m target chips and intermediaries.

In a possible implementation manner, before the setting module 4201, the setting module further includes a placing module, configured to, for each target chip of the m target chips, respond to a selection operation performed on a chip name in a chip type selection list in a toolbar of the first display interface, and acquire the target chip;

responding to a first interaction event of a cursor, and displaying an angle placing menu of the target element, wherein the angle placing menu comprises a plurality of preset placing angles;

responding to a first selection event of the cursor, and displaying a preview of the target chip under a target placing angle, wherein the target placing angle is one of the preset placing angles;

and responding to a second selection event of the cursor, and generating a design drawing of the target chip under the target placing angle at the target position in the canvas area.

In a possible implementation manner, before the module 4201 is provided, a chip library establishing module is further included, and the chip library establishing module is configured to establish a chip library in response to an import operation performed on parameters of a chip, where the parameters at least include an electrical property, a shape, a size, and a name of the chip.

after the module 4201 is set, a position adjustment module is further included, the position adjustment module is configured to detect an initial placement position of the target chip in a canvas in response to the target chip being set in the canvas, where the canvas includes a plurality of grid cells arranged in an array, each of the grid cells is provided with a contact point, and the contact point is used for representing a contact point of an interposer;

In a possible implementation manner, the position adjusting module is further configured to detect whether the initial placing position is aligned with a preset reference position;

In a possible implementation manner, the position adjusting module is further configured to determine a plurality of candidate placing positions based on the initial placing position, where the candidate placing positions are obtained by using the initial placing position as a starting point and moving the target chip by using a second offset;

determining the target pose position based on the initial pose position and the plurality of candidate pose positions.

In a possible implementation manner, after the first display module 4202, a pin setting module is further included, and the pin setting module is configured to set, on the second display interface, netlist names and routing types of pins in n component modules in the m target chips and the interposer, where n is an integer greater than 1.

In one possible implementation, the pin setting module is further configured to suspend displaying a pin setting window on the second display interface in response to a trigger operation performed on any one of the m target chips and the n component modules in the interposer;

and in response to the input operation executed for the netlist name input box or the selection operation executed for the netlist name list and the selection operation executed for the routing type list, displaying a target netlist name identification corresponding to the target netlist name at any pin in the second display interface.

In one possible implementation, the wiring type includes:

a first wiring type, a second wiring type and a third wiring type,

wherein the first routing type is used to characterize routing through an interposer, the second routing type is used to characterize routing through a re-routing layer, and the third routing type is used to characterize routing through a re-routing layer and/or an interposer.

the device also comprises a tool selection module, wherein the tool selection module is used for responding to a selection operation executed by a cursor aiming at any tool in the tool menu and displaying a view of the tool at the cursor;

responding to the cursor moving to any pin of the m target chips and the n element modules in the interposer;

In one possible implementation, the tool menu includes at least passive electronic components or contacts.

the second display module 4203 is configured to display the third display interface in response to a trigger operation performed by the second control in the second display interface, where the m target chips, an interposer and a substrate are displayed in the third display interface, where contacts are displayed on the interposer and contact pads connectable to the contacts are displayed on the substrate;

connecting lines of pins which belong to the same target netlist name and have wiring types set as first wiring types on the m target chips and the interposer, and connecting lines of the joints and the joint pads;

displaying a fourth display interface in response to a trigger operation executed by the third control element in the second display interface, wherein the fourth display interface displays the m target chips, an interposer and a substrate, wherein contacts are displayed on the interposer, and contact pads connectable with the contacts are displayed on the substrate;

the m target chips and the connecting lines of the pins which belong to the same target netlist name and have the wiring types set as the second wiring types on the interposer, and the connecting lines of the contacts and the contact pads.

In one possible implementation of the method according to the invention,

the device further comprises a fourth display module, wherein the fourth display module is used for responding to a trigger operation executed by a third wiring type in a pin setting window displayed in a suspension mode in the second display interface;

responding to a selection operation executed aiming at the contact name list in the contact setting window;

and displaying the third display interface in response to a trigger operation executed for a second control in the second display interface, wherein the m target chips and the connecting lines of the pins which belong to the same target netlist name and have the wiring types set as the third wiring types and are routed through the interposer are displayed in the third display interface.

In a possible implementation manner, the m target chips and connection lines routed through the interposer on the interposer, which belong to the same target netlist name and have routing types set as pins of a third routing type, are displayed in the third display interface;

and the fourth display interface displays the m target chips and the connecting lines of the pins which belong to the same target netlist name and are set to be of the third wiring type and are wired through the rewiring layer.

In one possible implementation manner, the interposer includes at least a power management module, a communication interface module, a control module, and a level shifter.

In a possible implementation manner, the device further comprises a component setting module, and the component setting module is used for setting the component setting module

and setting the component in an intermediary layer in response to a triggering operation performed by the cursor on the intermediary layer.

In one possible implementation, the apparatus further includes a component handling module, configured to respond to a selection operation performed on a component or a module on the interposer;

in response to a deletion operation being performed with respect to a selected component or module, the component or module is deleted from the interposer.

In a possible implementation manner, the apparatus further includes a stereoscopic view display module, where the stereoscopic view display module is configured to display a stereoscopic view corresponding to the wiring diagram in the target display interface in response to a trigger operation executed for a fourth control in the second display interface.

In a possible implementation manner, the apparatus further includes a file generation module, and the file generation module is configured to output different types of files corresponding to the wiring diagram in response to a trigger operation executed for a fifth control in the first display interface.

Fig. 43 is a schematic diagram of a terminal according to an embodiment of the present invention. As shown in fig. 43, the terminal 43 of this embodiment includes: a processor 4301, a memory 4302, and a computer program 4303 stored in the memory 4302 and operable on the processor 4301. The steps in each of the display method embodiments described above, such as steps 2401 to 2403 shown in fig. 24, are implemented when the processor 4301 executes the computer program 4303. Alternatively, the processor 4301, when executing the computer program 4303, implements the functions of the modules/units in the display apparatus embodiment described above, for example, the functions of the modules/units 4201 to 4203 shown in fig. 42.

The present invention also provides a readable storage medium, in which a computer program is stored, and the computer program is used for implementing the display method provided by the above various embodiments when executed by a processor.

The readable storage medium may be a computer storage medium or a communication medium. Communication media includes any medium that facilitates transfer of a computer program from one place to another. Computer storage media can be any available media that can be accessed by a general purpose or special purpose computer. For example, a readable storage medium is coupled to a processor such that the processor can read information from, and write information to, the readable storage medium. Of course, the readable storage medium may also be an integral part of the processor. The processor and the readable storage medium may reside in an Application Specific Integrated Circuits (ASIC). Additionally, the ASIC may reside in user equipment. Of course, the processor and the readable storage medium may also reside as discrete components in a communication device. The readable storage medium may be read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, optical data storage devices, and the like.

The present invention also provides a program product comprising executable instructions stored on a readable storage medium. The at least one processor of the device may read the execution instructions from the readable storage medium, and the execution of the execution instructions by the at least one processor causes the device to implement the display method provided by the various embodiments described above.

In the above embodiments of the apparatus, it is understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A display method, comprising:

in response to a trigger operation executed for a first control in the first display interface, displaying the m target chips and the interlayer on a second display interface;

and in response to a trigger operation executed for a target control in the second display interface, displaying a wiring diagram on the target display interface, wherein the wiring diagram is generated based on the netlist names and the wiring types of the pins corresponding to the m target chips and the intermediate layers.

2. The display method of claim 1, wherein in response to the m target chips being placed in front of the canvas of the first display interface, further comprising:

3. The display method as claimed in claim 2, wherein before the obtaining the target chip in response to the selection operation performed on the chip name in the chip type list in the toolbar of the first display interface, the method further comprises:

4. The display method of claim 3, wherein the target placement position is an initial placement position of the target chip in the canvas;

after the response that the m target chips are arranged in the canvas of the first display interface, the method further comprises the following steps:

detecting an initial placement position of the target chip in a canvas in response to the target chip being arranged in the canvas, wherein the canvas comprises a plurality of grid cells arranged in an array, and each grid cell in the plurality of grid cells is provided with a joint for representing a contact point of an interposer;

5. The display method of claim 4, wherein the determining the target placement position corresponding to the target chip based on the initial placement position comprises:

6. The display method of claim 5, wherein the determining the target placement position corresponding to the target chip based on the initial placement position comprises:

determining a plurality of candidate placing positions based on the initial placing position, wherein the candidate placing positions are obtained by taking the initial placing position as a starting point and moving the target chip by a second offset;

7. The display method of claim 1, wherein the responding to the trigger operation performed for the first control in the first display interface further comprises, after the m target chips and the interposer are displayed in the second display interface:

and setting net list names and wiring types of pins in n element modules in the m target chips and the intermediate layer on the second display interface, wherein n is an integer larger than 1.

8. The method of displaying as claimed in claim 7, wherein said setting netlist names and routing types of pins in n component modules in said m target chips and intermediaries in said second display interface comprises:

in response to a trigger operation executed on any pin of the m target chips and the n element modules in the interposer, suspending a display of a pin setup window on the second display interface;

9. The display method of claim 8, wherein the wiring type comprises:

a first wiring type, a second wiring type and a third wiring type,

10. The display method of claim 9, wherein the second display interface further comprises a tool menu bar;

in response to a selection operation performed by a cursor for any tool in the tool menu, displaying a view of the any tool at the cursor;

responding to the cursor moving to any pin in the m target chips and the n element modules in the interposer;

11. The display method of claim 10, wherein the tool menu includes at least passive electronic components or contacts.

12. The display method of claim 11, wherein the target display interface comprises a third display interface and a fourth display interface, and the target control comprises a second control and a third control;

the step of displaying the wiring diagram on the target display interface in response to the triggering operation executed for the target control in the second display interface comprises the following steps:

displaying a third display interface in response to a trigger operation executed by the second control in a second display interface, wherein the m target chips, an interposer and a substrate are displayed in the third display interface, wherein joints are displayed on the interposer, and joint pads capable of being connected to the joints are displayed on the substrate;

13. The display method as claimed in claim 12,

responding to a trigger operation executed for a third wiring type in a pin setting window displayed in a floating mode in the second display interface;

and displaying the third display interface in response to a triggering operation executed on a second control in the second display interface, wherein the third display interface displays the m target chips and connecting lines of the pins, which belong to the same target netlist name and have the wiring types set as third wiring types, on the interposer, and the connecting lines are routed through the interposer.

14. The display method of claim 13,

the m target chips and connecting lines which belong to the same target netlist name and are arranged on the interposer in a wiring type set to be a third wiring type and pass through interposer wiring are displayed in the third display interface;

15. The display method of claim 7, wherein the interposer internally comprises at least a power management module, a communication interface module, a control module, and a level shifter.

16. The display method of claim 7, wherein the method further comprises:

17. The display method of claim 16, wherein the method further comprises:

18. The display method of claim 17, wherein the method further comprises:

and responding to a triggering operation executed for a fourth control in the second display interface, and displaying a stereoscopic view corresponding to the wiring diagram in the target display interface.

19. The display method of claim 1, wherein the method further comprises:

and outputting different types of files corresponding to the wiring diagram in response to a triggering operation executed for a fifth control in the first display interface.

20. A display device, comprising:

a first display module, configured to display the m target chips and the interposer on a second display interface in response to a trigger operation performed on a first control in the first display interface;

and the second display module is used for responding to a trigger operation executed for a target control in the second display interface and displaying a wiring diagram on the target display interface, wherein the wiring diagram is generated based on the net list names and the wiring types of the pins corresponding to the m target chips and the intermediate layers.

21. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the display method according to any one of claims 1 to 19 when executing the computer program.

22. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the display method according to any one of claims 1 to 19.