CN115758983B

CN115758983B - Wiring method, wiring device, terminal and storage medium

Info

Publication number: CN115758983B
Application number: CN202211431452.6A
Authority: CN
Inventors: 许荣峰; 卢萧; 易春来; 林哲民
Original assignee: Shanghai Chipler Chip Technology Co ltd; Shenzhen Qipule Chip Technology Co ltd
Current assignee: Shanghai Chipler Chip Technology Co ltd; Shenzhen Qipule Chip Technology Co ltd
Priority date: 2022-11-14
Filing date: 2022-11-14
Publication date: 2023-10-20
Anticipated expiration: 2042-11-14
Also published as: CN115758983A

Abstract

The application discloses a wiring method, a wiring device, a terminal and a storage medium, wherein the wiring method comprises the following steps: setting netlist names and wiring types of pins in n element modules in m target chips and an intermediate layer on a first display interface, and displaying a wiring diagram generated according to the netlist names and the wiring types of the pins on the target display interface in response to trigger operation executed by a target control in the first display interface. According to the application, the connection relation of each pin is determined by automatically identifying the netlist name and the signal type of the pin, so that the corresponding wiring diagram is displayed on the target display interface directly based on the connection relation between the pins, the automatic connection between the chip and the interposer is realized, and the wiring efficiency is improved. In addition, the netlist names and signal types of different pins are set, so that different wiring patterns are generated according to the netlist names and signal types of different pins, wiring between a chip and an intermediary layer is clear, and user experience is improved.

Description

Wiring method, wiring device, terminal and storage medium

Technical Field

The application relates to the technical field of EDA, in particular to a wiring method, a wiring device, a wiring terminal and a storage medium.

Background

Chiplet technology refers to decomposing a Soc (System on Chip) into a plurality of smaller chiplets, where the chiplets can have different functions and processes, and then packaging the modular chiplets together using a novel packaging technology to achieve interconnection of the chiplets, i.e., to form a heterogeneous integrated Chip.

To realize the wide application of the Chiplet technology, chiplet technology is applied to EDA (electronic design automation ). In EDA based on Chiplet technology, there are typically multiple chiplets that need to be connected to pins between the multiple chips according to customer requirements to make up a heterogeneous integrated chip. In addition, since the heterogeneous integrated chip needs to be connected with the active medium layer and the substrate. Therefore, how to realize wiring among a plurality of chiplets, active interposer, and substrate is a problem to be solved.

At present, wiring among a plurality of chiplets, active intermediaries and substrates is mainly achieved manually, i.e. experienced wiring personnel manually connect the plurality of chiplets, active intermediaries and substrates based on customer requirements.

However, the above method cannot realize automatic wiring among a plurality of chiplets, active interposer, substrate, so that the cost of resources such as manpower, time and the like increases, and the cost of resources is high.

Disclosure of Invention

The application mainly aims to provide a wiring method, a wiring device, a wiring terminal and a storage medium, so as to solve the problem of high resource cost in the related technology.

In order to achieve the above object, in a first aspect, the present application provides a wiring method comprising:

setting netlist names and wiring types of pins in n element modules in m target chips and an intermediate layer on a first display interface, wherein m and n are integers larger than 1;

and responding to the triggering operation executed by the target control in the first display interface, and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface.

In one possible implementation, setting netlist names and routing types of pins in n component modules in m target chips and an interposer at a first display interface includes:

responding to a triggering operation executed for any pin of n element modules in the m target chips and the intermediate layer, and suspending a display pin setting window on a first display interface;

Responding to trigger operation executed for netlist names and wiring types in a pin setting window displayed in a floating manner on a first display interface, and displaying a netlist name input frame or a netlist name list and a wiring type list in the pin setting window;

responding to the input operation executed for the netlist name input box or the selection operation executed by the netlist name list and the selection operation executed by the wiring type list, and displaying a target netlist name identifier corresponding to the target netlist name at any pin in the first display interface;

in response to a selection operation of the cursor for any target pin of the displayed target netlist name identifications, in response to a selection operation of the cursor for pins required to be connected with the target pin, the pin selected by the cursor displays the target netlist name identifications same as the target pin and is defined as the netlist name and the wiring type same as the target pin.

In one possible implementation, the routing types include:

a first wiring type, a second wiring type, and a third wiring type,

wherein the first wire type is used for characterizing routing through the interposer, the second wire type is used for characterizing routing through the rewiring layer, and the third wire type is used for characterizing routing through the rewiring layer and/or the interposer.

In one possible implementation, the pin setup window displays a list of pin signal types in response to an operation performed for the list of wire types to select a wire type; the pin signal types include: the pin signal type is selected by clicking a cursor.

In one possible implementation, in response to an operation performed for the routing type list to select the first routing type or the third routing type and an operation performed for the pin signal type to select the digital signal, a drive pin is selected from pins of the same netlist name, and a window is set for the drive pin to select the drive control.

In one possible implementation, the first display interface further includes a tool menu bar;

displaying a view of any tool at the cursor in response to a selection operation performed by the cursor for any tool in the tool menu;

responding to cursor movement to any pin of n element modules in the m target chips and the intermediate layer;

and in response to the triggering operation executed for any pin, displaying the identification corresponding to any tool at any pin.

In one possible implementation, the tool menu includes at least passive electronic components or contacts.

In one possible implementation manner, after displaying the identifier corresponding to any tool at any pin in response to the trigger operation performed on any pin, the method further includes:

when any tool is a contact, responding to a triggering operation executed for an identifier corresponding to the contact displayed at any pin, and suspending and displaying a contact setting window on a first display interface;

and responding to the selection operation executed for the contact name list in the contact setting window, displaying the names of the contacts, wherein the names of the contacts are in one-to-one correspondence with the names of the contacts on the interposer on the target display interface.

In one possible implementation, the target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control;

responding to the triggering operation executed by the target control in the first display interface, displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface, wherein the method comprises the following steps:

responding to the triggering operation executed by the first control in the first display interface, displaying a second display interface, wherein m target chips and an intermediary layer are displayed in the second display interface, and

connecting wires of pins which belong to the same target netlist name and are set as a first wiring type on the m target chips and the interposer;

Responding to the triggering operation executed by the second control in the first display interface, displaying a third display interface, wherein the third display interface displays m target chips and an intermediary layer, and

and connecting wires which belong to the same target netlist name and are set as pins of a second wiring type on the m target chips and the interposer.

In one possible implementation manner, m target chips displayed on the second display interface and connecting wires which belong to the same target netlist name and are routed through the interposer, wherein the routing type of each connecting wire is set as a pin of a third routing type;

and m target chips displayed on the third display interface and connecting wires which belong to the same target netlist name and are routed through the rewiring layer, wherein the routing type of each connecting wire is set as a pin of a third routing type.

responding to the triggering operation executed by the first control of the first display interface, displaying a second display interface, wherein m target chips, an intermediate layer and a substrate are displayed in the second display interface, the intermediate layer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

Connecting wires of pins with wiring types set as a first wiring type and connecting wires of joints and contact pads, which belong to the same target netlist name on m target chips and an interposer;

responding to the triggering operation executed by the second control of the first display interface, displaying a third display interface, wherein the third display interface displays m target chips, an intermediate layer and a substrate, the intermediate layer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

connecting wires of pins with the wiring type set as a second wiring type and connecting wires of joints and contact pads on the m target chips and the interposer layer belong to the same target netlist name.

In one possible implementation, the trigger operation performed in response to the third wiring type in the pin setup window for floating display in the first display interface;

responding to a selection operation executed for a contact name list in a contact setting window;

and responding to a triggering operation executed for the first control in the first display interface, displaying a second display interface, wherein m target chips and connecting wires which belong to the same target netlist name and are routed through the interposer on the interposer and are arranged as pins of a third routing type are displayed in the second display interface.

In one possible implementation manner, m target chips and wiring connecting lines through the interposer, which belong to the same target netlist name and are provided with pins with a third wiring type, are displayed on the second display interface;

and displaying m target chips and connecting wires which belong to the same target netlist name and are routed through a rewiring layer, wherein the routing type of the connecting wires is set as pins of a third routing type, on the interposer.

In one possible implementation, in response to a trigger operation performed for a first wiring pattern button in a target display interface, displaying m target chips and an interposer on the target display interface, and connecting lines of pins on the m target chips and the interposer belonging to the same target netlist name and having a wiring type set to a first wiring type;

and in response to a trigger operation performed for the second wiring pattern button in the target display interface, displaying m target chips and the interposer on the target interface, and connecting lines of pins which belong to the same target netlist name and are set to be of a second wiring type on the m target chips and the interposer.

In one possible implementation, in response to a trigger operation performed for a first wiring pattern button in a target display interface, displaying on the target display interface m target chips and connection lines routed through the interposer of pins belonging to the same target netlist name and having a wiring type set to a third wiring type;

In response to a trigger operation performed for the second wiring pattern button in the target display interface, connecting lines routed through the rewiring layer, which belong to the same target netlist name and whose wiring type is set as pins of the third wiring type, are displayed on the target display interface on the m target chips and the interposer.

In one possible implementation, m target chips and intermediaries, and connection lines on the m target chips and intermediaries that belong to the same target netlist name pin, are displayed on the target interface in response to a trigger operation performed for a third wiring pattern button in the target display interface.

In one possible implementation, m target chips, an interposer, and a substrate are displayed on a target display interface in response to a trigger operation performed on a first wiring pattern button in the target display interface, wherein contacts are displayed on the interposer, and contact pads connectable with the contacts are displayed on the substrate;

in response to a trigger operation executed for a second wiring pattern button in the target display interface, displaying m target chips, an interposer and a substrate on the target interface, wherein the interposer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

responding to a triggering operation performed for a first wiring diagram button in a target display interface;

displaying connecting wires which belong to the same target netlist name and are routed through the interposer, of pins with the routing type set as a third routing type, on m target chips and the interposer on a target display interface;

responding to a triggering operation performed for a second wiring diagram button in the target display interface;

and displaying the connecting wires which belong to the same target netlist name and are routed through the rewiring layer, of the pins with the routing type set as the third routing type, on the m target chips and the interposer on the target display interface.

In one possible implementation, m target chips, an interposer, and a substrate are displayed on the target interface in response to a trigger operation performed on a third wiring pattern button in the target display interface, connecting lines on the m target chips and the interposer that belong to the same target netlist name pin, and connecting lines between interposer contacts and contact pads on the substrate.

In one possible implementation, the selecting operation of the second routing type performed in response to the input operation performed for the netlist name input box in the pin setup window or the selecting operation performed for the netlist name list, and the selecting operation of the second routing type performed for the routing type list;

responding to a selection operation executed for the flying lead control in the pin setting window;

responding to a triggering operation executed by a second control in the first display interface, displaying a third display interface, wherein the third display interface displays m target chips, an interposer, and flying leads of pins which belong to the same target netlist name and are set as a second wiring type on the m target chips and the interposer;

responding to a selection operation which is performed for editable in an editing list in a menu bar in a third display interface;

in response to a connection operation of a cursor for pins belonging to the same target netlist name and having a wiring type set to a second wiring type on the m target chips and the interposer, or in response to a trigger operation performed for an auto-connect button in a menu bar in a target display interface, m target chips, the interposer, and connection lines of pins belonging to the same target netlist name and having a wiring type set to the second wiring type on the m target chips and the interposer are displayed on a third display interface.

In one possible implementation, the selecting operation of the second routing type is performed in response to an input operation performed for a netlist name input box in the pin setup window or a selecting operation performed for a netlist name list, and the routing type list;

in response to a trigger operation performed for a second wiring pattern button in the target display interface, displaying m target chips and an interposer on the target interface, and flying leads of pins belonging to the same target netlist name and having a wiring type set to a second wiring type on the m target chips and the interposer;

responding to a selection operation which is performed for editable in an editing list in a menu bar in a target display interface;

in response to a connection operation of a cursor for pins belonging to the same target netlist name and having a wiring type set to a second wiring type on m target chips and interposer, or in response to a trigger operation performed for an auto-wire button in a menu bar in a target display interface, m target chips and interposer, and connection lines of pins belonging to the same target netlist name and having a wiring type set to a second wiring type on m target chips and interposer are displayed on the target interface.

In one possible implementation, the selecting operation of the first routing type is performed in response to an input operation performed for a netlist name input box in a pin setup window or a selecting operation performed for a netlist name list, and the routing type list;

responding to a triggering operation executed by a first control of the first display interface, displaying a second display interface, wherein the second display interface displays m target chips and an interposer;

in response to a connection operation of a cursor for a pin on the m target chips and the interposer that belongs to the same target netlist name and whose wiring type is set to the first wiring type, or in response to a trigger operation performed for a route view button in a menu bar in a target display interface, the m target chips, the interposer, and a connection line of a pin on the m target chips and the interposer that belongs to the same target netlist name and whose wiring type is set to the first wiring type are displayed on a second display interface.

In one possible implementation, the selecting operation of the first routing type performed in response to the input operation performed for the netlist name input box of the pin setup window or the selecting operation performed for the netlist name list, and the selecting operation of the first routing type performed for the routing type list;

In response to a trigger operation performed for a first wiring diagram button in a target display interface, displaying m target chips and an interposer on the target interface;

in response to a connection operation of a cursor for pins belonging to the same target netlist name and having a wiring type set to a first wiring type on m target chips and an interposer, or in response to a trigger operation performed for a route view button in a menu bar in a target display interface, m target chips and an interposer, and connection lines of pins belonging to the same target netlist name and having a wiring type set to a first wiring type on m target chips and an interposer are displayed on the target interface.

In one possible implementation, the interposer is an active interposer;

the connecting wire of the pin routed through the active medium layer at least comprises a digital signal wire and an analog signal wire, wherein the digital signal wire is arranged in the digital channel, and the analog signal wire is arranged in the analog channel;

and setting a preset digital signal line in the analog channel in response to a trigger operation performed on a channel switching button of the target display interface.

In a second aspect, an embodiment of the present invention provides a wiring device including:

The setting module is used for setting netlist names and wiring types of pins in n element modules in m target chips and an interposer on a first display interface, wherein m and n are integers larger than 1;

and the wiring module is used for responding to the triggering operation executed by the target control in the first display interface and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface.

In a third aspect, an embodiment of the present invention provides a terminal including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps of any one of the routing methods described above when executing the computer program.

In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the wiring methods described above.

The embodiment of the invention provides a wiring method, a wiring device, a terminal and a storage medium, comprising the following steps: setting netlist names and wiring types of pins in n element modules in m target chips and an interposer layer on a first display interface, and displaying a wiring diagram generated according to the netlist names and the wiring types of the pins on the target display interface in response to trigger operation executed by a target control in the first display interface. According to the invention, the connection relation of each pin is determined by automatically identifying the netlist name and the signal type of the pin, so that the corresponding wiring diagram is displayed on the target display interface directly based on the connection relation between the pins, the automatic connection between the chip and the interposer is realized, and the wiring efficiency is improved. In addition, the netlist names and signal types of different pins are set, so that different wiring patterns are generated according to the netlist names and signal types of different pins, wiring between a chip and an intermediary layer is clear, and user experience is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application, are incorporated in and constitute a part of this specification. The drawings and their description are illustrative of the application and are not to be construed as unduly limiting the application. In the drawings:

FIG. 1 is a flow chart of an implementation of a wiring method provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a first display interface according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a pin setup window according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a pin setup window according to another embodiment of the present application;

FIG. 5 is a schematic diagram of a pin setup window according to another embodiment of the present application;

FIG. 6 is a schematic diagram of a chiplet U12 provided in accordance with an embodiment of the present application;

FIG. 7 is a schematic diagram of a tool menu bar provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of a resistance setting window according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a chiplet U12 provided in accordance with another embodiment of the present application;

FIG. 10 is a schematic view of a contact setting window according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a contact name list provided by an embodiment of the present application;

Fig. 12 is a schematic view of a contact setting window according to another embodiment of the present invention;

FIG. 13 is a schematic diagram of a second display interface according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of a third display interface according to an embodiment of the present invention;

FIG. 15 is a schematic view of a second display interface according to another embodiment of the present invention;

FIG. 16 is a schematic diagram of a third display interface according to another embodiment of the present invention;

FIG. 17 is a schematic diagram of a wiring switching button provided by an embodiment of the present invention;

FIG. 18 is a schematic diagram of an interposer provided by an embodiment of the present invention;

fig. 19 is a schematic structural view of a wiring device according to an embodiment of the present invention;

fig. 20 is a schematic diagram of a terminal according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.

It should be understood that, in various embodiments of the present invention, the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

It should be understood that in the present invention, "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in the present invention, "plurality" means two or more. "and/or" is merely an association relationship describing an association object, and means that three relationships may exist, for example, and/or B may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. "comprising A, B and C", "comprising A, B, C" means that all three of A, B, C comprise, "comprising A, B or C" means that one of the three comprises A, B, C, and "comprising A, B and/or C" means that any 1 or any 2 or 3 of the three comprises A, B, C.

It should be understood that in the present invention, "B corresponding to a", "a corresponding to B", or "B corresponding to a" means that B is associated with a, from which B can be determined. Determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information. The matching of A and B is that the similarity of A and B is larger than or equal to a preset threshold value.

As used herein, "if" may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context.

The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the following description will be made by way of specific embodiments with reference to the accompanying drawings.

In one embodiment, as shown in fig. 1, a wiring method is provided, comprising the steps of:

step S101: netlist names and routing types of pins in n component modules in m target chips and an interposer are set in a first display interface.

The target chip can be any chip, and is selected according to the requirements of customers, such as a sensor chip, a power chip and the like. The component module in the interposer (interposer) is preset, wherein the component module is set based on the type of the interposer, and the component module can comprise any electronic device, circuit and combination of the two, wherein the electronic device can be an amplifier device, a power chip, an MCU and the like.

Wherein m and n are integers greater than 1.

As shown in fig. 2, the first display interface 21 displays an interposer 22 and 2 target chips, wherein 2 component modules, respectively S4 and S5, are in the interposer 22, and the target chips disposed on the right side of the interposer 22 are U12 and U15, respectively.

As can be seen from fig. 2, whether the component modules on the interposer 22 or some of the pins of the target chip on the right side thereof are required to be set according to the customer requirements, the set items include the netlist names of the pins, the routing types, and the Extended lots. The set operation method for the pins in the n element modules in the m target chips and the interposer is the same.

Further, the operations performed for setting netlist names and routing types of pins in n component modules in the interposer and m target chips at the first display interface mainly include: a pin setting window is displayed in suspension on a first display interface in response to a triggering operation executed for any pin of n element modules in m target chips and an intermediate layer, then a netlist name input frame or a netlist name list and a wiring type list are displayed on the pin setting window in response to a triggering operation executed for the netlist names and wiring types in the pin setting window displayed in suspension on the first display interface, and then a target netlist name identifier corresponding to the target netlist name is displayed on any pin in the first display interface in response to an input operation executed for the netlist name input frame or a selection operation executed for the netlist name list and a selection operation executed for the wiring type list.

Wherein the wiring types include: a first wiring type, a second wiring type, and a third wiring type,

wherein a first wire type is used to characterize routing through the interposer, a second wire type is used to characterize routing through the rewiring Layer (RDL, reDistribution Layer), and a third wire type is used to characterize routing through the rewiring Layer and/or the interposer.

After selecting the wiring types corresponding to the pins, the pin signal types corresponding to different wiring types can be selected. Namely, according to the selection operation performed in response to the input operation performed for the netlist name input box or the netlist name list and the selection operation performed for the wiring type list in the above steps, then in response to the operation performed for the wiring type list to select the wiring type, the pin setting window displays the pin signal type list; the pin signal types include: the pin signal type is selected by clicking a cursor.

Specifically, as shown in fig. 3, when clicking the C3 pin on the chip U12, a pin setting window is displayed in a floating manner on the chip U12, where the pin setting window includes three boxes, and the upper box on the left side is a netlist name input box or a netlist name list, and the netlist name setting of the pin C3 can be achieved by inputting a netlist name (e.g., the Enter Netname shown in fig. 3) in the netlist name input box. In addition, the upper left box can also be a netlist name list, and the netlist name setting of the pin C3 is realized through selecting any one netlist name in the netlist name list.

The right frame in the pin setting window is mainly used for setting the wiring types of pins, and for pins which are not subjected to wiring type setting, the Unassign is displayed in the frame first, and after clicking the Unassign, a wiring type list is directly displayed, wherein the wiring type list comprises three wiring types, namely a first wiring type (Programmable), a second wiring type (Metal Only) and a third wiring type (Metal Programmable). By clicking any wiring type, the setting of the wiring type of the pin C3 can be realized.

With reference to fig. 4, after setting the wiring type of the pin C3 to the first wiring type (Programmable), the pin signal type corresponding to the Programmable, that is, the Digital signal (Digital), the Analog signal (Analog), and the Power signal (Power), may be displayed by clicking the Programmable.

By setting the netlist name of the pin C3 as U12 DEC3 in the above manner, after the wiring type is set as Programmable, clicking a confirmation key in the pin setting window, wherein the confirmation key can be represented by Save, ok and the like, and the pin setting window is hidden or retracted. Accordingly, an identification corresponding to the netlist name, namely U12 DEC3, is displayed at pin C3. Wherein, the U12 DEC3 is displayed with a preset highlighting color, which can be defined by a customer or selected through a color setting menu.

Referring to fig. 2 and 6, after setting both the netlist name and the routing type of the pin C3, responding to a selection operation of the cursor for the target pin C3, responding to a selection operation of the cursor for the other pins, for example, the D2 pin on the U15 chip, and selecting the D2 pin to be connected with the pin C3; the same netlist name as pin C3 is displayed at the selected pin and the same highlighting color as pin C3 is displayed, at which point the D2 pin has been defined as the same netlist name and routing type as C3.

Referring to fig. 5, if the C3 wiring type is the first wiring type (Programmable) or the third wiring type (metal Programmable), the signal type is selected as the Digital signal (Digital) type, and one of the pins with the same netlist name, i.e. pin C3 and pin D2, needs to be selected as a driving pin, and the driving control (driver) in the three lower right-hand corner controls is checked. This is because the driver pins need to be selected when the digital signal lines are routed through the interposer.

Referring to fig. 5, if the C3 wiring type is the second wiring type (metal Programmable) or the third wiring type (metal only), a flying lead control (performance title) in the three controls at the lower right corner may be checked, then the target display interface may display a flying lead between the pins routed through the re-routing layer, and when the target display interface needs to edit the pin connection line routed through the re-routing layer, the pins with the same name of the netlist may be identified by the flying lead between the pins.

In addition, the lower left box in the pin setting window is Extended Tiles. The input frame is used for communicating the wiring of the rewiring layer with the inside of the interposer; in the target display interface, the interposer is divided into grids (tiles) of 44×64 or other specifications by grid lines; when the wiring type of a certain pin is the second wiring type or the third wiring type, the number of rows and columns of a certain grid (tile) on the interposer of the target display interface are input in the Extended Tiles frame. The connection lines on the rewiring layer for the pins whose name is the same as that of the netlist are connected to the interposer through the mesh (tile).

The first display interface in the present application further includes a tool menu bar, that is, an a area, a B area, and a C area in fig. 2, where the a area, the B area, and the C area may set various setting items in each area according to a user's requirement. It should be noted that the setting items in the respective areas are not repeatable.

Referring to fig. 7, a tool menu bar is set in the area a, where the tool (tool) menu bar includes passive electronic components, contacts (bond pads), print buttons, and withdraw operation buttons from left to right.

In the case where the Tool (TOOLS) menu bar includes a resistor, a contact (BONDPAD), a view of any tool is displayed at the cursor in response to a selection operation performed by the cursor for any tool in the tool menu, then a corresponding identification of any tool is displayed at any pin in response to movement of the cursor to any pin in the n component modules in the m target chips and interposer, and then in response to a triggering operation performed for any pin.

When any tool is a resistor, by clicking the icon of the resistor shown in fig. 7, the icon of the resistor is displayed at the cursor, and simultaneously the resistor resistance setting window shown in fig. 8 is popped up, after 10000 (i.e. 10 k) is input, the cursor is moved to the pin D2 of the chip U12, and then it can be seen that a resistor with a resistance of 10k is connected to the pin D2 shown in fig. 9, and the icon of the resistor and the mark rn_1 are displayed.

When any tool is bond pad, by clicking the bond pad icon shown in fig. 6, the bond pad icon is displayed at the cursor, and the bond pad icon is directly moved to the pin B4 of the chip U12, then it can be seen that a bond pad is connected to the pin B4 shown in fig. 9, and the bond pad icon and the identification bond pad_2 are displayed.

After the bond pad is set on the corresponding pin in the above manner, when the bond pad jumps to the target display interface, the bond pad set before and the name corresponding to the bond pad are displayed on the interposer displayed in the target display interface. Therefore, the name corresponding to the bond pad needs to be set on the first display interface, and the specific implementation manner is as follows: and displaying the names of the contacts in a one-to-one correspondence manner with the names of the contacts on the interposer on the target display interface in response to a triggering operation executed for the identifier corresponding to the contact displayed at any pin, suspending the display of the contact setting window on the first display interface, and then in response to a selecting operation executed for the contact name list in the contact setting window.

Through the above operation, a bond pad is connected to the pin B4 shown in fig. 9, and an icon of the bond pad and the identifier bond pad_2 are displayed. Then clicking on the bond pad at B4 pops up the contact setting window shown in fig. 10, and clicking on the contact setting window displays the contact name list shown in fig. 11, where the contact name list displays a plurality of contact names, such as pacdio_i_0/12, pacdio_i_1/20, pacdio_i_2/28, and so on. The corresponding contact name is selected by clicking on the box in front of the contact name. After clicking on the box in front of the Padio_I_4/44, the contact name list is hidden or collapsed, after which Padio_I_4/44 is displayed in the contact setup window as shown in FIG. 12. Finally, clicking the confirm button Save.

Step S102: and responding to the triggering operation executed by the target control in the first display interface, and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface.

The target display interface includes a second display interface and a third display interface, and the target control includes a first control and a second control, where the first control and the second control may be controls disposed in any of the area a, the area B, and the area C in the first display interface shown in fig. 2.

Based on the three wiring types, the connecting wires of the pins of different wiring types can be displayed in different display interfaces, so the connecting wires of the pins of the three wiring types are displayed in the second display interface and the third display interface.

The second display interface is used for displaying the m target chips and connecting wires of pins belonging to the same target netlist name and having the wiring types set as the first wiring type and the third wiring type on the interposer. The specific implementation steps are as follows: and responding to the triggering operation executed by the first control in the first display interface, displaying a second display interface, wherein m target chips and intermediaries are displayed in the second display interface, connecting wires of pins which belong to the same target netlist name and are set to be of a first wiring type on the m target chips and intermediaries, and connecting wires of pins which belong to the same target netlist name and are set to be of a third wiring type on the m target chips and intermediaries are arranged through intermediaries.

Illustratively, clicking on a first control disposed in the first display interface jumps to the second display interface. As shown in fig. 13, a chip layer 1201 (including a chip U12 and a chip U15) and an interposer 1202 are displayed in the second display interface from top to bottom, where a pin C2 of the chip U12 and a pin A1 of the chip U15 belong to the same netlist name (i.2c0_sda), and a connection line between the pin C2 and the pin A1 is displayed in the interposer 1202. In addition, the pin C1 of the chip U12 and the pin A3 of the chip U15 belong to the same netlist name (i.e. i3c1_sda), and the pin C1 and the pin A3 are both of the third wiring type, so that the connection lines of the pin C1 and the pin A3 are displayed on the interposer 1202.

According to the above example, further, a menu bar may be further disposed on the right side of the second display interface, where a route view button is disposed; clicking a first control arranged in the first display interface, and jumping to a second display interface, wherein only the chip layer 1201 and the interposer 1202 are displayed at the moment, and connecting wires between pins are not displayed; responding to the cursor for connection operation of the pin C1 and the pin A3 and the pin C2 and the pin A1 or responding to triggering operation executed for a route view button in a menu bar in a second display interface; pin C1 and pin A3 and pin C2 and pin A1 are connected by a connecting wire.

The third display interface is used for displaying the m target chips and connecting wires of pins belonging to the same target netlist name and having the wiring types set as the second wiring type and the third wiring type on the interposer. The specific implementation steps are as follows: and responding to the triggering operation executed by the second control in the first display interface, displaying a third display interface, wherein m target chips and an intermediate layer, connecting wires of pins which belong to the same target netlist name and are set as a second wiring type on the m target chips and the intermediate layer, and connecting wires which belong to the same target netlist name and are routed through a rerouting layer, of pins which are set as a third wiring type, on the m target chips and the intermediate layer.

Illustratively, clicking on a second control disposed in the first display interface jumps to the third display interface. As shown in fig. 14, a chip layer 1201 (including a chip U12 and a chip U15) and an interposer 1202 are displayed in the third display interface from top to bottom, where a pin C3 of the chip U12 and a pin A2 of the chip U15 belong to the same netlist name (I2 c0_sda, for example), and the pin C3 and the pin A2 are both of the second wiring type, and then a connection relationship between the pin C3 and the pin A2 is displayed in the interposer 1202. In addition, the pin C1 of the chip U12 and the pin A3 of the chip U15 belong to the same netlist name (i.e. i3c1_sda), and the pin C1 and the pin A3 are both of the third wiring type, so that the connection relationship between the pin C1 and the pin A3 is displayed in the redistribution layer.

According to the above example, further, a menu bar may be further set on the right side of the third display interface, where an edit list is set; and selecting a flying wire control (performance Tilemap) in three controls at the right lower corners of the pin C3 and the pin C1 pin setting window on the first display interface, clicking a second control arranged in the first display interface, and jumping to a third display interface, wherein the third display interface can display flying wires between the pin C3 and the pin A2 as well as between the pin C1 and the pin A3, and when the target display interface needs to edit connecting wires between the pin C3 and the pin A2 and between the pin C1 and the pin A3, the pins with the same names of netlists can be identified through the flying wires between the pins. Selecting editable options in an edit list in a menu bar in a third display interface; connecting wires are formed by connecting the pins C3 and A2 with the pins A1 and A3 through a cursor, or connecting wires between the pins C3 and A2 and between the pins C1 and A3 are formed by clicking an automatic connecting button in a menu bar in a third display interface.

As shown in fig. 18, the second display interface and the third display interface can both display the mesh diagram of the interposer, and at this time, the chip layer 1201 does not display the outer frame, only displays the outer frames of the chip U12 and the chip U15, and this view can clearly see that the chip pins occupy several meshes 12021 (tiles). The interposer 1202 of the third display interface is divided into a grid (tile) view of 44×64 or other specifications, and a rowbit display view 1301 is further provided on the right side of the interposer 1202 or the substrate 1205; the row bit display view 1301 is used to show the occupation situation of the common transverse analog channels of each row of the grids (tile) of the interposer, as shown in fig. 18, which shows that the grids 12021 (tile) of each row of the interposer have seven common transverse analog channels, and when one of them is occupied, the grid of the row bit display view 1301 corresponding to the common transverse analog channel in the transverse direction is highlighted, as shown in 13011, and as shown in black mark of fig. 18.

Note that, the four sides of the periphery of the interposer 1202 are uniformly provided with contacts (bond pads) 1203, and each bond pad is marked with a respective code. Among them, the BONDPAD shown in fig. 13 and 14 is only an example.

In addition, the application can also realize the jump or switch of the first display interface, the second display interface and the third display interface through the first interface control, the second interface control and the third interface control respectively. The first interface control may be a "scheme View" button, the second interface control may be an "Optimize" button, etc., and the third interface control may be a "Package View" button, etc. The buttons corresponding to the three interface controls are only examples, and can be represented by other identifiers.

Because the menu bar above the first display interface, the second display interface and the third display interface comprises the three interface controls, the user can jump to the corresponding display interface automatically by clicking any one of the three interface controls. The first display interface is provided with m target chips and an intermediate layer, and connecting lines belonging to the same target netlist name pin on the m target chips and the intermediate layer.

When clicking the second interface control "Optimize" button, that is, in response to a triggering operation performed on the "Optimize" button in the menu bar above the first display interface, m target chips and intermediaries are displayed on the second display interface, connecting lines of pins belonging to the same target netlist name and having a wiring type set as a first wiring type are connected to the m target chips and intermediaries, and connecting lines of pins belonging to the same target netlist name and having a wiring type set as a third wiring type are routed through the intermediaries.

When clicking a third interface control (Package view), that is, responding to the triggering operation executed by the third interface control, m target chips and intermediaries are displayed on a third display interface, connecting lines of pins belonging to the same target netlist name and having the wiring type set as a second wiring type on the m target chips and intermediaries, and connecting lines of pins belonging to the same target netlist name and having the wiring type set as a third wiring type and being routed through a rerouting layer on the m target chips and intermediaries.

When the m target chips and the connecting wires of the pins on the interposer are displayed on the target display interface, the connecting wires are displayed on different display interfaces based on the wiring types of the pins. In addition, the connection wire needs to be connected with the pins of the external equipment through the contact of the interposer and the connection wire of the substrate, so that more functions are realized.

Therefore, for the second display interface, it is used for displaying m target chips and connecting wires belonging to the same target netlist name and having the wiring type set as the pins of the first wiring type and connecting wires of the contacts and the contact pads on the interposer, the specific implementation steps are as follows: responding to the triggering operation executed by the second interface control 'Optimize' or the first control of the first display interface, displaying a second display interface, wherein m target chips are displayed in the second display interface, an interposer and a substrate are displayed on the interposer, contacts are displayed on the interposer, and contact pads capable of being connected with the contacts are displayed on the substrate; and displaying connecting wires which belong to the same target netlist name and are provided with pins of the first wiring type on the m target chips and the interposer, connecting wires which belong to the same target netlist name and are provided with pins of the third wiring type and are provided with connecting wires which pass through the interposer and are provided with pins of the first wiring type on the m target chips and the interposer, and connecting wires of the contact and the contact pad on the second display interface.

Illustratively, the first control button of the second interface control "Optimize" or the first display interface is first clicked, and the jump is made to the second display interface. As shown in fig. 15, the second display interface includes a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202 and a substrate 1205 sequentially arranged from top to bottom, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 15 are only examples.

Since the pin C2 of the chip U12 and the pin A1 of the chip U15 belong to the same netlist name (i.e. i2c0_sda), and the pin C2 and the pin A1 are both of the first wiring type, the connection relationship between the pin C2 and the pin A1 is displayed on the interposer 1202. In addition, the corresponding external leads of the connection lines of the pins belonging to the first wiring type may also be simultaneously displayed on the second display interface, that is, the connection lines of the pin C2 and the pin A1 are connected to the connection pads 21 on the substrate 1205 through the connection points 11 on the interposer 1202 as the external leads of the pin C2 and the pin A1.

Aiming at a third display interface, which is used for displaying the m target chips and the connecting wires of pins belonging to the same target netlist name and having the wiring type set as a second wiring type and the connecting wires of joints and joint pads on an interposer, the specific implementation steps are as follows: responding to the triggering operation of a second control of the first display interface or a third interface control, displaying a third display interface, wherein the third display interface displays m target chips, an intermediate layer and a substrate, the intermediate layer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts; the third display interface displays the m target chips and the connecting wires of pins belonging to the same target netlist name and having the wiring type set as the second wiring type and the connecting wires of the contact points and the contact pads on the interposer.

Illustratively, clicking on the third interface control "Package view" button or clicking on the second control button on the first display interface jumps to the third display interface. As shown in fig. 16, the third display interface includes a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202 and a substrate 1205 sequentially arranged from top to bottom, where contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, and the number and arrangement of the contact pads in fig. 16 are only examples.

Since pin C3 of chip U12 and pin A2 of chip U15 belong to the same netlist name (i.e., i2c0_sda), and pin C3 and pin A2 are both of the second routing type, the connection relationship between pin C3 and pin A2 is shown in interposer 1202. In addition, the corresponding external leads of the connection lines of the pins belonging to the second wiring type may also be simultaneously displayed on the third display interface, that is, the connection lines of the pin C3 and the pin A2 are connected to the connection pads 23 on the substrate 1205 through the connection points 13 on the interposer 1202 as the external leads of the pin C2 and the pin A1.

In addition, only one target display interface may be provided, that is, the second display interface and the third display interface are displayed on one interface, and the view is switched by providing a first Wiring button, a second Wiring button and a third Wiring button in a toolbar on the right side of the target display interface, where the first Wiring button, the second Wiring button and the third Wiring button may be provided as a Wiring switching button (wire) as shown in fig. 17.

Clicking a first wiring diagram button in a target display interface, and responding to a triggering operation executed for the first wiring button, the target display interface displays m target chips and intermediaries, connecting wires of pins which belong to the same target netlist name and are set to be of a first wiring type on the m target chips and intermediaries, and wiring connecting wires of pins which belong to the same target netlist name and are set to be of a third wiring type on the m target chips and intermediaries through intermediaries.

Clicking a second wiring diagram button in a target display interface, and responding to a triggering operation executed for the second wiring button, the target interface displays m target chips and intermediaries, connecting wires which belong to the same target netlist name and are provided with pins of a second wiring type on the m target chips and intermediaries, and connecting wires which belong to the same target netlist name and are provided with pins of a third wiring type on the m target chips and intermediaries and are routed through a rewiring layer.

Clicking a third wiring diagram button in a target display interface, and responding to a triggering operation executed for the third wiring button, wherein the target interface displays m target chips and an intermediate layer, and connecting lines of all pins belonging to the same target netlist name on the m target chips and the intermediate layer.

Therefore, aiming at the target display interface, the method is used for displaying the m target chips and the connecting wires belonging to the same name pin of the target netlist and the connecting wires of the contact points and the contact pads on the interposer, and specifically comprises the following steps:

in response to a trigger operation performed for a first wiring diagram button in the target display interface, displaying at the target display interface:

the chip comprises m target chips, an intermediate layer and a substrate, wherein the intermediate layer is provided with contacts, and the substrate is provided with contact pads capable of being connected with the contacts;

and connecting wires of pins which belong to the same target netlist name and are set as a first wiring type on the m target chips and the interposer, connecting wires of wires which belong to the same target netlist name and are set as a third wiring type on the m target chips and the interposer and are connected through the interposer, and connecting wires of contacts and contact pads.

Illustratively, clicking the target control of the first display interface first jumps to the target display interface and clicks the first routing button. As shown in fig. 15, the target display interface includes a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202 and a substrate 1205 sequentially arranged from top to bottom, and contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, where the number and arrangement of the contact pads in fig. 15 are only examples.

Since the pin C2 of the chip U12 and the pin A1 of the chip U15 belong to the same netlist name (i.e. i2c0_sda), and the pin C2 and the pin A1 are both of the first wiring type, the connection relationship between the pin C2 and the pin A1 is displayed on the interposer 1202. In addition, the corresponding external leads of the connection lines of the pins belonging to the first wiring type may also be simultaneously displayed on the target display interface, that is, the connection lines of the pin C2 and the pin A1 are connected to the connection pads 21 on the substrate 1205 through the connection points 11 on the interposer 1202 as the external leads of the pin C2 and the pin A1.

In response to a trigger operation performed for the second wiring diagram button in the target display interface, the target interface displays:

and connecting wires of pins belonging to the same target netlist name and having a wiring type set as a second wiring type on the m target chips and the interposer, connecting wires of pins belonging to the same target netlist name and having a wiring type set as a third wiring type on the m target chips and the interposer, and connecting wires of contacts and contact pads through the rewiring layer.

Illustratively, clicking the target control of the first display interface first jumps to the target display interface and clicks the second routing button of the target display interface. As shown in fig. 16, the target display interface includes a chip layer 1201 (including a chip U12 and a chip U15), an interposer 1202 and a substrate 1205 sequentially arranged from top to bottom, and contact pads 1204 are uniformly disposed on the periphery of the substrate 1205, and each contact pad 1204 corresponds to a respective code, where the number and arrangement of the contact pads in fig. 16 are only examples.

Since pin C3 of chip U12 and pin A2 of chip U15 belong to the same netlist name (i.e., i2c0_sda), and pin C3 and pin A2 are both of the second routing type, the connection relationship between pin C3 and pin A2 is shown in interposer 1202. In addition, the corresponding external leads of the connection lines of the pins belonging to the second wiring type may also be simultaneously displayed on the target display interface, that is, the connection lines of the pin C3 and the pin A2 are connected through the contact pads 23 on the contacts 13 and 1205 on the interposer 1202 as the external leads of the pin C2 and the pin A1.

The embodiment of the invention provides a wiring method, which comprises the following steps: setting netlist names and wiring types of pins in n element modules in m target chips and an interposer layer on a first display interface, and displaying a wiring diagram generated according to the netlist names and the wiring types of the pins on the target display interface in response to trigger operation executed by a target control in the first display interface. According to the invention, the connection relation of each pin is determined by automatically identifying the netlist name and the signal type of the pin, so that the corresponding wiring diagram is displayed on the target display interface directly based on the connection relation between the pins, the automatic connection between the chip and the interposer is realized, and the wiring efficiency is improved. In addition, the netlist names and signal types of different pins are set, so that different wiring patterns are generated according to the netlist names and signal types of different pins, wiring between a chip and an intermediary layer is clear, and user experience is improved.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.

The following are device embodiments of the invention, for details not described in detail therein, reference may be made to the corresponding method embodiments described above.

Fig. 19 shows a schematic structural diagram of a wiring device according to an embodiment of the present invention, and for convenience of explanation, only a portion related to the embodiment of the present invention is shown, and the wiring device includes a setting module 1901 and a wiring module 1902, specifically as follows:

a setting module 1901, configured to set netlist names and routing types of pins in n element modules in m target chips and an interposer on a first display interface, where m and n are integers greater than 1;

and the wiring module 1902 is used for responding to the triggering operation executed by the target control in the first display interface and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface.

In one possible implementation, the setting module 1901 is further configured to hover display a pin setting window on the first display interface in response to a trigger operation performed for any pin of the n element modules in the m target chips and the interposer;

In one possible implementation, the routing types include:

a first wiring type, a second wiring type, and a third wiring type,

In one possible implementation, the apparatus further includes a pin type setting module for displaying a pin signal type list in response to an operation performed for the wire type list to select the wire type; the pin signal types include: the pin signal type is selected by clicking a cursor.

In one possible implementation manner, the apparatus further includes a driver setting module, where the driver setting module is configured to select a driver pin from pins with the same netlist name in response to an operation performed on the list of wiring types to select the first wiring type or the third wiring type and an operation performed on a pin signal type to select a digital signal, and select a driver control in a pin setting window of the driver pin.

the device also comprises a tool selection module, wherein the tool selection module is used for responding to the selection operation executed by the cursor for any tool in the tool menu, and displaying the view of any tool at the cursor;

In one possible implementation manner, after the tool selecting module, the tool selecting module further includes a contact setting module, where the contact setting module is configured to, in a case where any tool is a contact, suspend and display a contact setting window on the first display interface in response to a trigger operation performed on an identifier corresponding to the contact displayed at any pin;

the wiring module 1902 is further configured to display a second display interface in response to a triggering operation performed by the first control in the first display interface, where m target chips and intermediaries are displayed in the second display interface, and

the device also comprises a first display module, wherein the first display module is used for responding to the triggering operation executed by the first control of the first display interface, displaying a second display interface, m target chips are displayed in the second display interface, an interposer and a substrate, wherein the interposer is provided with a contact, and the substrate is provided with a contact pad which can be connected with the contact;

In one possible implementation, the apparatus further includes a second display module for responding to a trigger operation performed for a third wiring type in a pin setup window of the floating display in the first display interface;

In one possible implementation manner, the apparatus further includes a third display module, where the third display module is configured to display, on the target display interface, m target chips and an interposer, and connection lines of pins on the m target chips and the interposer that belong to a same target netlist name and have a wiring type set to a first wiring type, in response to a trigger operation performed on the first wiring pattern button in the target display interface;

In one possible implementation manner, the apparatus further includes a fourth display module, configured to display, on the target display interface, m target chips and connection lines routed through the interposer that belong to the same target netlist name and have a routing type set as pins of a third routing type, in response to a trigger operation performed for the first wiring pattern button in the target display interface;

In one possible implementation, the apparatus further includes a fifth display module, where the fifth display module is configured to display, on the target interface, m target chips and an interposer, and connection lines on the m target chips and the interposer that belong to a same target netlist name pin, in response to a trigger operation performed on a third wiring pattern button in the target display interface.

In one possible implementation manner, the apparatus further includes a sixth display module, configured to display m target chips, an interposer, and a substrate on the target display interface in response to a triggering operation performed on the first wiring pattern button in the target display interface, where the interposer displays contacts, and the substrate displays contact pads that can be connected to the contacts;

In one possible implementation, the apparatus further includes a seventh display module for responding to a trigger operation performed for the third wiring type in the pin setup window floating in the first display interface;

In one possible implementation, the apparatus further includes an eighth display module, where the eighth display module is configured to display, on the target interface, m target chips, an interposer, and a substrate in response to a trigger operation performed on a third wiring pattern button in the target display interface, connection lines of the m target chips and the interposer that belong to a same name pin of the target netlist, and connection lines of the interposer contacts and contact pads on the substrate.

In one possible implementation, the apparatus further includes a ninth display module for responding to an input operation performed for a netlist name input box in the pin setup window or a selection operation performed for a netlist name list, and a selection operation of a second wire type performed for the wire type list;

In one possible implementation, the apparatus further includes a tenth display module for performing a selection operation of the second routing type in response to an input operation performed for a netlist name input box in the pin setup window or a selection operation performed for a netlist name list, and the routing type list;

In one possible implementation, the apparatus further includes an eleventh display module for performing a selection operation of the first routing type in response to an input operation performed with respect to a netlist name input box in the pin setup window or a selection operation performed by a netlist name list, and the routing type list;

In one possible implementation, the apparatus further includes a twelfth display module for responding to an input operation performed for the netlist name input box of the pin setup window or a selection operation performed for the netlist name list, and a selection operation of the first routing type performed for the routing type list;

In one possible implementation, the interposer is an active interposer;

the device also comprises a circuit setting module, wherein the circuit setting module is used for connecting wires of pins routed through the active interposer and at least comprises a digital signal wire and an analog signal wire, the digital signal wire is arranged in the digital channel, and the analog signal wire is arranged in the analog channel;

Fig. 20 is a schematic diagram of a terminal according to an embodiment of the present invention. As shown in fig. 20, the terminal 20 of this embodiment includes: a processor 2001, a memory 2002, and a computer program 2003 stored in the memory 2002 and executable on the processor 2001. The steps in the respective wiring method embodiments described above, for example, steps 101 to 102 shown in fig. 1, are realized when the processor 2001 executes the computer program 2003. Alternatively, the processor 2001, when executing the computer program 2003, implements the functions of the respective modules/units in the above-described wiring device embodiment, such as the functions of the modules/units 1901 to 1902 shown in fig. 19.

The present invention also provides a readable storage medium having a computer program stored therein, which when executed by a processor is configured to implement the wiring method provided in the above-described various embodiments.

The readable storage medium may be a computer storage medium or a communication medium. Communication media includes any medium that facilitates transfer of a computer program from one place to another. Computer storage media can be any available media that can be accessed by a general purpose or special purpose computer. For example, a readable storage medium is coupled to the processor such that the processor can read information from, and write information to, the readable storage medium. In the alternative, the readable storage medium may be integral to the processor. The processor and the readable storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC). In addition, the ASIC may reside in a user device. The processor and the readable storage medium may reside as discrete components in a communication device. The readable storage medium may be read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tape, floppy disk, optical data storage device, etc.

The present invention also provides a program product comprising execution instructions stored in a readable storage medium. The at least one processor of the apparatus may read the execution instructions from the readable storage medium, and execution of the execution instructions by the at least one processor causes the apparatus to implement the wiring methods provided by the various embodiments described above.

In the above described embodiments of the apparatus, it is understood that the processor may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims

1. A wiring method, characterized by comprising:

responding to the triggering operation executed by the target control in the first display interface, and displaying a wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface;

the setting of netlist names and routing types of pins in n element modules in m target chips and an interposer at a first display interface includes:

suspending a display pin setup window at the first display interface in response to a trigger operation performed for any pin of the n element modules in the m target chips and the interposer;

responding to trigger operation executed for netlist names and wiring types in a pin setting window which is displayed in a floating way on the first display interface, and displaying a netlist name input box or a netlist name list and a wiring type list in the pin setting window;

2. The wiring method of claim 1, wherein the wiring type comprises:

a first wiring type, a second wiring type, and a third wiring type,

wherein the first wire type is used for characterizing routing through an interposer, the second wire type is used for characterizing routing through a rewiring layer, and the third wire type is used for characterizing routing through a rewiring layer and/or an interposer.

3. The wiring method as in claim 2, wherein the pin setup window displays a list of pin signal types in response to an operation of selecting a wiring type performed for the list of wiring types; the pin signal types include: the pin signal type is selected through cursor clicking.

4. The routing method of claim 3, wherein in response to the operation performed for the list of routing types to select the first routing type or the third routing type and the operation performed for the pin signal type to select the digital signal, a drive pin is selected among pins of a same netlist name, and a window tick drive control is set at a pin of the drive pin.

5. The routing method of claim 2, wherein the first display interface further comprises a tool menu bar;

displaying a view of any tool in the tool menu at a cursor in response to a selection operation performed by the cursor for the any tool;

responsive to the cursor moving to any pin of the m target chips and n element modules in the interposer;

and responding to the triggering operation executed for any pin, and displaying the identification corresponding to any tool at any pin.

6. The routing method of claim 5, wherein at least passive electronic components or contacts are included in the tool menu.

7. The routing method of claim 6, wherein after displaying the identifier corresponding to the arbitrary tool at the arbitrary pin in response to the trigger operation performed for the arbitrary pin, further comprising:

when any tool is the contact, responding to a triggering operation executed for the identifier corresponding to the contact displayed at any pin, and suspending and displaying a contact setting window on the first display interface;

8. The routing method of claim 2, wherein the target display interface comprises a second display interface and a third display interface, the target control comprising a first control and a second control;

the responding to the triggering operation executed by the target control in the first display interface displays the wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface, and the method comprises the following steps:

the second display interface is displayed in response to the triggering operation executed by the first control in the first display interface, wherein the m target chips and the intermediary layer are displayed in the second display interface,

responding to the triggering operation executed by the second control in the first display interface, displaying a third display interface, the third display interface displaying the m target chips and the intermediary layer,

and connecting wires of pins which belong to the same target netlist name and are set as a second wiring type on the m target chips and the interposer.

9. The wiring method as in claim 8, wherein,

The m target chips displayed on the second display interface and the connecting lines which belong to the same target netlist name and are routed through the interposer, wherein the routing type of the connecting lines is set as pins of a third routing type;

and the m target chips displayed on the third display interface and the connecting wires which belong to the same target netlist name and are routed through the rewiring layer, wherein the routing type of the connecting wires is set as pins of a third routing type.

10. The routing method of claim 7, wherein the target display interface comprises a second display interface and a third display interface, the target control comprising a first control and a second control;

responding to the triggering operation executed by the first control of a first display interface, displaying a second display interface, wherein the m target chips, an intermediate layer and a substrate are displayed in the second display interface, wherein the intermediate layer is provided with contacts, the substrate is provided with contact pads which can be connected with the contacts, and the m target chips and the intermediate layer are provided with connecting wires which belong to the same target netlist name and are provided with pins of a first wiring type, and the connecting wires of the contacts and the contact pads;

Responding to the triggering operation executed by the second control of the first display interface, displaying the third display interface, wherein the third display interface displays the m target chips, an intermediate layer and a substrate, wherein the intermediate layer is provided with contacts, the substrate is provided with contact pads which can be connected with the contacts,

and connecting wires of pins which belong to the same target netlist name and are set as a second wiring type on the m target chips and the interposer, and connecting wires of the contact points and the contact pads.

11. The wiring method as set forth in claim 10, wherein,

responding to a trigger operation executed for a third wiring type in a pin setting window which is displayed in a floating mode in the first display interface;

responding to a selection operation executed for a contact name list in the contact setting window;

and responding to a triggering operation executed for a first control in a first display interface, and displaying a second display interface, wherein the m target chips and connecting wires which belong to the same target netlist name and are arranged as pins of a third wiring type and are routed through an interposer are displayed in the second display interface.

12. The wiring method according to claim 10 or 11, wherein,

the m target chips and connecting wires which belong to the same target netlist name and are routed through the interposer, wherein the routing type of the connecting wires is set as pins of a third routing type, are displayed in the second display interface;

and the third display interface displays the m target chips and connecting wires which belong to the same target netlist name and are arranged as pins of a third wiring type and are routed through the rewiring layer on the intermediate layer.

13. The wiring method of claim 2, wherein the m target chips and the interposer are displayed on the target display interface in response to a trigger operation performed for a first wiring pattern button in the target display interface, and connection lines of pins belonging to a same target netlist name and having a wiring type set to a first wiring type are on the m target chips and the interposer;

and in response to a trigger operation executed for a second wiring diagram button in the target display interface, displaying the m target chips and the intermediate layer on the target display interface, and connecting lines of pins which belong to the same target netlist name and are set to be of a second wiring type on the m target chips and the intermediate layer.

14. The wiring method as in claim 13, wherein,

responding to a triggering operation executed for a first wiring diagram button in the target display interface, and displaying wiring connecting lines through an interposer of pins which belong to the same target netlist name and are set to be a third wiring type on the m target chips and the interposer on the target display interface;

and in response to a trigger operation performed on a second wiring diagram button in the target display interface, displaying connection lines routed through a rerouting layer of pins belonging to the same target netlist name and having a routing type set as a third routing type on the m target chips and the interposer on the target display interface.

15. The wiring method as in claim 14, wherein,

and responding to a triggering operation executed for a third wiring diagram button in the target display interface, and displaying the m target chips and the intermediate layer on the target display interface, wherein the m target chips and the intermediate layer belong to the same target netlist name pin connecting lines.

16. The wiring method as set forth in claim 7, wherein,

in response to a trigger operation performed for a first wiring pattern button in the target display interface, displaying the m target chips, an interposer, and a substrate on the target display interface, wherein contacts are displayed on the interposer, contact pads connectable to the contacts are displayed on the substrate,

Connecting wires of pins which belong to the same target netlist name and are set to be of a first wiring type on the m target chips and the interposer, and connecting wires of the contact points and the contact pads; in response to a trigger operation performed for a second wiring pattern button in the target display interface, displaying the m target chips, an interposer, and a substrate on the target display interface, wherein contacts are displayed on the interposer, contact pads connectable to the contacts are displayed on the substrate,

17. The wiring method as set forth in claim 16, wherein,

responding to a triggering operation performed for a first wiring diagram button in the target display interface;

Displaying wiring connecting lines through the interposer, which belong to the same target netlist name and are provided with pins with a third wiring type, on the m target chips and the interposer on the target display interface;

and displaying connecting wires which belong to the same target netlist name and are routed through a rewiring layer, of pins with the routing type set as a third routing type, on the m target chips and the interposer on the target display interface.

18. The wiring method according to claim 16 or 17, wherein,

in response to a trigger operation performed for a third wiring pattern button in the target display interface, displaying the m target chips, interposer, and substrate on the target display interface,

and connecting wires of the m target chips and pins belonging to the same target netlist name on the interposer, and connecting wires of the interposer contacts and contact pads on the substrate.

19. The wiring method according to any one of claims 8 or 10, wherein:

responding to an input operation executed for a netlist name input box in the pin setting window or a selection operation executed by a netlist name list and a selection operation of a second wiring type executed by a wiring type list;

Responding to a selection operation executed for a flying lead control in the pin setting window;

responding to a triggering operation executed by the second control in a first display interface, displaying a third display interface, wherein the third display interface displays the m target chips, an interposer, and flying leads of pins which belong to the same target netlist name and are set as a second wiring type on the m target chips and the interposer;

and displaying the m target chips, the interposer, and connecting lines of pins belonging to the same target netlist name and having a wiring type set to a second wiring type on the m target chips and the interposer on the third display interface in response to a connection operation of a cursor for pins belonging to the same target netlist name and having a wiring type set to the second wiring type on the m target chips and the interposer, or in response to a trigger operation executed for an auto-connect button in a menu bar in the target display interface.

20. The wiring method according to any one of claims 13 or 16, wherein:

Responding to an input operation executed for a netlist name input box in the pin setting window or a selection operation executed by a netlist name list, and executing a selection operation of a second wiring type by a wiring type list;

responding to a triggering operation executed for a second wiring diagram button in the target display interface, and displaying flying leads of pins which belong to the same target netlist name and are set as a second wiring type on the m target chips and the intermediate layer on the target display interface;

responding to a selection operation which can be performed in an editing list in a menu bar in the target display interface;

and responding to the connection operation of cursors for pins which belong to the same target netlist name and are set to be of a second wiring type on the m target chips and the intermediate layer, or responding to the triggering operation which is executed for an automatic connection button in a menu bar in the target display interface, and displaying connection lines of the pins which belong to the same target netlist name and are set to be of the second wiring type on the m target chips and the intermediate layer on the target display interface.

21. The wiring method according to any one of claims 8 or 10, wherein:

responding to an input operation executed for a netlist name input box in the pin setting window or a selection operation executed by a netlist name list, and executing a first wiring type selection operation by a wiring type list;

responding to a triggering operation executed by the first control of a first display interface, displaying a second display interface, wherein the second display interface displays the m target chips and an interposer;

and displaying the m target chips, the interposer, and connecting lines of pins belonging to the same target netlist name and having a wiring type set to a first wiring type on the m target chips and the interposer on the second display interface in response to a connection operation of a cursor for pins belonging to the same target netlist name and having a wiring type set to the first wiring type on the m target chips and the interposer, or in response to a trigger operation executed for a route view button in a menu bar in the target display interface.

22. The wiring method according to any one of claims 13 or 16, wherein:

responding to an input operation executed by a netlist name input box of the pin setting window or a selection operation executed by a netlist name list and a selection operation of a first wiring type executed by a wiring type list;

Displaying the m target chips and the interposer on the target display interface in response to a trigger operation performed for a first wiring diagram button in the target display interface;

and displaying connection lines of pins which belong to the same target netlist name and are set to be of a first wiring type on the m target chips and the interposer on the target display interface in response to connection operation of cursors for the pins which belong to the same target netlist name and are set to be of the first wiring type on the m target chips and the interposer, or in response to triggering operation executed for a route view button in a menu bar in the target display interface.

23. The wiring method according to any one of claim 2 to 11 or 13 to 17,

the intermediate layer is an active intermediate layer;

the connecting wire of the pin routed through the active interposer at least comprises a digital signal wire and an analog signal wire, wherein the digital signal wire is arranged in a digital channel, and the analog signal wire is arranged in an analog channel;

and responding to the triggering operation executed by the channel switching button of the target display interface, and setting a preset digital signal line in the analog channel.

24. A wiring device, characterized by comprising:

the device comprises a setting module, a first display interface and a second display interface, wherein the setting module is used for setting netlist names and wiring types of pins in n element modules in m target chips and an intermediate layer on the first display interface, wherein m and n are integers larger than 1, and the element modules in the intermediate layer are preset;

the setting module is further used for suspending a display pin setting window on the first display interface in response to a trigger operation executed for any pin of the n element modules in the m target chips and the interposer;

responding to the selection operation of a cursor for any target pin of the displayed target netlist name identifications, and responding to the selection operation of the cursor for pins which need to be connected with the target pins, wherein the pins selected by the cursor display the target netlist name identifications which are the same as the target pins and are defined as the netlist names and wiring types which are the same as the target pins;

And the wiring module is used for responding to the triggering operation executed by the target control in the first display interface, and displaying the wiring diagram generated according to the name of the pin netlist and the wiring type on the target display interface, wherein the wiring diagram displayed on the target display interface is used for displaying the connecting wires of the pins which belong to the same name of the target netlist and are set to be of the same wiring type on the m target chips and the interposer.

25. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the wiring method according to any one of claims 1 to 23 when the computer program is executed.

26. A computer-readable storage medium storing a computer program, characterized in that the computer program realizes the steps of the wiring method according to any one of claims 1 to 23 when the computer program is executed by a processor.