CN114664749A - Three-dimensional packaging structure for multi-chip device integration - Google Patents
Three-dimensional packaging structure for multi-chip device integration Download PDFInfo
- Publication number
- CN114664749A CN114664749A CN202210177136.4A CN202210177136A CN114664749A CN 114664749 A CN114664749 A CN 114664749A CN 202210177136 A CN202210177136 A CN 202210177136A CN 114664749 A CN114664749 A CN 114664749A
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- packaging
- working device
- embedding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 61
- 230000010354 integration Effects 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 46
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 238000002791 soaking Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 238000007789 sealing Methods 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 10
- 230000006872 improvement Effects 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a three-dimensional packaging structure for multi-chip device integration, which comprises a substrate, chip packaging units and working devices, wherein the surface of the substrate is provided with a plurality of packaging areas and a plurality of concave embedding areas; at least one chip packaging unit comprises a chip and a passive silicon medium layer, wherein the chip is inverted and is in bonding connection with the top surface of the passive silicon medium layer, and the passive silicon medium layer is connected with the substrate through bumps arranged on the bottom surface. The three-dimensional packaging structure for multi-chip device integration has the advantages of simple arrangement, good heat dissipation performance, difficulty in warping, capability of additionally arranging a packaged chip and an electronic device and the like.
Description
Technical Field
The invention relates to the technical field of three-dimensional packaging, in particular to a three-dimensional packaging structure for multi-chip device integration.
Background
Currently, as semiconductor process approaches physical limits, advanced three-dimensional packaging technology has become another way for the industry to continue moore's law. Advanced three-dimensional packaging enables the system to be higher in integration level, smaller in size and more excellent in performance, and meanwhile, the cost and power consumption of system integration can be reduced.
The existing 2.5D package technology mainly utilizes micro bumps (u bumps) and Through Silicon Vias (TSV) to redesign the interconnection lines between the substrate and the chip by using an Interposer (Interposer), thereby achieving the stacked package of the chip. In the packaging process, firstly, a chip to be packaged is prepared, the front surface of the chip is provided with a bump, the back surface of the chip is thinned, and a known good chip (KGD) is cut for standby application without packaging. Then, layout of TSV, a redistribution layer and a bump is carried out on a bare wafer, the back of the wafer is thinned, the bump is manufactured, and a passive silicon medium layer is manufactured; the KGD is then flipped over, aligned, bonded face-to-face with the passive silicon interposer, and the whole is connected to the package substrate via the bumps. The packaging method can generate huge heat, so that huge pressure for heat dissipation is caused, and the electric performance of the chip is influenced.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a three-dimensional packaging structure for multi-chip device integration, which is simple in arrangement, good in heat dissipation performance, not easy to warp and capable of additionally arranging a packaging chip and an electronic device.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a three-dimensional packaging structure for multi-chip device integration comprises a substrate, chip packaging units and working devices, wherein a plurality of packaging areas and a plurality of concave embedding areas are arranged on the surface of the substrate, each chip packaging unit is packaged and connected at the packaging area, and each working device is embedded and connected in the embedding area; at least one chip packaging unit comprises a chip and a passive silicon medium layer, wherein the chip is inverted and is in bonding connection with the top surface of the passive silicon medium layer, and the passive silicon medium layer is connected with the substrate through bumps arranged on the bottom surface.
As a further improvement of the above technical solution:
the chip packaging unit comprises a plurality of chips, each chip is connected to the top surface of the passive silicon medium layer, silicon through hole connection areas are arranged at the connection positions of the passive silicon medium layer corresponding to the chips, and the silicon through holes in the silicon through hole connection areas are connected with the chips and the bumps on the bottom surface of the passive silicon medium layer.
The depth of the embedding area is smaller than the thickness of the working device, and the top surface of the working device exposed out of the embedding area is connected to the surface of the substrate through the copper-plated circuit.
The depth of the embedding area is larger than the thickness of the working device, after the working device is installed in the embedding area, the opening of the embedding area is sealed by adopting the material of the substrate, and the working device is connected to the surface of the substrate by adopting a copper-plated hole arranged on the sealing structure.
The three-dimensional packaging structure for multi-chip device integration also comprises a soaking plate, wherein the soaking plate is covered outside each chip packaging unit and the working device, and the edge of the soaking plate is connected with the substrate.
The chip packaging unit also comprises a thermal interface material layer, and the thermal interface material layer is positioned between the chip and a soaking plate outside the chip packaging unit.
And the surfaces of the two sides of the substrate are symmetrically provided with the packaging areas and the embedding areas, and are symmetrically connected with the chip packaging units and the working device.
Compared with the prior art, the invention has the advantages that:
the three-dimensional packaging structure for multi-chip device integration is different from the conventional packaging form in that a substrate and a chip are not arranged correspondingly, the structural form that the chip and the substrate are integrally taken as a component unit is not adopted, a plurality of packaging areas and a plurality of concave embedding areas are arranged on the surface of the substrate, the chip and a passive silicon middle level of the chip are taken as an integral unit, a plurality of chip packaging units are packaged and connected at the packaging areas, and all working devices are embedded and connected in the embedding areas, so that all chips and devices required by equipment functions are integrated as far as possible on one substrate.
The three-dimensional packaging structure firstly enables the area of the substrate to be obviously increased, when the chip packaging unit or the working device is connected, the size of the packaging body is increased due to the increase of the area of the corresponding substrate, the heat bearing capacity is improved, meanwhile, the soaking plate is utilized to uniformly radiate heat, the heat radiation performance is also obviously improved, and the improvement of the performance of the chip or the device is facilitated. Compared with an independent packaging component, the structure also improves the area utilization rate of the substrate, further improves the integration level of system-in-package, achieves better system electrical performance, and improves board-level reliability. Meanwhile, as the working device for executing work is integrated, the working device is more directly connected with the chip, and the connection reliability and the accuracy of information transmission are improved.
Drawings
Fig. 1 is a schematic diagram of a three-dimensional package structure for multi-chip device integration of the present invention.
Illustration of the drawings: 1. a substrate; 11. a packaging region; 12. an embedding region; 2. a chip packaging unit; 21. a chip; 22. a passive silicon interposer; 23. a layer of thermal interface material; 3. a working device; 4. a soaking plate.
Detailed Description
In order to facilitate understanding of the invention, the invention will be described more fully and in detail with reference to the accompanying drawings and preferred embodiments, but the scope of the invention is not limited to the specific embodiments below.
Example (b):
as shown in fig. 1, the three-dimensional package structure for multi-chip device integration of the present embodiment includes a substrate 1, chip package units 2 and working devices 3, wherein a plurality of package regions 11 and a plurality of recessed embedding regions 12 are disposed on a surface of the substrate 1, each chip package unit 2 is packaged and connected at the package region 11, and each working device 3 is embedded and connected in the embedding region 12; the at least one chip package unit 2 includes a chip 21 and a passive silicon interposer 22, the chip 21 is flipped and bonded to the top surface of the passive silicon interposer 22, and the passive silicon interposer 22 is connected to the substrate 1 through bumps disposed on the bottom surface.
In the package structure of the embodiment, the substrate 1 and the chip 21 are not arranged correspondingly, the chip 21 and the substrate 1 are not used as a whole as a component unit, but the chip 21 and the passive silicon interposer 22 are used as a whole unit, a plurality of chip package units 2 are packaged and connected at the package region 11, and the working devices 3 are embedded and connected in the embedding region 12, so that all the chips 21 and the working devices 3 required by the device functions are integrated into one substrate 1 as much as possible.
The three-dimensional packaging structure firstly enables the area of the substrate 1 to be obviously increased, when the chip packaging unit 2 or the working device 3 is connected, the area of the corresponding substrate 1 is increased, the packaging part can not be used for heat dissipation only by the substrate 1 of the corresponding part in the packaging process, the size of the packaging body is increased, the heat bearing capacity is improved, meanwhile, the soaking plate 4 is used for heat dissipation, the uniform heat dissipation performance is also obviously improved, and the improvement of the performance of the chip 21 or the working device 3 is facilitated. Compared with a single packaging component, the structure further improves the integration level of system-in-package, achieves better system electrical performance and improves board-level reliability. Meanwhile, as the working device 3 for executing work is integrated, the connection between the working device 3 and the chip 21 is more direct, and the connection reliability and the accuracy of information transmission are improved. The working device 3 in this embodiment is a common device that is required by the package structure to implement the work, and may be replaced and selected according to the work requirement, which is not described herein.
In this embodiment, two kinds of chip package units 2 are provided, one kind of chip package unit 2 includes a plurality of chips 21, each chip 21 is connected to the top surface of the passive silicon interposer 22, the passive silicon interposer 22 is provided with a through-silicon-via connection region corresponding to the connection position of each chip 21, and each through-silicon-via in the through-silicon-via connection region is connected to the chip 21 and the bump on the bottom surface of the passive silicon interposer 22. In another chip packaging unit 2, the chip 21 is packaged by using a common packaging technology, and belongs to a simple chip 21 with a small number of pins, such as chips 21 of power management, sensors, and the like.
In this embodiment, the substrate 1 is made of an organic resin (e.g., epoxy resin), as shown in the right working device 3 of fig. 1, the depth of the embedded region 12 may be smaller than the thickness of the working device 3, each working device 3 is tiled in the embedded region 12, the top surface of the working device 3 exposed from the embedded region 12 is connected to the surface of the substrate 1 through a copper-plated wire, and then the encapsulation is formed by injecting the organic resin into the surface. As shown in the working device 3 on the left side of fig. 1, the depth of the embedding region 12 may be made larger than the thickness of the working device 3, and after the working device 3 is mounted on the embedding region 12, the opening of the embedding region 12 may be closed with the same organic resin material as the substrate 1, and the working device 3 may be connected to the surface of the substrate 1 with a copper-plated hole provided in the closed structure.
In this embodiment, the three-dimensional package structure for multi-chip device integration further includes a vapor chamber 4, the vapor chamber 4 covers the exterior of each chip package unit 2 and the working device 3, and fills in the gap between each component to play a role in protection and heat dissipation, and the edge of the vapor chamber is connected to the substrate 1. The soaking plate 4 can effectively protect the chip packaging unit 2 and the working device 3 from being interfered by the external environment.
In this embodiment, the chip packaging unit 2 further includes a thermal interface material layer 23, and the thermal interface material layer 23 is made of a conventional thermal interface material, which can reduce the thermal contact resistance between the heat dissipation device and the heat generation device when the material is coated between the heat dissipation device and the heat generation device. And thus is disposed between the chip 21, which mainly generates heat, and the soaking plate 4 outside the chip-packaging unit 2, and heat dissipation of the chip 21 can be further facilitated.
In this embodiment, the substrate 1 may be provided with a single-sided connection structure in a manner that is not highly required. Under the use condition with higher requirements on the substrate 1, the package regions 11 and the embedding regions 12 can be symmetrically arranged on the two side surfaces of the substrate 1 according to requirements, and the chip package units 2 and the working devices 3 can be symmetrically connected. The structure that the symmetry set up makes base plate 1 atress more even stable with being heated, avoids base plate 1 warpage.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-described embodiments. It should be apparent to those skilled in the art that modifications and variations can be made without departing from the technical spirit of the present invention.
Claims (7)
1. A three-dimensional packaging structure for multi-chip device integration is characterized in that: the packaging structure comprises a substrate (1), chip packaging units (2) and working devices (3), wherein a plurality of packaging areas (11) and a plurality of concave embedding areas (12) are arranged on the surface of the substrate (1), each chip packaging unit (2) is packaged and connected at the packaging area (11), and each working device (3) is embedded and connected in the embedding area (12); the chip packaging unit (2) comprises a chip (21) and a passive silicon intermediate layer (22), wherein the chip (21) is flipped and is in bonding connection with the top surface of the passive silicon intermediate layer (22), and the passive silicon intermediate layer (22) is connected with the substrate (1) through bumps arranged on the bottom surface.
2. The three-dimensional package structure for multi-chip device integration of claim 1, wherein: the chip packaging unit (2) comprises a plurality of chips (21), each chip (21) is connected to the top surface of the passive silicon medium layer (22), the passive silicon medium layer (22) is provided with a silicon through hole connection area corresponding to the connection position of each chip (21), and each silicon through hole in the silicon through hole connection area is connected with the chip (21) and the lug on the bottom surface of the passive silicon medium layer (22).
3. The three-dimensional package structure for multi-chip device integration of claim 1, wherein: the depth of the embedding region (12) is smaller than the thickness of the working device (3), and the top surface of the working device (3) exposed out of the embedding region (12) is connected to the surface of the substrate (1) through a copper-plated circuit.
4. The three-dimensional package structure for multi-chip device integration of claim 1, wherein: the depth of the embedding area (12) is larger than the thickness of the working device (3), after the working device (3) is installed in the embedding area (12), the opening of the embedding area (12) is sealed by the material of the substrate (1), and the working device (3) is connected to the surface of the substrate (1) through a copper-plated hole arranged on the sealing structure.
5. The three-dimensional package structure for multi-chip device integration of claim 1, wherein: the chip packaging structure is characterized by further comprising a soaking plate (4), wherein the soaking plate (4) covers the outer parts of the chip packaging units (2) and the working device (3), and the edges of the soaking plate (4) are connected with the substrate (1).
6. The three-dimensional package structure for multi-chip device integration of claim 5, wherein: the chip packaging unit (2) further comprises a thermal interface material layer (23), and the thermal interface material layer (23) is located between the chip (21) and a soaking plate (4) outside the chip packaging unit (2).
7. The three-dimensional package structure for multi-chip device integration according to any one of claims 1 to 6, wherein: the two side surfaces of the substrate (1) are symmetrically provided with the packaging areas (11) and the embedding areas (12) and are symmetrically connected with the chip packaging units (2) and the working device (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210177136.4A CN114664749A (en) | 2022-02-25 | 2022-02-25 | Three-dimensional packaging structure for multi-chip device integration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210177136.4A CN114664749A (en) | 2022-02-25 | 2022-02-25 | Three-dimensional packaging structure for multi-chip device integration |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114664749A true CN114664749A (en) | 2022-06-24 |
Family
ID=82026925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210177136.4A Pending CN114664749A (en) | 2022-02-25 | 2022-02-25 | Three-dimensional packaging structure for multi-chip device integration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114664749A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115758983A (en) * | 2022-11-14 | 2023-03-07 | 深圳市奇普乐芯片技术有限公司 | Wiring method, device, terminal and storage medium |
-
2022
- 2022-02-25 CN CN202210177136.4A patent/CN114664749A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115758983A (en) * | 2022-11-14 | 2023-03-07 | 深圳市奇普乐芯片技术有限公司 | Wiring method, device, terminal and storage medium |
| CN115758983B (en) * | 2022-11-14 | 2023-10-20 | 深圳市奇普乐芯片技术有限公司 | Wiring method, wiring device, terminal and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11177217B2 (en) | Direct bonded heterogeneous integration packaging structures | |
| US10083919B2 (en) | Packaging for high speed chip to chip communication | |
| US10867897B2 (en) | PoP device | |
| US7656015B2 (en) | Packaging substrate having heat-dissipating structure | |
| US20150221625A1 (en) | Semiconductor package having a dissipating plate | |
| TW201351579A (en) | High density 3D package | |
| KR20120001340A (en) | An embedded chip on chip package and package on package including the same | |
| KR20080038035A (en) | Semiconductor package and stacked layer type semiconductor package | |
| WO2002103793A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN100448003C (en) | Semiconductor device | |
| TWI635585B (en) | Semiconductor package and method of manufacture | |
| US20150187675A1 (en) | Methods and apparatus for dissipating heat from a die assembly | |
| KR20150137976A (en) | Semiconductor package having heat dissipating member | |
| KR20170027391A (en) | Semiconductor package on which a plurality of chips is embedded and method of manufacturing the same | |
| CN113192936A (en) | Double-sided chip packaging structure | |
| KR20120040536A (en) | Semiconductor packages and methods of fabricating the same | |
| CN108807361B (en) | Three-dimensional packaging structure of chip stack | |
| TWI391084B (en) | Pcb structure having heat-dissipating member | |
| CN114664749A (en) | Three-dimensional packaging structure for multi-chip device integration | |
| US10629536B2 (en) | Through-core via | |
| CN112397475A (en) | Fan-out type packaging chip structure and unit with fine-pitch through-silicon-via packaging | |
| US11749583B2 (en) | Electronic package and method for manufacturing the same | |
| CN114334945B (en) | Packaging structure and manufacturing method | |
| US20200051897A1 (en) | Semiconductor package | |
| TW202339130A (en) | Electronic package and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20240204 Address after: East, 2nd floor, building C, Lugu high level Talents Innovation and entrepreneurship Park, 1698 Yuelu West Avenue, Changsha hi tech Development Zone, Hunan 410000 Applicant after: Changsha Anmuquan Intelligent Technology Co.,Ltd. Country or region after: China Address before: 410083 Hunan province Changsha Lushan Road No. 932 Applicant before: CENTRAL SOUTH University Country or region before: China |
|
| TA01 | Transfer of patent application right |