KR20150137976A - Semiconductor package having heat dissipating member - Google Patents

Abstract

A semiconductor package comprises: a substrate including an upper surface and a lower surface; a semiconductor chip mounted on the upper part of the substrate, and having a first recess unit on an upper part of the semiconductor chip; a molding member formed to cover the semiconductor chip in the upper part of the substrate by exposing the upper part of the semiconductor chip; and a first dissipating member formed on the first recess unit. The first dissipating member includes a moisture absorbing particle, and a heat dissipating molding member.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor package having a heat dissipating member,

Technical aspects of the present invention relate to a semiconductor package, and more particularly to a semiconductor package that emits heat through a heat dissipating member.

2. Description of the Related Art In recent years, as a semiconductor device such as a mobile terminal has become highly integrated, performs a multifunction, and power consumption of a semiconductor device has increased, heat dissipation capability of the semiconductor device has become important. On the other hand, there is a space limitation for heat dissipation in a highly integrated semiconductor device, and accordingly, there is a demand for a semiconductor package technology capable of efficiently performing a heat dissipation function and utilizing space so as to be suitable for high integration.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor package capable of effectively releasing heat that may be involved in the operation of a semiconductor package to maintain operation stability.

According to an aspect of the present invention, there is provided a semiconductor package comprising: a substrate having an upper surface and a lower surface; a semiconductor chip mounted on an upper surface of the substrate and having a first recess portion on an upper surface; And a first heat dissipation member formed on the first recess portion, wherein the first heat dissipation member includes a moisture absorption particle and a heat dissipation molding member do.

In some embodiments, the top surface of the semiconductor chip includes a protrusion defined by the first recess portion, and the protrusion may have a matrix structure.

The first recess may have a depth of less than 100 um.

In some embodiments, the semiconductor package may further include a second recess portion provided on an upper surface of the molding member, and a second heat dissipating member formed on the second recess portion.

The hygroscopic particles can absorb moisture around the semiconductor package at room temperature. The hygroscopic particles may be selected from the group consisting of sodium polyacrylate, polyacrylic alcohol-based copolymer, crosslinked polyacrylamide, potassium polyacrylate, polyacrylic acid Polyacrylic acid, silicagel, molecular sieve, montmorillonite clay, and zeolite. The material may be at least one of the following materials: polyacrylic acid, silicagel, molecular sieve, montmorillonite clay, and zeolite.

In some embodiments, the heat dissipation molding member may comprise an epoxy-group molding resin or a polyimide-group molding resin.

The semiconductor package may further include a bump interposed between the semiconductor chip and the substrate, and the semiconductor chip may be mounted on the substrate via the bump.

The semiconductor package may further include an under fill between the semiconductor chip and the substrate to cover the bump.

In some embodiments, the substrate includes an opening slit formed in a central portion, and the semiconductor chip may be mounted face down on the substrate.

In some embodiments, the upper surface of the heat radiation member may be located at a lower level than the upper surface of the semiconductor chip. In some other embodiments, the upper surface of the heat radiation member may be located at the same level as the upper surface of the semiconductor chip. In some other embodiments, the upper surface of the heat radiation member may be located at a higher level than the upper surface of the semiconductor chip.

According to another aspect of the present invention, there is provided a semiconductor package comprising: a substrate having an upper surface and a lower surface; a semiconductor chip mounted on the upper surface of the substrate; A molding member having a recessed portion on an upper surface thereof, and a heat dissipating member formed on the recessed portion, wherein the heat dissipating member includes a moisture absorbing particle and a heat dissipating molding member.

In some embodiments, the lower surface of the recessed portion may be located at a higher level than the upper surface of the semiconductor chip.

According to another aspect of the present invention, there is provided a semiconductor package comprising: a substrate having an upper surface and a lower surface; a plurality of semiconductor chips stacked on an upper surface of the substrate; A first recess portion provided on the upper surface of the molding member and a first heat dissipation member formed on the first recess portion, wherein the first heat dissipation member includes a hygroscopic particle and a heat dissipation molding member can do.

In some embodiments, the molding member is formed to cover the semiconductor chips, exposing an upper surface of the semiconductor chip located at the uppermost portion of the semiconductor chips, wherein the semiconductor package is provided on the upper surface of the semiconductor chip A second recess portion, and a second heat dissipating member formed on the second recess portion.

The semiconductor chips may be stacked in a stepped manner.

In some embodiments, the semiconductor chips may include a first semiconductor chip including a through silicon via (TSV), and a second semiconductor chip stacked on the first semiconductor chip.

In some embodiments, the semiconductor package may further include a solder ball attached on a lower surface of the substrate.

The semiconductor package according to the technical idea of the present invention includes the heat dissipating member including the moisture absorbing particles, thereby absorbing the moisture around the semiconductor package and evaporating moisture absorbed therein, thereby releasing the heat of the semiconductor package to the outside. Furthermore, since the heat dissipating member is formed in the recess of the semiconductor chip or the molding member, the heat dissipating function can be efficiently performed in the highly integrated semiconductor device without increasing the volume of the semiconductor package.

1A is a plan view of a semiconductor package according to an embodiment of the present invention.
1B is a sectional view taken along the line A1-A1 'in FIG. 1A.
1C is an enlarged view of a region A of FIG. 1B.
FIGS. 2 and 3 are semiconductor packages according to other embodiments according to the technical idea of the present invention, in which the area corresponding to area A in FIG. 1B is partially enlarged.
4 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
5 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
6 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
7 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
8 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
9 is a cross-sectional view of a semiconductor package according to another embodiment of the present invention.
10A to 10D are cross-sectional views illustrating a method of fabricating a semiconductor package according to an embodiment of the present invention.
11 is a block diagram schematically illustrating a memory card including a semiconductor package according to some embodiments of the present invention.
12 is a block diagram schematically illustrating an electronic system including a semiconductor package according to some embodiments of the present invention.
FIG. 13 is a cross-sectional view schematically showing an SSD device to which a semiconductor package according to some embodiments of the present invention is applied. FIG. 13 shows an example in which the electronic system of FIG. 12 is applied to an SSD device.
14 is a cross-sectional view schematically illustrating an electronic device to which a semiconductor package according to some embodiments of the present invention is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and a duplicate description thereof will be omitted.

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various elements, regions, layers, regions and / or elements, these elements, components, regions, layers, regions and / It should not be limited by. These terms do not imply any particular order, top, bottom, or top row, and are used only to distinguish one member, region, region, or element from another member, region, region, or element. Thus, a first member, region, region, or element described below may refer to a second member, region, region, or element without departing from the teachings of the present invention. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical terms and scientific terms. In addition, commonly used, predefined terms are to be interpreted as having a meaning consistent with what they mean in the context of the relevant art, and unless otherwise expressly defined, have an overly formal meaning It will be understood that it will not be interpreted.

If certain embodiments are otherwise feasible, the particular process sequence may be performed differently from the sequence described. For example, two processes that are described in succession may be performed substantially concurrently, or may be performed in the reverse order to that described.

In the accompanying drawings, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein, but should include variations in shape resulting from, for example, manufacturing processes.

1A is a plan view of a semiconductor package 100 according to an embodiment of the present invention. 1B is a sectional view taken along the line A1-A1 'in FIG. 1A. 1C is an enlarged view of a region A of FIG. 1B.

1A to 1C, a semiconductor package 100 includes a substrate 110, a semiconductor chip 120 mounted on a top surface 110T of the substrate 110, an upper surface 110T of the substrate 110, A bump 150 connecting the substrate 110 and the semiconductor chip 120 and a bump 150 connecting the substrate 110 and the bottom surface 110B of the substrate 110. The bump 150 is formed to cover the side wall 120S of the substrate 120, And the heat dissipation member 130 formed on the recessed portion 122 of the semiconductor chip 120. [

The substrate 110 may be, for example, a printed circuit board (PCB). The printed circuit board may be a single-sided PCB or a double-sided PCB and may be a multi-layer PCB including one or more internal wiring patterns in the substrate. Further, the substrate 110 may be a rigid-PCB or a flexible-PCB.

In some embodiments, the substrate 110 may be made of, for example, an epoxy resin, a polyimide resin, a bismaleimide triazine (BT) resin, FR-4 (Flame Retardant 4), FR-5, Photosensitive liquid dielectrics, photosensitive dry-film dielectrics, polyimide flexible film thermally cured dry films, thermally cured liquid dielectrics, A resin coated copper foil (RCC), a thermoplastic, or a flexible resin.

In some embodiments, the substrate 110 may be formed by bonding a plurality of rigid plates or may be formed by adhering a rigid plate to a thin flexible printed circuit board. The plurality of rigid flat plates, or the printed circuit boards, which are adhered to each other, may each include a wiring pattern. In addition, the substrate 110 may comprise a low temperature co-fired ceramic (LTCC) substrate. The LTCC substrate may include a plurality of ceramic layers stacked, and may include a wiring pattern therein.

Although not shown, the substrate 110 may include at least one insulating layer (not shown) and a metal wiring layer (not shown). The metal wiring layer is a circuit pattern formed on the substrate 110. The metal wiring layer may be formed of aluminum (Al) or copper (Cu), for example. In some embodiments, the surface of the metallization layer may be plated with tin (Sb), gold (Au), nickel (Ni), or lead (Pb).

The substrate 110 includes a conductive pad 112 for connecting the semiconductor chip 120 and the substrate 110 via the bumps 150 and a solder ball 112 for connecting the semiconductor package 100 to an external circuit, And a solder ball pad 114 on which the solder balls 160 are located. The conductive pad 112 and the solder ball pad 114 may be formed of, for example, aluminum (Al) or copper (Cu). In some embodiments, the surface of the conductive pad 112 and the solder ball pad 114 may be plated with tin (Sb), gold (Au), nickel (Ni), or lead (Pb)

The substrate 110 may further include a via contact (not shown) that penetrates the top and bottom surfaces of the substrate 110 to connect the conductive pad 112 and the solder ball pad 114 to each other.

The semiconductor chip 120 may be mounted on the upper surface 110T of the substrate 110. [

In some embodiments, the semiconductor chip 120 may be a semiconductor chip that performs a variety of functions such as memory, logic, microprocessors, analog devices, digital signal processors, and system on chips. have. Also, the semiconductor chip 120 may be a multi-chip having a structure in which at least two or more semiconductor chips are stacked. For example, at least two or more semiconductor chips may all be the same type of memory device, one of the two or more semiconductor chips may be a memory device, and the other may be a micro-controller device.

The semiconductor chip 120 shown in FIG. 1B is mounted on the substrate 110 in a flip-chip bonding manner, but the mounting method of the semiconductor chip 120 is not limited thereto. For example, as shown in FIG. 6, the semiconductor chip 120 may be mounted on the substrate 110 in a wire bonding manner.

When the semiconductor chip 120 is mounted in a flip-chip bonding manner as shown in FIG. 1B, the semiconductor chip 120 may be connected to the substrate 110 through the bumps 150.

Meanwhile, in the case of the flip-chip bonding method, the molding member 140 may be formed through a MUF (Molded Under Fill) process. Here, the MUF process is a process of filling the space between the semiconductor chip 120 and the substrate 110 with an under fill (not shown) (110). ≪ / RTI > It is a matter of course that the molding member material covering the outer periphery of the semiconductor die 120 and the molding material material between the semiconductor die 120 and the substrate 110 are made identical when the molding member 140 is formed in the MUF process.

However, as shown in FIG. 1B, the molding member 140 may be formed without going through the MUF process.

That is, the semiconductor chip 120 is first filled with an underfill (not shown) between the semiconductor chip 120 and the substrate 110, and then an outer molding part of the semiconductor chip 120 is covered with an outer molding member It is possible. At this time, an underfill (not shown) for filling the gap between the semiconductor chip 120 and the substrate 110 and an outer molding member (not shown) for covering the outer periphery of the semiconductor chip 120 may be formed of the same material, .

Meanwhile, the semiconductor chip 120 in this embodiment may include a recess 122 formed in the upper surface 120T of the semiconductor chip 120. The recess 122 may be formed to have a depth 122D at which the radiation member 130, which will be described later, can sufficiently absorb moisture outside the semiconductor package 100. For example, the recessed portion 122 may be formed to have a depth 122D of 100 μm or less. The depth 122D of the recess 122 may be variously changed depending on the type and size of the semiconductor package 100 or the semiconductor chip 120. [

1A, an upper surface 120T of the semiconductor chip may include a protrusion 120D defined by the recess 122, and the protrusion 120D may include a matrix structure Lt; / RTI > However, the shape of the recessed portion 122 shown is merely exemplary, and the recessed portion may have various pattern structures on a plan view.

The heat dissipating member 130 may be formed in the recess 122.

In some embodiments, the top surface 130T of the heat dissipating member 130 may be located at a lower level than the top surface of the semiconductor chip 120T, as shown in Fig. 1C. That is, the heat dissipating member 130 may be formed to fill only a part of the recess 122.

The heat dissipation member 130 may radiate heat generated during the operation of the semiconductor package 100 to the outside of the semiconductor package 100.

Specifically, the heat radiation member 130 may include a heat dissipation molding member 132 and a moisture absorption particle 134.

The heat dissipating molding member 132 may perform a role of fixing the moisture absorbing particles 134 in the heat dissipating member 130 by using its own adhesiveness. In addition, the heat dissipation molding member 132 may serve to disperse heat of the semiconductor package 100.

The heat dissipating molding member 132 may include, for example, an epoxy-group molding resin or a polyimide-group molding resin. The epoxy-based molding resin may include, for example, a polyacrylic epoxy resin, a bisphenol-group epoxy resin, a naphthalene-group epoxy resin, an olocresol novolac epoxy resin, Dicyclopentadiene epoxy resin, biphenyl-group epoxy resin, phenol novolac epoxy resin, and the like may be used as the epoxy resin.

The heat dissipating molding member 132 is not limited to the molding resin and the like and may be formed of various materials capable of fixing the moisture absorbing particles 134 in the heat dissipating member 130 and dispersing the heat of the semiconductor package 100 Materials.

In some embodiments, the heat dissipation molding member 132 may be cured by heat to maintain its shape without being subjected to heat associated with operation of the semiconductor package 100.

The moisture absorbing particles 134 absorb moisture around the semiconductor package 100 and evaporate moisture absorbed thereby to discharge the heat of the semiconductor package 100 to the outside.

More specifically, the moisture absorption particles 134 can absorb moisture around the semiconductor package 100 when the semiconductor package 100 is in the standby mode, that is, at a normal temperature before the semiconductor package 100 operates. When the semiconductor package 100 is in an operating state, moisture absorbed in the moisture absorption particles 134 can be evaporated through the heat generated by the semiconductor package 100. In the evaporation process, a part of the heat generated in the semiconductor package 100 is used as heat of vaporization, so that part of the heat accompanying the operation of the semiconductor package 100 can be removed.

On the other hand, the moisture absorption and evaporation of the hygroscopic particles 134 are not limited to those described above, but can be performed within various temperature ranges depending on the material of the hygroscopic particles 134.

For example, the moisture absorption of the moisture absorption particles 134 can be achieved not only at the normal temperature state before the semiconductor package 100 operates, but also at the semiconductor package 100 operating state at a temperature below a certain temperature (for example, 100 ° C) have. In this case, the absorbed moisture may be evaporated in a semiconductor package 100 operating state at the predetermined temperature or higher.

The hygroscopic particles 134 may be made of various materials having strong water absorption properties. For example, the hygroscopic particles 134 may be formed of a material selected from the group consisting of sodium polyacrylate, a polyacrylic alcohol-based copolymer, a crosslinked polyacrylamide, a potassium polyacrylate A material such as polyacrylate, polyacrylic acid, silicagel, molecular sieve, montmorillonite clay, and zeolite may be used.

The molding member 140 may seal the semiconductor chip 120 on the upper surface 110T of the substrate 110 to protect the semiconductor chip 120 from the risk factors of the external environment.

The top surface 140T of the molding member 140 may be located at the same level as the top surface 120T of the semiconductor chip 120. In some embodiments, That is, the molding member 140 in this embodiment is formed so as to cover only the side wall 120S of the semiconductor chip 120 and expose the upper surface 120T of the semiconductor chip 120, but the present invention is not limited thereto. For example, as shown in FIG. 5, the molding member 540 may be formed to cover both the upper surface 520T and the side wall 520S of the semiconductor chip 520. FIG.

The molding member 140 may include an epoxy-group molding resin or a polyimide-group molding resin. The molding member 140 may be formed of the same material as the heat dissipating molding member 132 described above, but it is not limited thereto and may be formed of a material different from the heat dissipating molding member 132.

In some embodiments, the molding resin may contain a colorant, carbon black. On the other hand, the molding resin may further contain a curing agent, a curing accelerator, a filler, and a flame retardant in addition to carbon black as a colorant.

Examples of the curing agent include an amine, a polycyclic aromatic phenol resin, a phenol novolac resin, a cresol novolac resin, a dicyclopentadiene phenol resin, Resin (Dicyclopentadiene Phenol Resin), xylyl resin, naphthalene resin and the like can be used.

The curing accelerator is a catalyst component for accelerating the curing reaction between the epoxy molding resin and the curing agent. Examples of the curing accelerator include benzyldimethylamine, triethanolamine, triethylenediamine, dimethylaminoethanol, tri (dimethylaminomethyl) Imidazoles such as tertiary amines such as 2-methylimidazole and 2-phenylimidazole, organic phosphines such as triphenylphosphine, diphenylphosphine and phenylphosphine, tetraphenylphosphonium tetraphenylborate, triphenyl And tetraphenylboron salts such as phosphine tetraphenylborate.

In some embodiments, a silica filler or the like may be used as the filler, and a brominated epoxy resin, antimony oxide, metal hydrate or the like may be used as the flame retardant.

Further, the molding resin may further contain a release agent such as a higher fatty acid, a higher fatty acid metal salt, an ester wax and the like, and a stress relaxation agent such as a modified silicone oil, a silicone powder, and a silicone resin, if necessary.

The molding resin may have a viscosity suitable for the molding conditions. For example, the molding resin may be a fluid solid such as a gel.

Since the semiconductor package 100 includes the heat radiation member 130 as in the present embodiment, sufficient heat radiation can be performed without increasing the volume of the semiconductor package 100. [

FIGS. 2 and 3 are semiconductor packages 200 and 300 according to another embodiment of the present invention, which are partially enlarged regions corresponding to region A of FIG. 1B.

Each of the semiconductor packages 200 and 300 of FIGS. 2 and 3 may have a structure similar to that of the semiconductor package 100 described with reference to FIGS. 1A through 1C except for the structure of the heat radiation members 230 and 330, Only the differences between the heat radiation members 230 and 330 will be briefly described.

Referring to FIG. 2, a heat dissipating member 230 is formed on a recess 122 formed on an upper surface of the semiconductor chip 120. The upper surface 230T of the heat radiation member 230 may be located at the same level as the upper surface of the semiconductor chip 120T. That is, the heat dissipating member 230 may be formed to fill the recess 122.

According to the present embodiment, the maximum amount of water absorption of the heat dissipating member 230 can be increased by filling the recess 122 with the heat dissipating member 230, and the space occupied by the semiconductor package 200 can be efficiently .

Referring to FIG. 3, a heat dissipating member 330 is formed on a recess 122 formed on an upper surface of the semiconductor chip 120. The upper surface 330T of the heat radiation member 330 may be located at a higher level than the upper surface of the semiconductor chip 120T. That is, the heat dissipating member 330 may be formed beyond the recess 122.

According to this embodiment, the maximum moisture absorption amount of the heat radiation member 330 is increased, and the surface area of the heat radiation member 330 is enlarged, so that water absorption and evaporation can be more efficiently performed.

4 is a cross-sectional view of a semiconductor package 400 according to another embodiment of the present invention. In FIG. 4, the same reference numerals as in FIGS. 1A to 3 denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

4, a semiconductor package 400 includes a substrate 110, a semiconductor chip 420 mounted on a top surface 110T of the substrate 110, an upper surface 110T of the substrate 110, A bump 150 connecting the substrate 110 and the semiconductor chip 420, a solder ball 160 attached to the lower surface 110B of the substrate 110, The first heat dissipation member 430_1 formed on the first recess portion 422_1 of the chip 420 and the second heat dissipation member 430_2 formed on the second recess portion 422_2 of the molding member 440 have.

The semiconductor package 400 according to the present embodiment has a structure substantially similar to that of the semiconductor package 100 described with reference to FIG. 1B, but the upper surface 420T of the semiconductor chip 420 as well as the upper surface 440T of the molding member 440 The heat dissipation member 430_2 is also formed.

The semiconductor package 400 includes a first heat dissipation member 430_1 formed on the first recess portion 422_1 of the semiconductor chip 420 and a second heat dissipation member 430_1 formed on the second recess portion 422_2 of the molding member 440. [ And a heat dissipation member 430_2.

Unlike the semiconductor package 100 of FIG. 1B and the semiconductor package 400 of FIG. 4, the semiconductor package (not shown) has a heat dissipating member only on the upper surface of the molding member and a heat dissipating member formed on the upper surface of the semiconductor chip Of course.

Each of the semiconductor chip 420 and the molding member 440 may have a structure similar to that of each of the semiconductor chip 120 and the molding member 140 described with reference to FIG. 1B except for the difference described above. A description thereof will be omitted.

The first heat radiation member 430_1 may include a first heat dissipation molding member 432_1 and first moisture absorption particles 434_1 and the first heat dissipation molding member 432_1 and the first moisture absorption particles 434_1 may include a first heat dissipation member 432_1 and a first heat dissipation particle 434_1, The heat dissipating member 132 and the moisture absorbing particles 134 described with reference to Figs.

The second heat radiation member 430_2 may be formed in the second recess portion 422_2 formed on the upper surface 440T of the molding member 440. [

In some embodiments, each of the second heat dissipating molding member 432_2 and the second moisture absorbing particles 434_1 of the second heat dissipating member 430_2 is formed of the first heat dissipating molding member 432_1 and the first moisture absorbing particles 434_1 But the present invention is not limited thereto.

When the heat radiation member 430_2 is formed not only on the upper surface 420T of the semiconductor chip 420 but also on the upper surface 440T of the molding member 440 as in the present embodiment, By increasing the maximum moisture absorption amount of the heat radiation member 230, a better heat radiation function can be performed.

5 is a cross-sectional view of a semiconductor package 500 according to another embodiment of the present invention. In FIG. 5, the same reference numerals as in FIGS. 1A to 4 denote the same members, and a duplicate description thereof will be omitted for the sake of brevity.

5, a semiconductor package 500 includes a substrate 110, a semiconductor chip 520 mounted on a top surface 110T of the substrate 110, an upper surface 110T of the substrate 110, A bump 150 connecting the substrate 110 and the semiconductor chip 520, a solder ball 160 attached to the lower surface 110B of the substrate 110, And a heat dissipating member 530 formed in the recessed portion 542 of the molding member 540.

The semiconductor package 500 in this embodiment has a structure substantially similar to that of the semiconductor package 100 described with reference to FIG. 1B, but the molding member 540 is formed on the upper surface 520T as well as the side wall 520S of the semiconductor chip 520T. ) There is also a difference in covering points.

Accordingly, the heat radiation member 530 may be formed on the upper surface 540T of the molding member 540. [

Each of the semiconductor chip 520, the heat dissipating member 530 and the molding member 540 shown in the figures may have the same structure as the semiconductor chip 120, the heat dissipating member 130 and the molding member 140 ), And thus a description thereof will be omitted.

6 is a cross-sectional view of a semiconductor package 600 according to another embodiment of the present invention. In Fig. 6, the same reference numerals as in Figs. 1A to 5 denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

6, the semiconductor package 600 includes a substrate 610, a semiconductor chip 620 mounted on a top surface 610T of the substrate 610, a top surface 610T of the substrate 610, and a semiconductor chip 620. [ A bonding wire 650 connecting the substrate 610 and the semiconductor chip 620, a solder ball 160 attached to the lower surface 610B of the substrate 610, And a heat dissipating member 630 formed in the recess portion 642 of the molding member 640.

The semiconductor package 600 in this embodiment has a structure substantially similar to that of the semiconductor package 500 described with reference to FIG. 5, but there is a difference only in that the semiconductor chip 620 is mounted by wire bonding.

Each of the substrate 610, the semiconductor chip 620, the heat dissipating member 630 and the molding member 640 shown in the figures may have the same structure as that of the substrate 110, the semiconductor chip 520, the heat dissipating member 530, and the molding member 540, the description thereof will be omitted.

When the semiconductor chip 620 is mounted by wire bonding, the semiconductor chip 620 is attached to the upper surface 610T of the substrate 610 through an adhesive tape 652 or the like, 620 and the substrate 610 may be electrically connected through a bonding wire 650. For example, one end of the bonding wire 650 is connected to a conductive pad 612 formed on an upper surface 610T of the substrate 610 and the other end is connected to a chip conductive pad (not shown) formed on an upper surface 620T of the semiconductor chip 620 622 so that the semiconductor chip 620 and the substrate 610 can be electrically connected to each other.

In some embodiments, the bonding wires 650 may be formed of gold (Au) or aluminum (Al) wires, and the bonding wires 650 may be any of ball-bonding and wedge bonding. Can be formed.

In some embodiments, the bonding wires 650 may be bound by either a thermo compression connection or an ultrasonic connection, and may be bonded to a thermal sound wave thermo sonic) connection method.

7 is a cross-sectional view of a semiconductor package 700 according to another embodiment of the present invention. In Fig. 7, the same reference numerals as in Figs. 1A to 6 denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

7, a semiconductor package 700 includes a substrate 710, a semiconductor chip 720 mounted on a top surface 710T of the substrate 710, an upper surface 710T of the substrate 710, A second molding member 740_2 formed to cover a part of the lower surface 710B of the substrate 710 and a part of the lower surface 720B of the semiconductor chip, 720 to the upper surface 710T of the substrate 710, a bonding wire 750 connecting the substrate 710 and the semiconductor chip 720 to the lower surface 710B of the substrate 710, And the heat dissipating member 730 formed in the recessed portion 742 of the first molding member 740_1.

The semiconductor package 700 in this embodiment has a substantially similar structure to the semiconductor package 600 described with reference to FIG. 6, but there is a difference only in the mounting structure of the substrate 710 and the semiconductor chip 720.

The substrate 710 may include an opening slit 711 formed in a central portion of the substrate 710, a plurality of solder ball pads 714 formed on the substrate 710 in the substrate 710 and a conductive pad 712.

Further, the substrate 710 may include at least one or more insulating layers (not shown) and a metal wiring layer (not shown). Further, the substrate 710 may further include a protective layer (not shown) that exposes only the solder ball pad 714 and the conductive pad 712, and covers all the remaining areas. The protective layer may be formed as an SMD type that partially exposes the solder ball pad 714 and the conductive pad 712 or may be formed as an NSMD type that exposes the solder ball pad 714 and the conductive pad 712 as a whole It is possible.

The opening slit 711 is formed to penetrate the upper surface 710T and the lower surface 710B of the substrate 710 so as to allow the semiconductor chip 720 to be mounted face down have.

The semiconductor chip 720 is mounted on the upper surface 710T of the substrate 710. The semiconductor chip 720 may be a semiconductor chip that performs various functions such as a memory, logic, microprocessor, analog device, digital signal processor, and system-on-chip, similar to the semiconductor chip 120 described above with reference to FIG. The semiconductor chip 720 may be a multi-chip having a structure in which at least two or more semiconductor chips are stacked.

The semiconductor chip 720 may be mounted in a face down type as shown in Fig. More specifically, the chip conductive pads 723 of the semiconductor chip 720 are arranged in the central region of the lower surface 720B of the semiconductor chip 720, and the chip conductive pads 723 are arranged in the opening slit 711 formed in the substrate 710, May be electrically connected to the conductive pads 712 through bonding wires 750 extending through the conductive pads 712. [

The heat dissipating member 730 may discharge heat generated during the operation of the semiconductor package 700 to the outside of the semiconductor package 700.

The heat dissipating member 730 may include a heat dissipating molding member 732 and moisture absorbing particles 734 and each of the heat dissipating molding member 732 and the moisture absorbing particles 734 may be formed of the heat dissipating molding member 132 described with reference to FIG. And the hygroscopic particles 134, so that a description thereof will be omitted.

The first molding member 740_1 may be formed to cover the upper surface 710T of the substrate 710 and the semiconductor chip 720. [

The second molding member 740_2 is formed to cover a part of the lower surface 710B of the substrate 710, a part of the lower surface 720B of the semiconductor chip, and the bonding wire 750, From the risk factors of the.

The first molding member 740_1 and the second molding member 740_2 may be formed of a material similar to the molding member 140 described with reference to FIG. 1B.

The first molding member 740_1 and the second molding member 740_2 may be formed of the same material through one process, but the present invention is not limited thereto. The second molding member 740_2 may be formed of the same material as the first molding member 740_1 May be formed through a manufacturing process different from the manufacturing process of the first molding member 740_1 using a different material from the first molding member 740_1.

8 is a cross-sectional view of a semiconductor package 800 according to another embodiment of the present invention. In Fig. 8, the same reference numerals as in Figs. 1A to 6 denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

8, the semiconductor package 800 includes a substrate 110, an inner substrate 820_1 formed on the upper surface of the substrate 110, a semiconductor chip 820_2 formed on the upper surface of the inner substrate 820_1, a substrate 110, A molding member 840 formed to cover the upper surface 110T of the substrate 110, the inner substrate 820_1 and the semiconductor chip 820_2, a solder ball 160 attached to the lower surface 110B of the substrate 110, a molding member 840 And a heat dissipating member 830 formed in the recessed portion 842 of the heat dissipation member 830. [

The semiconductor package 800 in this embodiment has a structure substantially similar to that of the semiconductor package 500 described with reference to FIG. 5, but an internal substrate 820_1 formed between the substrate 110 and the semiconductor chip 820_2 exists There is a difference only in points.

The inner substrate 820_1 may include a top pad 824, a through silicon via (TSV) 855, and a first bump 850_1. Although not shown, the inner substrate 820_1 further includes a lower pad (not shown) formed of a conductive material on the lower surface of the inner substrate 820_1 and electrically connecting the TSV 855 and the first bump 850_1 It is possible.

The inner substrate 820_1 may be formed based on an active wafer or an interposer substrate. Here, the active wafer refers to a wafer on which a semiconductor chip can be formed, such as a silicon wafer.

In the case where the inner substrate 820_1 is formed on the basis of an active wafer, the inner substrate 820_1 includes a semiconductor substrate (not shown), an integrated circuit layer (not shown), an interlayer insulating layer (not shown) ). A multilayer wiring layer (not shown) may be formed in the intermetal dielectric layer. Here, the semiconductor substrate may comprise a Group IV material wafer, such as a silicon wafer, or a Group III-V compound wafer. Further, the semiconductor substrate may be formed of a single crystal wafer such as a silicon single crystal wafer in terms of the formation method. However, semiconductor substrates are not limited to monocrystalline wafers, and various wafers such as epitaxial wafers, polished wafers, annealed wafers, and SOI (silicon on insulator) wafers can be used as semiconductor substrates . Here, the epitaxial wafer can be a wafer on which a crystalline material is grown on a single crystal silicon substrate.

When the inner substrate 820_1 is formed based on an active wafer, the inner substrate 820_1 can function as a memory element or a logic element. The memory device may include, for example, a DRAM, an SRAM, a flash memory, an EEPROM, a PRAM, an MRAM, and an RRAM.

On the other hand, even when the inner substrate 820_1 is formed on the basis of an active wafer, the inner substrate 820_1 includes only a semiconductor substrate and may not include an integrated circuit layer, an interlayer insulating layer, an intermetallic insulating layer, or the like.

When the inner substrate 820_1 is formed based on the interposer substrate, the inner substrate 820_1 may be formed based on silicon, glass, ceramic, plastic, or the like.

The upper pad 824 may be formed of a conductive material on the upper surface of the inner substrate 820 _ 1 and electrically connected to the TSV 855. The top pad 824 is shown connected directly to the TSV 855 while the top pad 824 may be connected to the TSV 855 via a wiring layer (not shown) in the inner substrate 820_1. The upper pad 824 may be formed of, for example, aluminum (Al), copper (Cu), or the like, and may be formed by a pulse plating method or a direct current plating method.

The TSV 855 penetrates the inner substrate 820_1 and can serve to connect the substrate 110 and the semiconductor chip 820_2.

The TSV 855 may comprise at least one metal. For example, TSV 855 may include a barrier metal layer (not shown) and a wiring metal layer (not shown). The barrier metal layer may include one or more laminated structures selected from titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). The wiring metal layer may be formed of a metal such as aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti), tungsten (W), zinc (Zn), zirconium (Zr). For example, the wiring metal layer may include one or more laminated structures selected from tungsten (W), aluminum (Al) and copper (Cu). However, the material of the TSV 855 is not limited to the above materials.

In some embodiments, the TSV 855 may be formed of any one of a Via-first, Via-middle, and Via-last structure. For reference, TSVs can be divided into via-first, via-middle, and via-last structures. The term "via-first" refers to a structure in which TSV is formed before an integrated circuit layer is formed, and "via-middle" refers to a structure in which TSV is formed before formation of a multilayer wiring layer after formation of an integrated circuit layer, Lt; RTI ID = 0.0 > TSV < / RTI >

The first bump 850_1 may function to electrically connect the TSV 855 of the inner substrate 820_1 and the upper pad 112 of the substrate 110. [ The first bump 850_1 may be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin, gold (Au), solder, or the like. However, the material of the first bump 850_1 is not limited thereto.

The semiconductor chip 820_2 may be connected to the inner substrate 820_1 through the second bump 850_2.

In this embodiment, only one semiconductor chip 820_2 is stacked on the internal substrate 820_1, but the present invention is not limited thereto. In some cases, a plurality of semiconductor chips may be stacked on the internal substrate 820_1. Unlike the internal substrate 820_1, the semiconductor chip 820_2 does not include the TSV and the upper pad, but the semiconductor chip 820_2 includes the TSV and the upper pad, and the semiconductor chip 820_2 A separate semiconductor chip may be additionally stacked.

The semiconductor chip 820_2 may be a memory device or a logic device. On the other hand, both the internal substrate 820_1 and the semiconductor chip 820_2 may be a memory element or a logic element, or one of them may be a memory element and the other may be a logic element. For example, the internal substrate 820_1 may be a logic device and the semiconductor chip 820_2 may be a memory device.

The heat dissipating member 830 may radiate heat generated during the operation of the semiconductor package 800 to the outside of the semiconductor package 800.

Although the molding member 840 in this embodiment is formed so as to cover the upper surface of the semiconductor chip 820_2 and the heat dissipating member 830 is formed only on the upper surface 840T of the molding member 840, It is not limited.

For example, the molding member 840 may expose the upper surface 820_2T of the semiconductor chip 820_2, similar to the molding member 140 described with reference to FIG. 1B. The heat dissipating member 830 may be formed on the upper surface of at least one of the upper surface 820_2T of the semiconductor chip 820_2 and the upper surface 840T of the molding member 840. In this case,

The heat dissipating member 830 may include a heat dissipating molding member 832 and a moisture absorbing particle 834 and each of the heat dissipating molding member 832 and the moisture absorbing particles 834 may include the heat dissipating molding member 132 described with reference to FIG. And the hygroscopic particles 134, so that a description thereof will be omitted.

The molding member 840 surrounds the inner substrate 820_1 and the semiconductor chip 820_2 on the substrate 110 and protects the inner substrate 820_1 and the semiconductor chip 820_2. The molding member 840 may be formed of, for example, a silicon-based material, a thermosetting material, a thermoplastic material, a UV treatment material, or the like.

9 is a cross-sectional view of a semiconductor package 900 according to another embodiment of the present invention. In Fig. 9, the same reference numerals as in Figs. 1A to 6 denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

9, a semiconductor package 900 includes a substrate 910, semiconductor chips 920 stacked on the substrate 910, a molding 920 formed to cover the semiconductor chips 920 on the substrate 910, A member 940, a solder ball 160 attached to the lower surface of the substrate 910 and a heat dissipating member 930 formed in the recessed portion 942 of the molding member 940.

The semiconductor package 900 in this embodiment has a structure substantially similar to that of the semiconductor package 600 described with reference to FIG. 6, except that there is a difference only in that a plurality of semiconductor chips 920 are stacked on the substrate 910 do.

The substrate 910 may include a conductive pad 912 formed on the upper surface 910T and a solder ball pad 914 formed on the lower surface 910B. The substrate 910 may be, for example, a printed circuit board, and the substrate 910 may have a structure similar to the substrate 110 described with reference to FIG. 1B except for the formation position of the conductive pad 912 and the like .

Each of the semiconductor chips 920 may have an upper surface 920T and a lower surface 920B opposite the upper surface 920T. A chip connection pad 923 may be positioned on one side edge region of the top surface 920T of each of the semiconductor chips 920.

These semiconductor chips 920 may be stacked stepwise such that each chip connection pad 923 is exposed on the upper surface 910T of the substrate 910. [

Although not shown, an adhesive member (not shown) may be formed on the lower surface 920B of each of the semiconductor chips 920. The adhesive member is made of any one of, for example, NCF (Non-Conductive Film), ACF (Anisotropic Conductive Film), UV film, instant adhesive, thermosetting adhesive, laser curing adhesive, ultrasonic curing adhesive and NCP Can be.

The stacked semiconductor chips 920 may be electrically connected to the substrate 910 through a connecting member 950. [

In some embodiments, the connecting member 950 may be a bonding wire as shown in Fig. The bonding wire may be gold, silver, copper, aluminum, or an alloy thereof. The connection member 950 may be any of connection means for electrically connecting the substrate 910 and the semiconductor chips 920 to each other. For example, the connection member 950 can be a solder ball, a bump, or a conductive vias, such as TSV, and combinations thereof

In some embodiments, semiconductor chips 920 may all be memory devices or logic devices. In some other embodiments, some semiconductor chips of semiconductor chips 920 may be memory devices, and some other semiconductor chips may be logic devices.

The heat dissipating member 930 may radiate heat generated during the operation of the semiconductor package 900 to the outside of the semiconductor package 900.

The heat dissipating member 930 may include a heat dissipating molding member 932 and moisture absorbing particles 934. Each of the heat dissipating molding member 932 and the moisture absorbing particles 934 may be formed of the heat dissipating molding member 132 described with reference to FIG. And the hygroscopic particles 134, so that a description thereof will be omitted.

The molding member 940 surrounds the semiconductor chips 920 on the substrate 910 and can protect the semiconductor chips 920. The molding member 940 may be formed of, for example, a silicon-based material, a thermosetting material, a thermoplastic material, a UV treatment material, or the like.

10A to 10D are cross-sectional views illustrating a method of fabricating the semiconductor package 100 according to an embodiment of the present invention.

In Figs. 10A to 10D, the same reference numerals as in Figs. 1A to 1C denote the same members, and a duplicate description thereof will be omitted for the sake of simplicity.

10A, a substrate 110 on which a conductive pad 112 and a solder ball pad 114 are formed is prepared and a semiconductor chip 120 is mounted on an upper surface 110T of the substrate 110 have. The semiconductor chip 120 is mounted on the substrate 110 in a flip chip manner and the semiconductor chip 120 is bonded to the substrate 110 through a bump 150, .

The molding member 140 is formed by injecting an appropriate amount of molding resin onto the top surface 110T of the substrate 110 by means of an injection element (e.g., a nozzle) or the like and then using a pressing element (not shown) Or by applying pressure to the semiconductor chip 110 or the semiconductor chip 120. Here, the processing conditions such as the delay time between the injection of the molding resin and the pressurization, the amount of the molding resin to be injected, and the pressurizing temperature and pressure can be set in consideration of the physical properties such as the viscosity of the molding resin. In some embodiments, the molding resin may include an epoxy molding resin or a polyimide molding resin.

Although the molding member 140 in the present embodiment is formed through the MUF process, the semiconductor chip 120 and the substrate 130 may be formed before the molding member 140, as described above with reference to FIG. 1B, An under fill (not shown) filling the space between the first electrode 110 and the second electrode 110 may be formed as a separate process.

The upper surface 140T of the molding member 140 in this embodiment is positioned at the same level as the upper surface 120T of the semiconductor chip 120 and the molding member 140 is positioned on the side wall 120S And the top surface 120T of the semiconductor chip 120 is exposed. However, the present invention is not limited thereto. For example, as shown in FIG. 5, the molding member 540 may be formed to cover both the upper surface 520T and the side wall 520S of the semiconductor chip 520. FIG.

The process of forming the solder ball 160 disposed on the lower surface 110B of the substrate 110 is performed after the semiconductor chip 120 and the molding member 140 are formed on the upper surface 110T of the substrate 110 Or may be performed before forming the semiconductor chip 120, the molding member 140, and the like.

Referring to FIG. 10B, a recess 122 is formed on the upper surface 120T of the semiconductor chip 120. FIG.

The recess 122 may be formed through various patterning processes using, for example, a doctor blade or a laser.

In some embodiments, in order to allow the heat dissipating member 130 (see FIG. 10E) to be formed in the recess 122 to sufficiently absorb moisture outside the semiconductor package 100, the patterning process may be performed by a recessed portion 122 can be controlled to have a depth of less than 100 um.

Although the recess 122 in the present embodiment is formed only on the upper surface 120T of the semiconductor chip 120, the recess portion 122 is similar to the recess portions 422_1, 422_2, and 542 described above with reference to FIGS. Or may be formed on the upper surface 140T of the molding member 140 as well.

Referring to FIG. 10C, a mask pattern M for exposing the recess 122 may be formed on the upper surface 120T of the semiconductor chip 120 and the upper surface 140T of the molding member 140. FIG.

After the mask pattern M is formed, a printing process or the like may be performed so that the heat dissipating molding resin 132x including the moisture-absorbing particles 134 is filled in the recess 122.

The heat-radiating molding resin 132x may include, for example, an epoxy-based molding resin or a polyimide-based molding resin. The detailed description of the above-described resins has been described with reference to FIGS. 1A to 1C, .

In some embodiments, after the printing process, a curing process for curing the heat-dissipating molding resin 132x formed in the recess 122 may be performed.

10D, the heat radiation molding resin 132x formed on the mask pattern M and the mask pattern M is removed to form the heat radiation member 130 including the heat radiation molding member 132 and the moisture absorption particles 134 . Thus, the semiconductor package 100 including the heat radiation member 130 can be completed.

11 is a block diagram schematically illustrating a memory card including a semiconductor package according to some embodiments of the present invention.

Referring to Fig. 11, in the memory card 10, the controller 11 and the memory 12 may be arranged to exchange electrical signals. For example, when a command is issued from the controller 11, the memory 12 can transmit data. The controller 11 and / or the memory 12 may include a semiconductor package 100, 200, 300, 400, 500, 600, 700, 800, 900 according to any of the embodiments of the present invention. The memory 12 may include a memory array (not shown) or a memory array bank (not shown).

Such a card 10 may include various types of cards such as a memory stick card, a smart media card (SM), a secure digital (SD) card, a mini-secure digital card (mini) a secure digital card (mini SD), or a multi media card (MMC).

12 is a block diagram schematically illustrating an electronic system including a semiconductor package according to some embodiments of the present invention.

12, the electronic system 20 may include a controller 21, an input / output device 22, a memory 23, and an interface 24. The electronic system 20 may be a mobile system or a system that transmits or receives information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card .

The controller 21 can execute the program and serve to control the electronic system 20. The controller 21 may be, for example, a microprocessor, a digital signal processor, a microcontroller, or the like. The input / output device 22 may be used to input or output data of the electronic system 20. [

The electronic system 20 can be connected to an external device, such as a personal computer or network, using the input / output device 22 to exchange data with the external device. The input / output device 22 may be, for example, a keypad, a keyboard, or a display. The memory 23 may store code and / or data for the operation of the controller 21, and / or may store the processed data in the controller 21. The controller 21 and the memory 23 may comprise semiconductor packages 100, 200, 300, 400, 500, 600, 700, 800, 900 according to any of the embodiments of the present invention. The interface 24 may be a data transmission path between the electronic system 20 and another external device. The controller 21, the input / output device 22, the memory 23 and the interface 24 can communicate with each other via the bus 25. [

For example, the electronic system 20 may be a mobile phone, an MP3 player, a navigation device, a portable multimedia player (PMP), a solid state disk (SSD) household appliances.

FIG. 13 is a cross-sectional view schematically showing an SSD device to which a semiconductor package according to some embodiments of the present invention is applied. FIG. 13 shows an example in which the electronic system 20 of FIG. 12 is applied to the SSD device 30.

13, a SSD (Solid State Drive) device 30 of the present embodiment includes a memory package 31, an SSD controller 33, a DRAM (Dynamic Random Access Memory) 35, and a main board 37 .

The memory package 31, the SSD controller 33, the DRAM 35 and the like are connected to the semiconductor package 100, 200, 300, 400, 500, 600, 700, 800, 900 according to any one of the embodiments of the present invention, . ≪ / RTI > However, the present invention is not limited thereto, and SSD devices using semiconductor encapsulants having different modulus and different structures employing external encapsulant may also be included in the technical idea of the present invention.

The memory package 31 may be mounted via an external connecting member or the like on the main board 37 and may be provided with four memory packages PKG1, PKG2, PKG3 and PKG4 as shown in the figure. However, the present invention is not limited to this, and more memory packages 31 can be mounted depending on the channel support state of the SSD controller 33. [ On the other hand, when the memory package 31 is composed of multiple channels, the memory package 31 may be reduced to less than four.

The memory package 31 may be mounted on the main board 37 in a ball grid array (BGA) manner through an external connecting member such as a solder ball. However, it is needless to say that the present invention is not limited thereto and can be mounted by other mounting methods. For example, a pin grid array (PGA) method, a tape carrier package (TCP) method, a chip-on-board (COB) method, a quad flat non-leaded (QFN) method, a quad flat package have.

The SSD controller 33 may have eight channels and eight channels may be connected one-to-one with the corresponding channels of the four memory packages PKG1, PKG2, PKG3, and PKG4, Chips can be controlled.

The SSD controller 33 includes a program that can exchange signals with an external device in a manner conforming to a serial advanced technology attachment (SATA) standard, a parallel advanced technology attachment (PATA) standard, or a small computer system interface . Here, the SATA standard may cover not only SATA-1 but also all SATA-related standards such as SATA-2, SATA-3, and e-SATA (external SATA). PATA standards can encompass all IDE-based standards such as integrated drive electronics (IDE) and enhanced-IDE (E-IDE).

In addition, the SSD controller 33 may be responsible for EEC or FTL processing. The SSD controller 33 may also be mounted on the main board 37 in the form of a package. The SSD controller 33 may be mounted on the main board 37 by a BGA method, a PGA method, a TCP method, a COB method, a QFN method, a QFP method, or the like as the memory package 31.

The DRAM 35 is an auxiliary memory device and can serve as a buffer in exchanging data between the SSD controller 33 and the memory package 31. [ The DRAM 35 may also be mounted on the main board 37 by various methods such as a BGA method, a PGA method, a TCP method, a COB method, a QFN method, and a QFP method.

The main board 37 may be a printed circuit board, a flexible printed circuit board, an organic substrate, a ceramic substrate, a tape substrate, or the like. The main board 37 may include, for example, a core board (not shown) having top and bottom surfaces, and a resin layer (not shown) formed on the top and bottom surfaces, respectively. Further, the resin layers may be formed in a multi-layer structure, and a signal layer, a ground layer, or a power source layer forming a wiring pattern between the multi-layer structures may be interposed. On the other hand, another wiring pattern may be formed on the resin layer. In the drawings, the fine patterns displayed on the main board 37 may mean a wiring pattern or a plurality of passive elements. On the other hand, an interface 39 for communicating with an external device may be formed on one side of the main board 37, for example, on the left side.

14 is a cross-sectional view schematically illustrating an electronic device to which a semiconductor package according to some embodiments of the present invention is applied.

Fig. 14 shows an example in which the electronic system 20 of Fig. 13 is applied to the mobile phone 40. Fig. In addition, the electronic system 20 can be applied to a portable notebook, an MP3 player, a navigation, a solid state disk (SSD), an automobile or household appliances.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

100: semiconductor package
110: substrate
112: conductive pad
114: solder ball pad
120: semiconductor chip
130:
132: heat dissipation molding member
134: hygroscopic particles
140: Molding member
150: Bumper
160: Solder ball

Claims (10)

A substrate having an upper surface and a lower surface,
A semiconductor chip mounted on an upper surface of the substrate and having a first recess portion on an upper surface thereof;
A molding member which exposes an upper surface of the semiconductor chip and is formed to cover the semiconductor chip on an upper surface of the substrate;
And a first heat dissipating member formed in the first recess portion,
Wherein the first heat radiation member includes a moisture absorption particle and a heat dissipation molding member.
The method according to claim 1,
A second recess portion provided on an upper surface of the molding member,
And a second heat dissipating member formed on the second recess portion.
The method according to claim 1,
Wherein the moisture-absorbing particles absorb moisture around the semiconductor package at room temperature.
The method according to claim 1,
Wherein the substrate includes an opening slit formed at a central portion thereof,
Wherein the semiconductor chip is mounted on the substrate in face-down fashion.
The method according to claim 1,
And the upper surface of the heat radiation member is located at a lower level than the upper surface of the semiconductor chip.
A substrate having an upper surface and a lower surface,
A semiconductor chip mounted on an upper surface of the substrate;
A molding member formed to cover an upper surface and a side surface of the semiconductor chip on the upper surface of the substrate and having a recessed portion on an upper surface thereof,
And a heat dissipating member formed in the recess portion,
Wherein the heat dissipating member includes a moisture absorbing particle and a heat dissipating molding member.
A substrate having an upper surface and a lower surface,
A plurality of semiconductor chips stacked on an upper surface of the substrate,
A molding member covering the semiconductor chips on an upper surface of the substrate;
A first recess portion provided on an upper surface of the molding member,
And a first heat dissipating member formed in the first recess portion,
Wherein the first heat radiation member includes a moisture absorption particle and a heat dissipation molding member.
8. The method of claim 7,
Wherein the molding member exposes an upper surface of the semiconductor chip located at the top of the semiconductor chips and is formed to cover the semiconductor chips,
A second recess portion provided on an upper surface of the uppermost semiconductor chip,
And a second heat dissipation member formed on the second recess portion.
8. The method of claim 7,
Wherein the semiconductor chips are stacked in a stepped manner.
8. The method of claim 7,
Wherein the semiconductor chips include a first semiconductor chip including a through silicon via (TSV), and a second semiconductor chip stacked on the first semiconductor chip.

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