KR20120031817A - Circuit board having semiconductor chip and stacked semiconductor package having thereof - Google Patents

Circuit board having semiconductor chip and stacked semiconductor package having thereof Download PDF

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Publication number
KR20120031817A
KR20120031817A KR1020100093430A KR20100093430A KR20120031817A KR 20120031817 A KR20120031817 A KR 20120031817A KR 1020100093430 A KR1020100093430 A KR 1020100093430A KR 20100093430 A KR20100093430 A KR 20100093430A KR 20120031817 A KR20120031817 A KR 20120031817A
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South Korea
Prior art keywords
substrate
semiconductor chip
semiconductor
outside
electrically connected
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Application number
KR1020100093430A
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Korean (ko)
Inventor
김진호
Original Assignee
하나 마이크론(주)
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Priority to KR1020100093430A priority Critical patent/KR20120031817A/en
Publication of KR20120031817A publication Critical patent/KR20120031817A/en

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: A substrate in which a semiconductor chip is included and a stacked semiconductor package including the same are provided to expose one surface of the semiconductor chip to the outside of the substrate, thereby effectively releasing heat generated from the semiconductor chip. CONSTITUTION: A cavity is formed on one surface of a first substrate(110). A plurality of terminals which is electrically connected to the outside is formed on a first semiconductor chip(130). The first semiconductor chip is arranged on the cavity in order to electrically connect the terminals to the first substrate. The other surface of the first semiconductor chip is exposed to the outside of the first substrate. A second substrate(120) is laminated on the other surface of the first substrate.

Description

Circuit board having semiconductor chip and stacked semiconductor package having same

The present invention relates to a semiconductor chip embedded substrate and a stacked semiconductor package including the same, and more particularly, to a semiconductor chip embedded substrate in which a semiconductor chip is embedded in a substrate and a stacked semiconductor package including the same.

As the capacity and speed of electronic devices including personal portable electronic products are increased, and their sizes are also smaller, semiconductor packages are also increasing in capacity, speed, and light weight. Therefore, in order to reduce the size of the package, a ball grid array package (BGA package) using a ball instead of a pin and a chip scale package (CSP) that can be assembled within a range that does not significantly exceed the size of the chip. ) Is proposed.

On the other hand, among these attempts, a semiconductor chip embedded substrate (embedded PCB) has been developed in which semiconductor chips of the same or different type as semiconductor chips mounted inside the substrate on which the semiconductor chips are mounted are embedded.

Using such a semiconductor chip embedded substrate, there is no need to mount a separate semiconductor chip on the substrate, it is possible to greatly reduce the size and thickness of the entire product.

However, when using the semiconductor chip embedded substrate, the semiconductor device may malfunction due to heat generated during the operation of the semiconductor chip embedded in the substrate, which may cause a defect.

In order to solve the above problems, the present invention is to provide a semiconductor chip-embedded substrate in which a semiconductor chip is embedded in a structure in which heat generated during operation of the semiconductor chip can be easily dissipated.

The present invention also provides a stacked semiconductor package in which a separate semiconductor chip is laminated on the semiconductor chip embedded substrate.

In order to solve the problem as described above, the semiconductor chip embedded substrate according to the present invention includes a first substrate having a cavity on one surface; A plurality of terminals electrically connected to an outside of the first semiconductor chip, the first semiconductor chips being provided in the cavity so that the terminals are electrically connected to the first substrate, and having the other surface exposed to the outside of the first substrate; And a second substrate laminated on the other surface of the first substrate. Including but, the wiring electrically connected to the first semiconductor chip may be provided in the form of interlayer wiring between the first substrate and the second substrate.

In addition, a terminal connecting the first substrate to the outside may be formed around the first semiconductor chip.

In addition, the first semiconductor chip may be mounted in the cavity such that the other surface of the first semiconductor chip is positioned on the same horizontal line as the lower surface of the first substrate.

The apparatus may further include a heat sink provided corresponding to the other surface of the first semiconductor chip.

The multilayer semiconductor package may include the semiconductor chip embedded substrate; And a semiconductor package stacked on the semiconductor chip embedded substrate, wherein a second semiconductor chip located in the semiconductor package is electrically connected to the outside through the semiconductor chip embedded substrate.

The semiconductor package may further include a third substrate; A second semiconductor chip provided on the third substrate; And third solder balls provided on the bottom surface of the third substrate to be electrically connected to the third substrate.

In addition, the semiconductor package and the semiconductor chip embedded substrate may be electrically connected by third solder balls.

The apparatus may further include a heat sink provided corresponding to the other surface of the first semiconductor chip.

As described above, in the semiconductor chip embedded substrate according to the present invention, a semiconductor chip is mounted in a cavity formed on the substrate, and at least one surface of the semiconductor chip is exposed to the outside of the substrate. As described above, according to the semiconductor chip embedded substrate of the present invention, since the outside of the semiconductor chip mounted in the cavity of the substrate is not wrapped with an insulating material or the like, the thickness of the entire substrate can be reduced.

And, by exposing one surface of the semiconductor chip to the outside of the substrate, it is possible to effectively release the heat generated from the semiconductor chip. As a result, problems such as malfunction of the semiconductor chip due to the generated heat are solved, thereby ensuring the reliability of the operation of the laminated semiconductor package.

1 is a cross-sectional view of a semiconductor embedded substrate according to an exemplary embodiment of the present invention.
2 is a cross-sectional view of a semiconductor embedded substrate according to another exemplary embodiment of the present disclosure.
3 is a cross-sectional view of a multilayer semiconductor package according to an embodiment of the present invention.
4 is a cross-sectional view of a laminated semiconductor package according to another embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

First, referring to FIGS. 1 and 2, a semiconductor chip embedded substrate 100 according to an exemplary embodiment of the present invention will be described in detail. 1 is a cross-sectional view of a semiconductor chip embedded substrate 100 in accordance with an embodiment of the present invention. 2 is a cross-sectional view of a semiconductor chip embedded substrate 100 in accordance with another embodiment of the present invention.

As shown in FIG. 1, the semiconductor chip embedded substrate 100 may include a first substrate 110 having a cavity 170 on one surface thereof, a first semiconductor chip 130 mounted on the cavity 170, and a first connection thereof. And a second substrate 120 stacked on the first member 110 and the first substrate 110.

In addition, as shown in FIG. 2, the heat dissipator 171 provided on the first substrate 110 of the semiconductor chip embedded substrate 100 shown in FIG. It may be configured to include more.

The first substrate 110 has first wiring electrodes 190 including a plurality of wirings formed on an upper surface and a lower surface thereof, and the first chip 130 is electrically mounted on the lower surface of the first substrate 110. It has a cavity 170 that can be. In addition, first solder balls 150 that are electrically connected to the first wiring electrodes 190 may be provided at portions of the lower surface of the first substrate 110 except for the cavity 700.

The second substrate 120 may be stacked on the upper surface of the first substrate 110 through an adhesive member, and the adhesive member may be a thermosetting material such as an epoxy resin. In addition, second wiring electrodes 180 including a plurality of wires may be formed on one surface of the second substrate 120. The first wiring electrodes 190 of the first substrate 110 and the second wiring electrodes 180 of the second substrate 120 are electrically connected to each other through the through electrodes 160 formed of a conductive material. Can be connected.

In addition, although not specifically illustrated in the drawings, an interlayer wiring is formed between the first substrate 190 and the second substrate 120 to form the first semiconductor chip 130, the first substrate 110, and the like. The second substrates 120 are configured to be electrically connected to each other. (Shown briefly as a vertical wiring structure for convenience)

The first semiconductor chip 130 may include at least one semiconductor device, and the semiconductor device may be a memory chip, a logic chip, an RF chip, or the like. In addition, the first semiconductor chip 130 may be mounted in the cavity 170 formed on the bottom surface of the first substrate 110 by flip chip bonding or the like. In this case, the first semiconductor chip 130 is mounted such that one surface on which the terminals 131 are formed faces the inner surface of the cavity 170 and the other surface is exposed to the outside. Therefore, when the depth of the cavity 170 is deeper than the thickness of the first semiconductor chip 130, the first semiconductor chip 130 does not protrude to the lower surface of the first substrate 110, but when the depth is shallow, The first semiconductor chip 130 may protrude from the lower surface of the first substrate 110.

That is, the other surface of the first semiconductor chip 130 is positioned on the same horizontal line as the bottom surface of the first substrate 110 and is mounted to be exposed to the outside. Therefore, heat generated during the operation of the first semiconductor chip 130 may be effectively released to the outside through the surface exposed to the outside of the first semiconductor chip 130. As a result, malfunction of the first semiconductor chip 130 due to heat may be prevented, thereby ensuring reliability of the operation of the multilayer semiconductor package 300 and increasing heat dissipation efficiency.

In addition, the first semiconductor chip 130 is mounted in the cavity 170 of the first substrate 110, so that the first semiconductor chip 130 is mounted on the first substrate 110. The mounting space area of the first semiconductor chip 130 may be reduced. Therefore, since the size of the third solder balls 240 shown in FIG. 3 can be reduced to a minimum, the overall thickness and size of the multilayer semiconductor package 300 can be reduced.

The first connection member 140 may be composed of first conductive bumps 140, and may be formed between the other surface of the first semiconductor chip 130 and the bottom surface of the cavity 170 of the first substrate 110. It may be composed of the first conductive bumps 140 provided in. The first connection members 140 electrically connect the terminals 131 of the first semiconductor chip 130 and the first wiring electrodes 190 formed on the bottom surface of the cavity 170. Therefore, the first semiconductor chip 130 has a flip chip bonding structure electrically connected to the first substrate 110 through the first conductive bumps 140.

In addition, a resin layer (not shown) is provided between the surface on which the terminals 131 of the first semiconductor chip 130 are formed and the bottom surface of the cavity 170, so that the first conductive bump is prevented from stress due to external force or temperature change. Protect 140. The resin layer (not shown) may be made of any one of an epoxy, a thermoplastic, a thermosetting material, polyamide, polyurethane, and a polymerizable material.

In addition, the heat dissipator 171 may be provided by interviewing a surface on which the terminals 131 exposed to the outside of the first semiconductor chip 130 are not formed and a heat conductive adhesive. The heat sink 171 may be made of materials having high thermal conductivity such as aluminum and copper. In addition, the radiator 171 may have an area equal to or larger than a surface on which the terminals 131 exposed to the outside of the first semiconductor chip 130 are not formed.

That is, the heat sink 171 is made of a metal material such as aluminum and copper having excellent thermal conductivity, and the heat generated during the operation of the first semiconductor chip 130 is external to the first semiconductor chip 130. It may be conducted to the radiator 171 through the exposed surface. Thus, the heat can be quickly released to the outside. In addition, when the heat sink 171 has a larger area than the surface exposed to the outside of the first semiconductor chip 130, the heat generated from the first semiconductor chip 130 can be more effectively discharged through the large area. Can be.

3 is a cross-sectional view of a multilayer semiconductor package according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of a multilayer semiconductor package according to another embodiment of the present invention.

As illustrated in FIG. 3, the multilayer semiconductor package 300 includes a semiconductor chip embedded substrate 100 illustrated in FIG. 1 and a semiconductor package 200 stacked on the semiconductor chip embedded substrate 100. It is configured by. In addition, as illustrated in FIG. 4, the multilayer semiconductor package 300 may further include a heat sink 171 formed corresponding to a surface exposed to the outside of the first semiconductor chip 130.

The semiconductor package 200 may include a third substrate 210, a second semiconductor chip 220, a third connection member 230 electrically connecting the third substrate 210 and the second semiconductor chip 220 to each other. And a third solder ball 240 formed on the bottom surface of the third substrate 210. In addition, the semiconductor package 200 may be stacked to be electrically connected to the semiconductor chip embedded substrate 100. That is, the third solder balls 240 electrically connected to third wiring patterns (not shown) of the third substrate 210 and disposed on the lower surface of the third substrate 210 are the second wiring electrodes 180. ) Is electrically connected to each other.

The third substrate 210 has a third wiring pattern (not shown) including a plurality of wirings. In addition, third solder balls 240 are provided on a lower surface of the third substrate 210 and electrically connected to the third wiring pattern (not shown).

The second semiconductor chip 220 may be formed of at least one semiconductor device electrically mounted on an upper surface of the third substrate 210. The semiconductor device may be a memory chip, a logic chip, or an RF chip. have.

The third connection member 230 may be formed of third conductive bumps 230 electrically connecting the second semiconductor chip 220 and the third substrate 210. In addition, the third conductive bumps 230 are provided between the second semiconductor chip 220 and the third substrate 210 to form a third wiring pattern (not shown). Electrical connection to the field. That is, the second semiconductor chip 220 may have a flip chip bonding structure connected to the third substrate 210 through the third conductive bumps 230.

In addition, the third connection member 230 may be formed of bonding wires (not shown). The bonding wires (not shown) may be made of highly conductive metals such as gold and aluminum, and electrically connect the second semiconductor chip 220 and a third wiring pattern (not shown).

The molding 250 is formed to surround the second semiconductor chip 220 and the third connection member 230 provided on the third substrate 210, and thus, the second semiconductor chip ( 220 and the third connection member 230 is protected. In addition, the molding 250 may be made of epoxy resin or the like.

As described above, the radiator 171 may be provided by interviewing a surface exposed to the outside of the first semiconductor chip 130 with a thermally conductive adhesive. In addition, the heat sink 171 is formed of a metal material such as aluminum, copper, etc. having excellent thermal conductivity, and heat generated during the operation of the first semiconductor chip 130 may be quickly released to the outside. Therefore, when the heat sink 171 has a larger area than the surface exposed to the outside of the first semiconductor chip 130, it is possible to more effectively release the heat generated from the first semiconductor chip 130.

That is, the semiconductor package 200 is mounted on the semiconductor chip embedded substrate 100 in which the one surface of the first semiconductor chip 130 is exposed to the outside in the cavity 170. The electrical connection can be configured in a stacked form. In addition, the first semiconductor chip 130 may further include the heat sink 171 provided corresponding to the surface exposed to the outside.

Accordingly, heat generated during the operation of the first semiconductor chip 130 may be effectively discharged to the outside of the multilayer semiconductor package 300, thereby preventing a malfunction of the first semiconductor chip 130 due to the heat. In this way, it is possible to secure the reliability of the operation of the multilayer semiconductor package 300.

In addition, due to the structure in which the first semiconductor chip 130 is mounted in the cavity 170 of the first substrate 110, the outside of the first semiconductor chip 130 is not wrapped with an insulating material. The thickness of the semiconductor chip embedded substrate 100 may be reduced. As a result, the size of the third solder balls 240 may be reduced to a minimum, and the overall thickness and size of the multilayer semiconductor package 300 may be reduced.

100: semiconductor chip embedded substrate 110: first substrate
120: second substrate 130: first semiconductor chip
131: terminal 140: first connecting member
150: first solder ball 160: through electrode
170: cavity 171: heat sink
180: second wiring electrode 190: first wiring electrode
200: semiconductor package 210: third substrate
220: second semiconductor chip 230: third connection member
240: third solder ball 250: molding
300: laminated semiconductor package

Claims (8)

A first substrate having a cavity on one surface;
A first semiconductor chip having a plurality of terminals electrically connected to an outside of the first substrate, the first semiconductor chip being provided in the cavity such that the terminals are electrically connected to the first substrate, and having the other surface exposed to the outside of the first substrate; And
A second substrate stacked on the other surface of the first substrate;
Including,
And a wire electrically connected to the first semiconductor chip in an interlayer wiring form between the first substrate and the second substrate.
The method of claim 1,
And a terminal connecting the first substrate to the outside around the first semiconductor chip.
The method of claim 1,
And the first semiconductor chip is mounted in the cavity such that the other surface of the first semiconductor chip is positioned on the same horizontal line as the lower surface of the first substrate.
The method of claim 1,
The semiconductor chip embedded substrate further comprises a heat sink provided corresponding to the other surface of the first semiconductor chip.
The semiconductor chip embedded substrate of claim 1; And
A semiconductor package stacked on the semiconductor chip embedded substrate;
Including,
The second semiconductor chip located in the semiconductor package is electrically connected to the outside through the semiconductor chip embedded substrate.
6. The method of claim 5,
The semiconductor package
Third substrate;
A second semiconductor chip provided on the third substrate; And
Laminated semiconductor package comprising a third solder ball on the lower surface of the third substrate to be electrically connected to the third substrate.
6. The method of claim 5,
And the semiconductor package and the semiconductor chip embedded substrate are electrically connected to each other by third solder balls.
6. The method of claim 5,
The semiconductor package of claim 1, further comprising a heat sink provided corresponding to the other surface of the first semiconductor chip.







KR1020100093430A 2010-09-27 2010-09-27 Circuit board having semiconductor chip and stacked semiconductor package having thereof KR20120031817A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252031B2 (en) 2013-09-23 2016-02-02 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
WO2022225314A1 (en) * 2021-04-21 2022-10-27 엘지이노텍 주식회사 Sip module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252031B2 (en) 2013-09-23 2016-02-02 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
WO2022225314A1 (en) * 2021-04-21 2022-10-27 엘지이노텍 주식회사 Sip module

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