CN114564771A - Chip package pin distribution method and device, electronic equipment and storage medium - Google Patents
Chip package pin distribution method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a chip packaging pin distribution method, a chip packaging pin distribution device, electronic equipment and a storage medium, wherein the method comprises the following steps: displaying a control interface; acquiring a setting instruction aiming at a control interface; creating and displaying a blank chip pin diagram based on a setting instruction; acquiring a processing instruction aiming at a control interface; loading a file based on the processing instruction, and determining the attributes of each bare chip pin and each chip pin according to the file; displaying the names of the bare chip pins and the chip pins in a menu mode; acquiring an operation instruction aiming at each chip pin position in a chip pin diagram; updating a chip pin diagram based on the operation instruction, and recording a corresponding distribution result; determining a connection relation between each bare chip pin and each chip pin based on the corresponding distribution result; and outputting the determined connection relation according to a preset format. The invention can manage the chip pin connection relation in a more intuitive and simple mode, and saves labor cost.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a chip package pin distribution method, a chip package pin distribution device, electronic equipment and a storage medium.
Background
Packaging (Package) is a process of assembling an integrated circuit bare chip (Die) into a chip, the integrated circuit bare chip needs to be placed on a substrate playing a bearing role, and then a bare chip pin (pad) is led out to the outside of the Package to obtain a chip pin (pin) for connection.
At present, in order to realize the pin allocation of chip packages, a chip designer needs to provide the package designer with a connection relationship between a bare-chip pin and a chip pin, and sometimes needs to provide a chip pin map (pin map) for the package designer to refer to. Because the number of chip pins is often numerous, when chip designers perform chip packaging pin allocation, the work is tedious and repeated, errors are easily introduced, the time from a product to the market is possibly delayed, and the development cost is increased.
Disclosure of Invention
Based on the problem that chip packaging pin allocation work is complicated and error-prone, the invention provides a chip packaging pin allocation method, a chip packaging pin allocation device, electronic equipment and a storage medium, which can manage the connection relation of chip pins in a more intuitive and simple manner and save labor cost.
In a first aspect, an embodiment of the present invention provides a method for allocating pins of a chip package, including:
displaying a control interface;
acquiring a setting instruction aiming at the control interface; the setting instruction comprises an instruction for selecting the packaging type of the chip and an instruction for defining the row number and the column number of the chip pin diagram to be created;
creating and displaying a blank chip pin diagram based on the setting instruction; the chip pin diagram comprises a plurality of chip pin positions to be allocated, each chip pin position is provided with a corresponding number, a bare chip pin and a chip pin can be allocated, corresponding allocation results are recorded, and the bare chip pin or the chip pin which is not allocated to each chip pin position in the blank chip pin diagram is not allocated;
acquiring a processing instruction aiming at the control interface; the processing instruction comprises an instruction for loading a file;
loading a file based on the processing instruction, and determining the attributes of each bare chip pin and each chip pin according to the file; the attributes of the bare chip pin and the chip pin comprise names;
displaying the names of the bare chip pins and the chip pins in a menu mode;
acquiring an operation instruction for each chip pin position in the chip pin diagram; wherein the operating instructions include instructions to allocate die pins/chip pins to chip pin bits;
updating the chip pin diagram based on the operation instruction, and recording a corresponding distribution result;
determining a connection relation between each bare chip pin and each chip pin based on the corresponding distribution result;
and outputting the determined connection relation according to a preset format.
Optionally, the chip package pin allocating method further includes:
after determining the attributes of each bare chip pin and each chip pin according to the file, judging whether the attributes of the bare chip pins or the chip pins include a connection relation; and if yes, updating the chip pin diagram according to the connection relation.
Optionally, the displaying the names of the die pins and the chip pins in a menu form includes:
and respectively displaying the names of all bare chip pins and the names of all chip pins in a column menu.
Optionally, the displaying the names of the die pins and the chip pins in the form of a menu further includes:
respectively displaying the names of bare chip pins in different current connection states and the names of chip pins by using menus in columns, and updating the names displayed in the menus based on the operation instructions after the operation instructions are obtained; wherein the connection state comprises: unconnected state, single connected state, and multiple connected state.
Optionally, the chip pin map displays the current allocation result type of each chip pin position in different colors; wherein the allocation result type includes: no assigned die pins and chip pins, only one assigned die pin, only one assigned chip pin, only a plurality of assigned die pins, only a plurality of assigned chip pins, and assigned die pins and chip pins.
Optionally, the operating instructions further include: the instructions for the chip pin bits are de-assigned die pins and/or chip pins.
Optionally, the chip package pin allocating method further includes:
after the blank chip pin diagram is created and displayed, acquiring a viewing instruction for one chip pin position in the chip pin diagram;
and displaying the allocation result of the chip pin position in a floating window mode based on the viewing instruction.
In a second aspect, an embodiment of the present invention further provides a chip package pin allocating apparatus, including:
the display module is used for displaying a control interface;
the setting module is used for acquiring a setting instruction aiming at the control interface; the setting instruction comprises an instruction for selecting a chip packaging type and an instruction for defining the number of rows and columns of a chip pin diagram to be created;
the creating module is used for creating and displaying a blank chip pin diagram based on the setting instruction; the chip pin diagram comprises a plurality of chip pin positions to be distributed, each chip pin position is provided with a corresponding number, bare chip pins and chip pins can be distributed, corresponding distribution results are recorded, and the bare chip pins or the chip pins which are not distributed in each chip pin position in the blank chip pin diagram are not distributed;
the processing module is used for acquiring a processing instruction aiming at the control interface; the processing instruction comprises an instruction for loading a file;
the name extraction module is used for loading a file based on the processing instruction and determining the attributes of each bare chip pin and each chip pin according to the file; the attributes of the bare chip pin and the chip pin comprise names;
the list display module is used for displaying the names of the bare chip pins and the chip pins in a menu mode;
the operation module is used for acquiring operation instructions aiming at the chip pin positions in the chip pin diagram; wherein the operating instructions include instructions to allocate die pins/chip pins to chip pin bits;
the updating module is used for updating the chip pin map based on the operation instruction and recording a corresponding distribution result;
the connection module is used for determining the connection relation between each bare chip pin and each chip pin based on the corresponding distribution result;
and the output module is used for outputting the determined connection relation according to a preset format.
In a third aspect, an embodiment of the present invention further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program, and the processor executes the computer program to implement the method according to any embodiment of this specification.
In a fourth aspect, the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed in a computer, the computer program causes the computer to execute the method described in any embodiment of the present specification.
The embodiment of the invention provides a chip package pin distribution method, a chip package pin distribution device, electronic equipment and a storage medium.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a method for allocating pins of a chip package according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a control interface provided by an embodiment of the present invention;
FIG. 3 is a diagram of a hardware architecture of an electronic device according to an embodiment of the present invention;
fig. 4 is a structural diagram of a pin assignment device for a chip package according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more complete, the technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, it is obvious that the described embodiments are some, but not all embodiments of the present invention, and based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
As described above, in practical engineering, in order to implement the pin assignment of a chip package, a chip designer needs to provide a document (e.g., Excel) to describe a connection relationship (i.e., pad-pin mapping relationship) between a die pin and a chip pin for the package designer, and sometimes needs to provide a chip pin diagram to provide a reference for the package designer. Because the number of chip pins is large, when describing the connection relationship between the bare chip pins and the chip pins and drawing a chip pin diagram, a chip designer has complex and repeated work, the distribution state in the chip pin diagram is not intuitive, errors are easily introduced, the time of products to the market is possibly delayed, and the development cost is increased. In view of this, the invention creates an operable chip pin diagram by using the control interface, and records the corresponding allocation result by each chip pin bit in the chip pin diagram, thereby realizing more intuitive and simple management of the connection relationship between the bare chip pin and the chip pin.
Specific implementations of the above concepts are described below.
Referring to fig. 1 and fig. 2, an embodiment of the invention provides a method for allocating pins of a chip package, the method including:
The displayed control interface preferably displays the literal prompt information to facilitate the user to operate according to the prompt information, and the control interface inputs various instructions, for example, the prompt information may be displayed in a form of characters directly on the control interface, the prompt information may be displayed in a form of function keys with a description of the characters, and the prompt information may be displayed in a form of a frame with the characters, as shown in fig. 2, it should be noted that the literal prompt information displayed on the control interface in fig. 2 and the arrangement form of the windows and the function keys are only exemplary descriptions, and do not represent that the control interface can only be displayed in the form shown in fig. 2.
102, acquiring a setting instruction for a control interface; the setting instruction comprises an instruction for selecting the chip packaging type and an instruction for defining the row number and the column number of the chip pin diagram to be created.
In step 102, by selecting the chip package type, the arrangement form of the chip pin diagram to be created can be determined, the common package type includes BGA/LGA/QFN, etc., and the chip pins of different package types are arranged according to the specific physical position; the size of the chip pin diagram to be created can be determined by defining the number of rows and the number of columns of the chip pin diagram, and independent serial numbers can be allocated to each chip pin by combining corresponding material position arrangement.
104, creating and displaying a blank chip pin diagram based on the acquired setting instruction;
the chip pin diagram comprises a plurality of chip pin positions to be distributed, each chip pin position is provided with a corresponding number (namely pin loc), and the position of each chip pin position and the corresponding number are determined according to a setting instruction;
each chip pin position can be allocated with a bare chip pin and a chip pin, and a corresponding allocation result is recorded, wherein the allocation result comprises the names of the bare chip pin and the chip pin which are currently allocated to the chip pin position;
in the blank chip pin diagram, there is no bare chip pin or chip pin allocated to each chip pin position, that is, for the blank chip pin diagram, the allocation result of each chip pin position is blank.
The files loaded at this step 106 may include: the method comprises the steps of recording a file of pin attributes of each die to be allocated and recording a file of pin attributes of each chip to be allocated. Of course, the attributes of each die pin to be allocated may be recorded in the same file as the attributes of each chip pin to be allocated.
In step 108, an array (i.e., pin array) composed of names of chip pins is obtained, which is mainly a description of names of functional pins that the chip must be packaged, and these names are also generally printed on the system-level circuit board.
Optionally, the attributes of the die pin may further include: the position coordinates of the die pins on the die, the sizes of the die pins (i.e., pad opening), and the corresponding connection relationships (i.e., which chip pin/s the die pins are connected to). If the corresponding connection relation in the loaded attribute of the bare chip pin is not null, the fact means that the connection relation exists between the bare chip pin and the chip pin.
Optionally, the attributes of the chip pin may further include: the number of the chip pins (i.e., pin loc), and the corresponding connection relationship (i.e., which die pin/pins are connected to the chip pins). If the number of the chip pin in the loaded attribute of the chip pin is not null, it means that a mapping relationship exists between the name of the chip pin and the number of the chip pin.
And step 114, updating the chip pin map based on the operation instruction, and recording the updated corresponding distribution result.
In step 114, a corresponding die pin is assigned to the chip pin bit based on the instruction for assigning a die pin to the chip pin bit, the name of the corresponding die pin is recorded in the assignment result of the chip pin bit, a corresponding chip pin is assigned to the chip pin bit based on the instruction for assigning a chip pin to the chip pin bit, and the name of the corresponding chip pin is recorded in the assignment result of the chip pin bit.
And step 116, determining the connection relation between each bare chip pin and each chip pin based on the corresponding distribution result so as to realize the distribution of the chip package pins.
The assignment result of each chip pin position corresponds to the connection relationship between a group of bare chip pins and the chip pins, that is, for the same chip pin position, all bare chip pins recorded with names in the assignment result are all connected with all chip pins recorded with names in the assignment result. The connection relationship includes a die-chip pin one-to-one connection relationship (i.e., one die pin is connected to one chip pin), a die-chip pin one-to-many connection relationship (i.e., one die pin is connected to a plurality of chip pins) or a many-to-one connection relationship (i.e., a plurality of die pins are connected to one chip pin), and a die-chip pin many-to-many connection relationship (i.e., a plurality of die pins are connected to a plurality of chip pins).
And step 118, outputting the connection relation between the bare chip pins and the chip pins according to a preset format.
In this step 118, a document describing the connection relationship between the die pins and the chip pins can be obtained by outputting the determined connection relationship according to a preset format, for example, an attribute document of each die pin and the chip pin can be updated and output, and the corresponding connection relationship is recorded in the attribute. Meanwhile, a drawn chip pin diagram can be output according to needs and can be referred by a packaging designer.
In the embodiment of the invention, the operable chip pin diagram is created by using the control interface, and a user (such as a chip designer) can directly operate each chip pin position in the chip pin diagram and allocate the corresponding chip pin and bare chip pin to the chip pin position so as to establish the connection relation between each bare chip pin and each chip pin.
Optionally, the chip package pin assignment method further includes:
in step 108, after determining the attributes of each bare chip pin and each chip pin according to the file, judging whether the attributes of the bare chip pins or the chip pins include corresponding connection relations; if yes, updating the chip pin diagram according to the existing connection relation in the attribute; otherwise, the next step is continuously executed.
If there is a connection relationship in the attributes of the die pins or chip pins, it may be that chip package pin assignment has been performed previously, or that there is a special requirement for some pin assignments. In the above embodiment, by directly loading the existing connection relationship and updating the chip pin map, the user can further modify the existing connection relationship, thereby saving the work of allocating the pin positions of each chip one by one.
Optionally, step 110 comprises:
and respectively displaying the names of all the bare chip pins and the names of all the chip pins in a column menu.
The chip pins are often numerous and difficult to comb and manage, and the bare chip pins and the chip pins are respectively displayed through the column-divided menus, so that a user can check the bare chip pins and the chip pins according to needs, and omission or errors in the distribution process are avoided.
Further, step 110 further comprises:
respectively displaying the names of bare chip pins in different current connection states and the names of chip pins by using the menus in columns, and updating the names displayed in the menus based on the operation instructions after the operation instructions are obtained; wherein the connection state includes: unconnected state, single connected state, and multiple connected state.
A die pin in an unconnected state, i.e., the die pin is not connected to any chip pin. A die pin in a single connection state, i.e., the die pin is connected to a chip pin. The die pins in the multi-connection state, that is, the die pins are connected to the chip pins. Similarly, a chip pin in an unconnected state, i.e., the chip pin is not connected to any die pin. A chip pin in a single connection state, i.e., the chip pin is connected to one die pin. The chip pins in the multi-connection state, that is, the chip pins are connected to the plurality of bare chip pins.
When the number of pins to be allocated exceeds a certain limit, even if a list composed of names of all bare chip pins and names of all chip pins is used as a prompt, a user is difficult to avoid errors, such as the possibility of missing the unconnected individual pins or mistakenly connecting the individual pins repeatedly, in the above embodiment, the bare chip pins in the unconnected state, the single-connection state and the multi-connection state and the chip pins in the unconnected state, the single-connection state and the multi-connection state respectively display corresponding name lists in different menus, and the name lists are updated in time in response to an operation instruction, so that the current connection states of the bare chip pins and the chip pins can be visually displayed to the user, particularly after the existing connection relation is directly loaded, the names of the pins in different current connection states can be sorted out by the lists, and the user can conveniently check and modify the connection relation further, avoiding erroneous connections or missing individual pins.
Further, step 118 may further include: and respectively outputting the names of the bare chip pins and the names of the chip pins in different connection states.
In the above embodiment, by respectively outputting the names of the bare chip pins and the names of the chip pins in different connection states, more reference information can be provided for chip package design, and package designers can conveniently perform work such as proofreading.
Optionally, in the method, the chip pin diagram displays the current allocation result type of each chip pin bit in different colors; wherein, the distribution result type comprises: the chip comprises a plurality of chip pins, a plurality of allocated die pins, a plurality of allocated chip pins, a plurality of allocated die pins, a plurality of chip pins, and a plurality of chip pins, wherein the chip pins are allocated only. Further, in the assignment result type, the type of the die pins and the chip pins assigned may be further subdivided according to the number of the assigned chip pins and die pins.
When the number of the chip pins is large, in the distribution process, a user may forget the distributed chip pin positions or repeatedly distribute the chip pins, by adopting the embodiment, the whole information can be displayed, the user can intuitively know whether the distributed bare chip pins and the distributed chip pins exist in the current chip pin positions on a chip pin diagram, specifically, a plurality of bare chip pins and the distributed chip pins are distributed, whether the connection relation between the bare chip pins and the chip pins can be completed, and the like, so that omission or repeated connection is effectively avoided.
Optionally, the operation instruction in step 110 further includes: the instructions for the assigned die pins and/or chip pins are cancelled for the chip pin bits. Accordingly, in step 114, updating the chip pin map based on the operation instruction includes: canceling the allocated bare chip pin recorded by the corresponding chip pin bit based on the instruction of canceling the allocated bare chip pin for the chip pin bit, canceling the allocated chip pin recorded by the corresponding chip pin bit based on the instruction of canceling the allocated chip pin for the chip pin bit, and canceling the allocated bare chip pin and the chip pin recorded by the corresponding chip pin bit based on the instruction of canceling the allocated bare chip pin and the chip pin for the chip pin bit. With the above-described embodiments, a user can re-release an allocated chip pin location, allocate a new die pin and/or chip pin to it, or empty it.
Optionally, the method further comprises:
after a blank chip pin diagram is created and displayed in step 104, a viewing instruction for one chip pin position in the chip pin diagram is acquired;
and displaying the allocation result of the chip pin position in a floating window mode based on the viewing instruction. Wherein the floating window may be positioned near a chip pin site.
With the above embodiment, a user can quickly check the current assignment result of the chip pin position, that is, the name of the assigned bare chip pin and/or chip pin, through a check instruction (e.g., left click), so that the user can find and check the connection relationship in time.
In other embodiments, the chip pin map further directly displays the current assignment result on each chip pin position, so that a user can check each chip pin position at any time.
As shown in fig. 3 and 4, an embodiment of the invention provides a pin assignment device for a chip package. The apparatus embodiments may be implemented by software, or by hardware, or by a combination of hardware and software.
From a hardware aspect, as shown in fig. 3, for a hardware architecture diagram of an electronic device in which a chip package pin allocating apparatus according to an embodiment of the present invention is located, in addition to the processor, the memory, the network interface, and the nonvolatile memory shown in fig. 3, the electronic device in which the apparatus is located may also include other hardware, such as a forwarding chip responsible for processing a message.
Taking a software implementation as an example, as shown in fig. 4, as a logical device, a CPU of the electronic device reads a corresponding computer program in the non-volatile memory into the memory for running. The device for allocating pins in a chip package provided by the present embodiment includes a display module 400, a setting module 402, a creating module 404, a processing module 406, a name extracting module 408, a list displaying module 410, an operating module 412, an updating module 414, a connecting module 416, and an output module 418, specifically, where:
the display module 400 is used for displaying a control interface;
the setting module 402 is configured to obtain a setting instruction for the control interface; the setting instruction comprises an instruction for selecting the chip packaging type and an instruction for defining the row number and the column number of a chip pin diagram to be created;
the creating module 404 is configured to create and display a blank chip pin diagram based on the setting instruction; the chip pin diagram comprises a plurality of chip pin positions to be allocated, each chip pin position is provided with a corresponding number, bare chip pins and chip pins can be allocated, corresponding allocation results are recorded, and the bare chip pins or the chip pins are not allocated to the chip pin positions in the blank chip pin diagram;
the processing module 406 is configured to obtain a processing instruction for the control interface; the processing instruction comprises an instruction for loading a file;
the name extraction module 408 is configured to load a file based on the processing instruction, and determine attributes of each die pin and each chip pin according to the file; the attributes of the bare chip pin and the chip pin comprise names;
the list display module 410 is used for displaying the names of the bare chip pins and the chip pins in a menu form;
the operation module 412 is configured to obtain an operation instruction for each chip pin position in the chip pin diagram; wherein the operation instructions comprise instructions to allocate die pins/chip pins to chip pin bits;
the updating module 414 is configured to update the chip pin map based on the operation instruction, and record a corresponding allocation result;
the connection module 416 is configured to determine a connection relationship between each die pin and each chip pin based on the corresponding allocation result;
the output module 418 is configured to output the determined connection relationship according to a preset format.
In an embodiment of the present invention, the display module 400 may be configured to perform step 100 in the foregoing method embodiment, the setting module 402 may be configured to perform step 102 in the foregoing method embodiment, the creating module 404 may be configured to perform step 104 in the foregoing method embodiment, the processing module 406 may be configured to perform step 106 in the foregoing method embodiment, the name extracting module 408 may be configured to perform step 108 in the foregoing method embodiment, the list displaying module 410 may be configured to perform step 110 in the foregoing method embodiment, the operating module 412 may be configured to perform step 112 in the foregoing method embodiment, the updating module 414 may be configured to perform step 114 in the foregoing method embodiment, the connecting module 416 may be configured to perform step 116 in the foregoing method embodiment, and the output module 418 may be configured to perform step 118 in the foregoing method embodiment.
Optionally, the name extraction module 408 is configured to determine whether the attributes of the die pins or the chip pins include a connection relationship after determining the attributes of the die pins and the chip pins according to the file; and if so, updating the chip pin diagram according to the connection relation.
Optionally, the list display module 410 displays names of the die pins and the chip pins in a menu form, including performing:
and respectively displaying the names of all the bare chip pins and the names of all the chip pins in a column menu.
Optionally, the list displaying module 410 displays names of the die pins and the chip pins in a menu form, and further performs:
respectively displaying the names of bare chip pins in different current connection states and the names of chip pins by using the menus in columns, and updating the names displayed in the menus based on the operation instructions after the operation instructions are obtained; wherein the connection state includes: unconnected state, single connected state, and multiple connected state.
Optionally, in the apparatus, the chip pin diagram displays the current assignment result type of each chip pin bit in different colors; wherein, the distribution result type comprises: no assigned die pins and chip pins, only one assigned die pin, only one assigned chip pin, only a plurality of assigned die pins, only a plurality of assigned chip pins, and assigned die pins and chip pins.
Optionally, the operation instructions further include: the instructions for the assigned die pins and/or chip pins are cancelled for the chip pin bits.
Optionally, the apparatus further includes a viewing module, where the viewing module is configured to obtain a viewing instruction for a chip pin position in the chip pin map after creating and displaying the blank chip pin map; and displaying the allocation result of the chip pin position in a floating window mode based on the viewing instruction.
It is to be understood that the illustrated structure of the embodiments of the invention is not to be construed as a specific limitation to a pin assignment apparatus for a chip package. In other embodiments of the present invention, a chip package pin assignment arrangement may include more or fewer components than shown, or combine certain components, or split certain components, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
Because the content of information interaction, execution process, and the like among the modules in the device is based on the same concept as the method embodiment of the present invention, specific content can be referred to the description in the method embodiment of the present invention, and is not described herein again.
The embodiment of the invention also provides electronic equipment which comprises a memory and a processor, wherein the memory is stored with a computer program, and when the processor executes the computer program, the chip packaging pin distribution method in any embodiment of the invention is realized.
An embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program causes the processor to execute a chip package pin allocation method according to any embodiment of the present invention.
Specifically, a system or an apparatus equipped with a storage medium on which software program codes that realize the functions of any of the above-described embodiments are stored may be provided, and a computer (or a CPU or MPU) of the system or the apparatus is caused to read out and execute the program codes stored in the storage medium.
In this case, the program code itself read from the storage medium can realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.
Examples of the storage medium for supplying the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (e.g., CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD + RW), a magnetic tape, a nonvolatile memory card, and a ROM. Alternatively, the program code may be downloaded from a server computer via a communications network.
Further, it should be clear that the functions of any one of the above-described embodiments may be implemented not only by executing the program code read out by the computer, but also by causing an operating system or the like operating on the computer to perform a part or all of the actual operations based on instructions of the program code.
Further, it is to be understood that the program code read out from the storage medium is written to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion module connected to the computer, and then a CPU or the like mounted on the expansion board or the expansion module is caused to perform part or all of the actual operations based on instructions of the program code, thereby realizing the functions of any of the embodiments described above.
In summary, the present invention provides a method and an apparatus for allocating pins of a chip package, an electronic device and a storage medium, and the present invention provides an intuitive way to manage the connection relationship between the pins of the die and the pins of the chip by using a graphical interface, and simultaneously supports the saving and loading of the engineering, thereby providing convenience for the user. The invention automates a large amount of manual work, reduces the repeated workload, reduces the probability of manually introducing errors, and can effectively save the chip development cost.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other similar elements in a process, method, article, or apparatus that comprises the element.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A chip package pin allocation method is characterized by comprising the following steps:
displaying a control interface;
acquiring a setting instruction aiming at the control interface; the setting instruction comprises an instruction for selecting a chip packaging type and an instruction for defining the number of rows and columns of a chip pin diagram to be created;
creating and displaying a blank chip pin diagram based on the setting instruction; the chip pin diagram comprises a plurality of chip pin positions to be allocated, each chip pin position is provided with a corresponding number, a bare chip pin and a chip pin can be allocated, corresponding allocation results are recorded, and the bare chip pin or the chip pin which is not allocated to each chip pin position in the blank chip pin diagram is not allocated;
acquiring a processing instruction aiming at the control interface; the processing instruction comprises an instruction for loading a file;
loading a file based on the processing instruction, and determining the attributes of each bare chip pin and each chip pin according to the file; the attributes of the bare chip pin and the chip pin comprise names;
displaying the names of the pins of the bare chips and the pins of the chips in a menu form;
acquiring an operation instruction for each chip pin position in the chip pin diagram; wherein the operating instructions include instructions to allocate die pins/chip pins to chip pin bits;
updating the chip pin diagram based on the operation instruction, and recording a corresponding distribution result;
determining a connection relation between each bare chip pin and each chip pin based on the corresponding distribution result;
and outputting the determined connection relation according to a preset format.
2. The method of claim 1, further comprising:
after determining the attributes of each bare chip pin and each chip pin according to the file, judging whether the attributes of the bare chip pins or the chip pins include a connection relation; and if so, updating the chip pin diagram according to the connection relation.
3. The method of claim 1,
the displaying of the names of the bare chip pins and the chip pins in a menu form includes:
and respectively displaying the names of all the bare chip pins and the names of all the chip pins in a column menu.
4. The method of claim 3,
the displaying of the names of the die pins and the chip pins in a menu form further includes:
respectively displaying the names of bare chip pins in different current connection states and the names of chip pins by using menus in columns, and updating the names displayed in the menus based on the operation instructions after the operation instructions are obtained; wherein the connection state comprises: unconnected state, single connected state, and multiple connected state.
5. The method of claim 1,
the chip pin diagram displays the current distribution result type of each chip pin position in different colors; wherein the allocation result type includes: no assigned die pins and chip pins, only one assigned die pin, only one assigned chip pin, only a plurality of assigned die pins, only a plurality of assigned chip pins, and assigned die pins and chip pins.
6. The method of claim 1,
the operation instructions further include: the instructions for the assigned die pins and/or chip pins are cancelled for the chip pin bits.
7. The method of claim 1, further comprising:
after the blank chip pin diagram is created and displayed, a viewing instruction for one chip pin position in the chip pin diagram is obtained;
and displaying the allocation result of the chip pin position in a floating window mode based on the viewing instruction.
8. A chip package pin assignment arrangement, comprising:
the display module is used for displaying a control interface;
the setting module is used for acquiring a setting instruction aiming at the control interface; the setting instruction comprises an instruction for selecting the packaging type of the chip and an instruction for defining the row number and the column number of the chip pin diagram to be created;
the creating module is used for creating and displaying a blank chip pin diagram based on the setting instruction; the chip pin diagram comprises a plurality of chip pin positions to be allocated, each chip pin position is provided with a corresponding number, a bare chip pin and a chip pin can be allocated, corresponding allocation results are recorded, and the bare chip pin or the chip pin which is not allocated to each chip pin position in the blank chip pin diagram is not allocated;
the processing module is used for acquiring a processing instruction aiming at the control interface; the processing instruction comprises an instruction for loading a file;
the name extraction module is used for loading a file based on the processing instruction and determining the attributes of each bare chip pin and each chip pin according to the file; the attributes of the bare chip pin and the chip pin comprise names;
the list display module is used for displaying the names of the bare chip pins and the chip pins in a menu mode;
the operation module is used for acquiring operation instructions aiming at the chip pin positions in the chip pin diagram; wherein the operating instructions include instructions to allocate die pins/chip pins to chip pin bits;
the updating module is used for updating the chip pin map based on the operation instruction and recording a corresponding distribution result;
the connection module is used for determining the connection relation between each bare chip pin and each chip pin based on the corresponding distribution result;
and the output module is used for outputting the determined connection relation according to a preset format.
9. An electronic device comprising a memory and a processor, the memory having stored therein a computer program, characterized in that the processor, when executing the computer program, implements the method according to any of claims 1-7.
10. A storage medium having stored thereon a computer program, characterized in that the computer program, when executed in a computer, causes the computer to perform the method of any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210262697.4A CN114564771A (en) | 2022-03-17 | 2022-03-17 | Chip package pin distribution method and device, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210262697.4A CN114564771A (en) | 2022-03-17 | 2022-03-17 | Chip package pin distribution method and device, electronic equipment and storage medium |
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| CN114564771A true CN114564771A (en) | 2022-05-31 |
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| CN202210262697.4A Pending CN114564771A (en) | 2022-03-17 | 2022-03-17 | Chip package pin distribution method and device, electronic equipment and storage medium |
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| Country | Link |
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| CN (1) | CN114564771A (en) |
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