CN115763342A - Chip position adjusting method and device, terminal and storage medium - Google Patents
Chip position adjusting method and device, terminal and storage medium Download PDFInfo
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- CN115763342A CN115763342A CN202211401335.5A CN202211401335A CN115763342A CN 115763342 A CN115763342 A CN 115763342A CN 202211401335 A CN202211401335 A CN 202211401335A CN 115763342 A CN115763342 A CN 115763342A
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Abstract
The application discloses a chip position adjusting method, a chip position adjusting device, a terminal and a storage medium, wherein the method comprises the following steps: responding to the target chip arranged in the canvas, and detecting the initial placing position of the target chip in the canvas; and determining a target placing position corresponding to the target chip based on the initial placing position, and adjusting the target chip to the target placing position. After the target chip is arranged in the canvas of the EDA tool, the EDA tool can automatically detect the placing position of the target chip in the canvas, namely the initial placing position, and judge whether the initial placing position is the target placing position. When the initial placing position is not the target placing position, the target placing position can be determined based on the initial placing position, and the target chip is automatically adjusted to the target placing position, so that the automatic adjustment of the position of the target chip is realized, the manual operation of designers is avoided, and the working efficiency is improved.
Description
Technical Field
The present application relates to the field of EDA technologies, and in particular, to a method and an apparatus for adjusting a chip position, a terminal, and a storage medium.
Background
The chipset technology is to decompose Soc (System on Chip) into a plurality of smaller chiplets, wherein the chiplets can have different functions and processes, and then package the modularized chiplets together by using a novel packaging technology to realize interconnection of the chiplets, i.e. to form a heterogeneous integrated Chip.
In order to realize wide application of the chipset technology, the chipset technology is applied to EDA (Electronic design automation). In an EDA based on the chip technology, there is usually a Chiplet placing step, i.e. placing the chiplets into a set canvas. In an EDA, the position where a chiplet is placed in the canvas can be mapped to the position where the chiplet is placed on the active silicon substrate in an actual soc chip. A programmable routing network is typically provided in the active silicon substrate for interconnecting the chiplets disposed on the active silicon substrate. In practical applications, a surface of the active silicon substrate in contact with the chiplet usually has metal bumps bump, and these metal bumps are connected to the programmable routing network in the active silicon substrate, and the programmable routing network is controlled to implement interconnection between any metal bumps. The bottom of the chiplet can also be provided with metal bumps bump, which enable the chiplets to be interconnected through a programmable routing network in the active silicon substrate by contacting the metal bumps of the chiplet with the metal bumps of the active silicon substrate. At this time, in order to ensure the signal transmission effect between the chiplet and the active silicon substrate, it is often necessary that the metal bumps of the chiplet and the metal bumps of the active silicon substrate can be aligned accurately or have as large a contact area as possible or have as many points of contact as possible. In order to ensure that the metal bumps of the chiplet and the active silicon substrate are aligned accurately or have a contact area as large as possible or have as many contact points as possible, a high requirement is required for the placement position of the chiplet in the canvas in the EDA tool at the chip design stage.
Currently, the accuracy of the placement of the chiplets in the canvas is achieved only by manual work.
Disclosure of Invention
The application mainly aims to provide a chip position adjusting method, a chip position adjusting device, a terminal and a storage medium, so as to solve the problem that in the related art, the accuracy of the placement position of a chiplet in a canvas is realized only by manpower.
In order to achieve the above object, in a first aspect, the present application provides a method for adjusting a chip position, including:
responding to the target chip arranged in the canvas, and detecting the initial placing position of the target chip in the canvas, wherein the canvas comprises a plurality of grid units arranged in an array, each grid unit in the grid units is provided with a contact point, and the contact point is used for representing the contact point of the active silicon substrate;
and determining a target placing position corresponding to the target chip based on the initial placing position, and adjusting the target chip to the target placing position.
In one possible implementation manner, determining a target placement position corresponding to a target chip based on an initial placement position includes:
detecting whether the initial placing position is aligned with a preset reference position;
and if the initial placing position is aligned with the preset reference position, taking the initial placing position as a target placing position corresponding to the target chip.
In one possible implementation, the method further includes:
if the initial placing position is not aligned with the preset reference position, searching whether the reference position exists in a search area formed by taking the initial placing position as a center and taking the first offset as a radius;
and if the reference positions exist in the search area, determining the target placing positions based on the number of the reference positions and the initial placing positions.
In one possible implementation, determining the target pose position based on the number of reference positions and the initial pose position includes:
and if the number of the reference positions is one, taking the reference positions as target placing positions.
In one possible implementation, determining the target pose position based on the number of reference positions and the initial pose position includes:
if the number of the reference positions is multiple, selecting a position closest to the initial placing position from the multiple reference positions as a target reference position;
and taking the target reference position as a target placing position.
In one possible implementation, the method further includes:
and if the reference position does not exist in the search area, expanding the first offset until the reference position is found in the search area formed by taking the initial placing position as the center and the expanded first offset as the radius, and determining the placing position of the target based on the number of the reference positions and the initial placing position.
In one possible implementation manner, determining a target placement position corresponding to a target chip based on an initial placement position includes:
determining a plurality of candidate placing positions based on the initial placing position, wherein the candidate placing positions are obtained by taking the initial placing position as a starting point and moving the target chip by using a second offset;
based on the initial pose position and the plurality of candidate pose positions, a target pose position is determined.
In one possible implementation, determining the target pose location based on the initial pose location and a plurality of candidate pose locations includes:
calculating the overlapping area of all chip joints in the target chip and all joints corresponding to the initial placement positions to obtain a first overlapping area;
calculating the overlapping area of all chip joints in the target chip and all joints corresponding to each candidate placing position in the candidate placing positions to obtain a plurality of candidate overlapping areas, wherein the candidate placing positions correspond to the candidate overlapping areas one by one;
and comparing the first overlapping area with the plurality of candidate overlapping areas to determine the target placing position.
In one possible implementation, comparing the first overlap area with a plurality of candidate overlap areas to determine the target placement position includes:
and if the first overlapping area is larger than each candidate overlapping area in the candidate overlapping areas, taking the initial placing position as a target placing position.
In one possible implementation, comparing the first overlap area with a plurality of candidate overlap areas to determine the target placement position includes:
sorting the first overlap area and the plurality of candidate overlap areas according to forward sorting to obtain all sorted overlap areas;
and selecting the last overlapping area in all the sequenced overlapping areas as a target overlapping area, and taking the placing position corresponding to the target overlapping area as a target placing position.
In a possible implementation manner, calculating an overlapping area of all chip contacts in the target chip and all contacts corresponding to the initial placement positions to obtain a first overlapping area, including:
the method comprises the steps of acquiring a plurality of contact points corresponding to chip contact points aiming at each chip contact point in all chip contact points in a target chip, and determining the overlapping area of the chip contact points and each contact point in the plurality of contact points based on the distance between the circle center of the chip contact points and the circle center of each contact point in the plurality of contact points;
summarizing and calculating the overlapping area of the chip contact and each contact in the plurality of contacts to obtain the overlapping area corresponding to the chip contact;
and calculating the overlapping areas corresponding to all the chip joints to obtain a first overlapping area.
In one possible implementation, determining an overlapping area of the chip contact and each of the plurality of contacts based on a distance between a center of the chip contact and a center of a circle of each of the plurality of contacts includes:
determining a distance interval to which a distance between the circle center of the chip contact and the circle center of the contact belongs for each contact in the plurality of contacts;
and acquiring the area corresponding to the distance interval, and taking the area as the overlapping area of the chip contact and the contact.
In a second aspect, an embodiment of the present invention provides an apparatus for adjusting a chip position, including:
the detection module is used for responding to the arrangement of a target chip in a canvas and detecting the initial arrangement position of the target chip in the canvas, wherein the canvas comprises a plurality of grid units which are arranged in an array, each grid unit in the grid units is provided with a contact, and the contact is used for representing the contact point of the active silicon substrate;
and the adjusting module is used for determining a target placing position corresponding to the target chip based on the initial placing position and adjusting the target chip to the target placing position.
In a third aspect, an embodiment of the present invention provides a terminal, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the steps of any one of the above methods for adjusting a chip position.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the method for adjusting a chip position as described above are implemented.
The embodiment of the invention provides a method, a device, a terminal and a storage medium for adjusting a chip position, wherein the method comprises the following steps: the method comprises the steps of responding to a target chip arranged in a canvas, detecting an initial placing position of the target chip in the canvas, then determining a target placing position corresponding to the target chip based on the initial placing position, and adjusting the target chip to the target placing position. After the target chip is arranged in the canvas of the EDA tool, the EDA tool can automatically detect the placing position of the target chip in the canvas, namely the initial placing position, and judge whether the initial placing position is the target placing position. When the initial placing position is not the target placing position, the target placing position can be determined based on the initial placing position, and the target chip is automatically adjusted to the target placing position, so that the automatic adjustment of the position of the target chip is realized, the manual operation of designers is avoided, and the working efficiency is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, serve to provide a further understanding of the application and to enable other features, objects, and advantages of the application to be more apparent. The drawings and their description illustrate the embodiments of the invention and do not limit it. In the drawings:
FIG. 1 is a schematic diagram of a design page of existing EDA software provided by an embodiment of the present invention;
fig. 2 is a flowchart illustrating an implementation of a method for adjusting a chip position according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a chiplet U9 provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of a chiplet U2 provided in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a chiplet U23 provided in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a chiplet U1 provided by an embodiment of the present invention;
FIG. 7 is a schematic diagram of a positional relationship between a chiplet U9 and a canvas, provided by an embodiment of the present invention;
FIG. 8 is a schematic diagram of a chiplet U9 misaligned from a reference position provided by an embodiment of the present invention;
FIG. 9 is a schematic diagram of alignment of a chiplet U9 with a reference location provided by an embodiment of the present invention
FIG. 10 is a schematic diagram of the positional relationship of a chiplet U9 with multiple reference locations provided by an embodiment of the present invention;
FIG. 11 is a schematic diagram of a chiplet U2 disposed at an initial placement position E according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a chiplet U2 disposed at a first candidate placement position F according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of a chiplet U2 disposed at a second candidate placement position G according to an embodiment of the present invention;
fig. 14 is a schematic structural diagram of an apparatus for adjusting a chip position according to an embodiment of the present invention;
fig. 15 is a schematic diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein.
It should be understood that, in various embodiments of the present invention, the sequence numbers of the processes do not mean the execution sequence, and the execution sequence of the processes should be determined by the functions and the internal logic of the processes, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
It should be understood that in the present application, "comprising" and "having" and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be understood that, in the present invention, "a plurality" means two or more. "and/or" is merely an association describing an associated object, meaning that three relationships may exist, for example, and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "comprising a, B and C", "comprising a, B, C" means that all three of a, B, C are comprised, "comprising a, B or C" means comprising one of a, B, C, "comprising a, B and/or C" means comprising any 1 or any 2 or 3 of a, B, C.
It should be understood that in the present invention, "B corresponding to a", "a corresponds to B", or "B corresponds to a" means that B is associated with a, and B can be determined from a. Determining B from a does not mean determining B from a alone, but may be determined from a and/or other information. And the matching of A and B means that the similarity of A and B is greater than or equal to a preset threshold value.
As used herein, the term "if" may be interpreted as "at \8230; …" or "in response to a determination" or "in response to a detection" depending on the context.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description is made by way of specific embodiments with reference to the accompanying drawings.
Existing EDA software, as shown in fig. 1, contains few controls on an EDA software page, where what is essential is an electrical toolbar and a drawing bar, and various types of elements are arranged in the electrical toolbar, and a user can click an element that is desired to be placed on a canvas, and then place the element in the canvas by dragging, so as to perform subsequent hardware design. Wherein the component includes, but is not limited to, a chiplet.
However, because the existing EDA software does not have the functions of automatically detecting and adjusting the placement position of the chiplets, a designer is generally required to place the chiplets according to accumulated experience to achieve the accuracy of the placement position of the chiplets. However, for inexperienced designers, after the designers set the chiplets in the canvas of the EDA software, the designers need to observe whether the placement positions of the chiplets are accurate, and if the placement positions are not accurate, the designers need to manually adjust the placement positions of the chiplets.
Therefore, a great deal of time is needed for designers to finish placing the small chips, and the working efficiency is reduced.
Based on the above problems, the application provides a chip position adjusting method, which can automatically detect and adjust the placement position of a chip, and improve the working efficiency of designers.
In one embodiment, as shown in fig. 2, there is provided a chip position adjusting method, including the steps of:
step S201: and responding to the target chip arranged in the canvas, and detecting the initial placing position of the target chip in the canvas.
The target chip refers to a small chip or a core particle with any function, and includes an outer frame and a plurality of chip contacts, and the type and name of the small chip are displayed around the outer frame, and the type of the small chip is U9 and the name of the small chip is TMP108AIYFFT as shown in fig. 3.
For different types of chiplets, the parameters of the chip contacts corresponding to the chiplets are different, and the parameters of the chip contacts can be set in a chip library of the EDA tool. The parameters of the chip contacts at least include the arrangement mode of the chip contacts, the number of the chip contacts and the radius of the chip contacts.
With reference to fig. 3-6, the arrangement of the chip contacts in the chiplet U9 in fig. 3 is a regular arrangement (i.e. 2 × 3 arrangement), and the number of the chip contacts is 6; the arrangement of the chip contacts in the chiplet U2 in FIG. 4 is irregular, and the number of the chip contacts is 12; the arrangement of the chip contacts in the chiplet U23 of FIG. 5 is regular (i.e. 4 by 5) and the number of chip contacts is 20; the arrangement of the die contacts in the chiplet U1 in fig. 6 is a regular arrangement (i.e. 2 x 2 arrangement). Furthermore, the method is simple. The radii of the chip contacts in the chiplets shown in figures 3-6 are different, with the radius of the chip contact in the chiplet shown in figure 6 being the largest and the radius of the chip contact in the chiplet shown in figure 3 being the smallest.
The canvas comprises a plurality of grid units which are arranged in an array, each grid unit in the grid units is provided with a contact point, and the contact points are used for representing contact points of the active silicon substrate.
As shown in fig. 7, the plurality of contacts arranged in an array in the canvas of the EDA tool are metal bump (i.e., contact points) on the active silicon substrate. The active silicon substrate is provided with a programmable routing network, and the connection between the metal bump on the active silicon substrate can be freely set by programming the programmable routing.
Taking the target chip as the chiplet U9 as an example, after the designer selects the chiplet U9 in the chip library, the designer drags the chiplet U9 into the canvas by manually operating the mouse. At this time, when it is detected that the chiplet U9 is set in the canvas, a response is made, that is, an initial placement position of the chiplet U9 in the canvas is automatically detected, where the initial placement position may be a coordinate of a certain point in the chiplet in the canvas.
This application adopts the coordinate of a certain point in the chiplet in the canvas as initial locating position, and the reason is as follows: when the type of the chiplet is determined, knowing the coordinates of a certain point in the chiplet in the canvas, the coordinates of each point in the chiplet in the canvas can be determined continuously. For example, only the coordinates of the lower left corner of the chiplet are used as the initial placement position, and after the coordinates of the lower left corner of the chiplet are determined, the coordinates of each point on the chiplet, even the coordinates of the center of the chip contact, can be calculated based on the type of the chiplet. The position of the small chip is represented by the coordinate of a certain point, and subsequent calculation processing is performed, so that the data processing amount is reduced, and the processing speed is increased.
In addition, after the chiplet U9 is placed in the canvas, the chip contacts in the chiplet U9 can be in contact with (communicate with) the metal bumps on the active silicon substrate, so that signals can be transmitted between the chiplet and the active silicon substrate.
It should be noted that, because the radius of the chip contacts in the chiplet is different due to the different types of chiplets, the overlapping area of the chip contacts in the chiplet and the contacts in the canvas is different when the chiplet is disposed in the canvas.
Step S202: and determining a target placing position corresponding to the target chip based on the initial placing position, and adjusting the target chip to the target placing position.
When the design of the small chip placing position is carried out by using the EDA tool, when a designer pulls a target chip through a mouse, the chip contact of the small chip and the metal bump of the active silicon substrate cannot be well aligned or have a better placing position, so the target placing position needs to be determined based on the initial placing position, the automatic adjustment function aiming at the placing position of the small chip is set in the EDA tool, the design efficiency and the design effect are improved, and the design difficulty is reduced.
The target placing position of the target chip is determined through two modes, specifically as follows:
the first mode is as follows: detecting whether the initial placing position is aligned with a preset reference position, and if the initial placing position is aligned with the preset reference position, taking the initial placing position as a target placing position corresponding to a target chip; if the initial placement position is not aligned with the preset reference position, the target placement position is determined in a manner of defining a search area based on the initial placement position.
Exemplarily, referring to fig. 8, a target chip is set as a chiplet U9, a vertex a of a lower left corner of an outer frame of the chiplet U9 is set as an initial placement position of the chiplet U9, and a grid point B closest to the initial placement position in a canvas is set as a preset reference position, and then, as can be seen from fig. 8, the vertex a of the lower left corner of the outer frame of the chiplet U9 is not aligned with the closest grid point B thereof, a search area can be defined based on the initial placement position to determine the target placement position, that is, whether a reference position exists in the search area formed by taking the initial placement position as a center and taking a first offset as a radius, and if a reference position exists in the search area, the target placement position is determined based on the number of reference positions and the initial placement position. The first offset may be set according to specific situations, and is not limited herein.
Further, with reference to fig. 8 to 9, if the number of the reference positions is one, that is, as shown in fig. 8, at grid point B, the reference position is set as the target placement position, and then the vertex a at the lower left corner of the outer frame of the chiplet U9 is adjusted to grid point B, as shown in fig. 9, so that the vertex at the lower left corner of the outer frame of the chiplet U9 coincides with grid point B.
If the number of reference positions is plural, as shown in fig. 10 as 3, including grid point B, grid point C, and grid point D, from the 3 reference positions: and selecting a position closest to the vertex A at the lower left corner of the outer frame of the small chip U9 from the grid points B, C and D as a target reference point, namely the grid point B, and taking the grid point B as a target placing position. Then, the vertex a of the lower left corner of the outer frame of the chiplet U9 is adjusted to grid point B, as shown in fig. 9, so that the vertex of the lower left corner of the outer frame of the chiplet U9 coincides with grid point B.
In addition, if no reference position exists in the search area, the first offset is expanded until the reference position is found in the search area formed by taking the initial placement position as the center and the expanded first offset as the radius, and the step of determining the target placement position based on the number of the reference positions and the initial placement position is performed.
Exemplarily, assuming that the first offset is a, when a search is performed by using the first offset a as a radius, the reference position is not found, and the first offset a may be enlarged by a preset multiple, where the preset multiple may be 2, 3, and the like, and is not limited herein. And when the preset multiple is 2, searching in a search area formed by taking the initial placing position as the center and taking 2a as the radius if the expanded first offset is 2a, if the reference position is found, determining the target placing position based on the number of the reference positions and the initial placing position, if one reference position is found, taking the reference position as the target placing position, and if a plurality of reference positions are found, selecting the reference position closest to the initial placing position as the target placing position. Optionally, when a plurality of reference positions are found, a suitable reference position may be selected as the target placement position according to various preset rules, for example, as far as possible away from an existing chiplet, as far as possible away from an edge of the active silicon substrate, and the like.
In addition, if the reference position is not found in the search area formed by taking the initial placing position as the center and taking the radius of 2a as the radius, the offset is continuously expanded, namely the reference position is found in the search area formed by taking the initial placing position as the center and taking the radius of 4a as the radius, and if the reference position is not found, the offset is continuously expanded until the reference position is found.
In this embodiment, this application not only automated inspection target chip's initial locating position to seek the reference position through initial locating position is automatic, and then confirm target chip's target locating position, realized the automation that target chip put, need not the designer and carry out manual operation, save designer's time, and then improved chip position adjustment, put the efficiency of work.
The second mode is as follows: and determining a plurality of candidate placing positions based on the initial placing position, wherein the plurality of candidate placing positions are obtained by taking the initial placing position as a starting point and moving the target chip by using the second offset, and then determining the target placing position based on the initial placing position and the plurality of candidate placing positions. The second offset amount may be set according to specific situations, and is not limited herein.
For example, referring to fig. 11-13, assuming that the target chip is the chiplet U2, the initial placement position of the chiplet U2 is the point E in the canvas, and moving the chiplet U2 with the second offset using the point E as the starting point, two candidate placement positions can be obtained, a first candidate placement position, i.e., the point F shown in fig. 12, and a second candidate placement position, i.e., the point G shown in fig. 13. Then, the target placement position can be determined from the initial placement position E, the first placement position candidate F, and the second placement position candidate G.
After the initial placement position and the plurality of candidate placement positions are determined, the target placement position needs to be determined by calculating the overlapping area of all chip contacts in the target chip and all contacts corresponding to the initial placement position and the plurality of candidate placement positions. Specifically, the overlapping area of all chip contacts in the target chip and all contacts corresponding to the initial placement positions is calculated to obtain a first overlapping area, then the overlapping area of all chip contacts in the target chip and all contacts corresponding to each candidate placement position in the candidate placement positions is calculated to obtain a plurality of candidate overlapping areas, wherein the candidate placement positions are in one-to-one correspondence with the candidate overlapping areas, and then the first overlapping area and the candidate overlapping areas are compared to determine the target placement position.
Comparing the first overlapping area with a plurality of candidate overlapping areas to determine a target placing position, wherein the two situations are included, namely if the first overlapping area is larger than each candidate overlapping area in the plurality of candidate overlapping areas, the initial placing position is used as the target placing position; and sequencing the first overlapping area and the plurality of candidate overlapping areas according to forward sequencing to obtain all sequenced overlapping areas, selecting the last overlapping area in all sequenced overlapping areas as a target overlapping area, and taking the placing position corresponding to the target overlapping area as a target placing position.
Exemplarily, with reference to fig. 11 to 13, the overlapping areas of all the joints corresponding to the initial placement position E, the first candidate placement position F, and the second candidate placement position G of 12 chip joints in the chiplet U2 are calculated to obtain a first overlapping area S1, a first candidate overlapping area S2, and a second candidate overlapping area S3, respectively. If the first overlapping area S1 is larger than the first candidate overlapping area S2 and the second candidate overlapping area S3, taking an initial placing position E corresponding to the first overlapping area S1 as a target placing position; if the first overlap area S1< the first candidate overlap area S2< the second candidate overlap area S3, the second placement position candidate G corresponding to the second candidate overlap area S3, which is the maximum area, is used as the target placement position.
Further, a first overlapping area is obtained by calculating overlapping areas of all chip contacts in the target chip and all contacts corresponding to the initial placement positions, a plurality of contacts corresponding to the chip contacts are obtained by aiming at each chip contact in all chip contacts in the target chip, the overlapping areas of the chip contacts and each contact in the plurality of contacts are determined based on the distance between the circle center of the chip contact and the circle center of each contact in the plurality of contacts, then the overlapping areas of the chip contacts and each contact in the plurality of contacts are collected and calculated to obtain the overlapping areas corresponding to the chip contacts, and then the overlapping areas corresponding to all the chip contacts are subjected to summation calculation to obtain the first overlapping area.
The overlapping area of the chip contact and each contact in the plurality of contacts is determined based on the distance between the circle center of the chip contact and the circle center of each contact in the plurality of contacts, a distance interval to which the distance between the circle center of the chip contact and the circle center of the contact belongs needs to be determined for each contact in the plurality of contacts, then the area corresponding to the distance interval is obtained, and the area is used as the overlapping area of the chip contact and the contact. The overlapping area is calculated in such a way, the calculation speed can be guaranteed to a certain degree under the condition that the calculation accuracy of the overlapping area is guaranteed, the calculation amount is reduced to a certain degree, and therefore the speed of determining the target placement position is improved.
For example, referring to fig. 11, taking the first chip contact in the upper left corner of the chiplet U2 as an example, it can be seen from fig. 11 that the first chip contact in the upper left corner covers a plurality of contacts in the canvas. Because the first chip contact in the upper left corner only partially covers with some contact in the canvas, the overlapping area at this moment is difficult to calculate accurately, consequently, this application determines its overlapping area through the distance interval that the distance between the centre of a circle of the first chip contact in the upper left corner and the centre of a circle of the contact in the canvas belongs to.
Specifically, the first distance interval is set to be [0-1.5cm ], and the corresponding area is L1; the second distance interval is [1.6-2cm ], and the corresponding area is L2; the third distance interval is [2.1-2.5cm ], and the corresponding area is L3; the fourth distance interval is [2.6-3cm ], and the corresponding area is L4, wherein L1> L2> L3> L4. As can be seen from fig. 11, the first chip contact in the upper left corner overlaps with 7 contacts in the canvas, where 3 contacts are completely covered and the other 4 contacts are partially covered. That is, the distance between the completely covered 3 contacts and the center of the first chip contact at the upper left corner belongs to a first distance interval [0-1.5cm ], and the area corresponding thereto is 3L1, the distance between 3 contacts of the other 4 contacts and the center of the first chip contact at the upper left corner belongs to a third distance interval [2.1-2.5cm ], and the area corresponding thereto is 3L3, and the distance between the other contact and the center of the first chip contact at the upper left corner belongs to a fourth distance interval [2.6-3cm ], and the area corresponding thereto is L4. And calculating the sum of all the areas to obtain the overlapping area Y1=3L1+3L3+ L4 of the first chip contact at the upper left corner and a plurality of contacts in the covered canvas.
By the method, the overlapping area of the other chip contacts in the small chip U2 and the contacts in the covered canvas can be calculated, and then the overlapping area of all the chip contacts in the small chip U2 and the contacts in the covered canvas is calculated to obtain the first overlapping area S1.
It should be noted that, in the present application, the overlapping areas of all chip joints in the target chip and all joints corresponding to each candidate placement position in the multiple candidate placement positions are calculated, and a manner of determining the multiple candidate overlapping areas is similar to a manner of calculating the first overlapping area, and details are not repeated here.
Alternatively, the determination of the target placement position of the target chip may be implemented by combining the first and second manners, specifically, when a plurality of reference positions are determined in a manner that the search area is defined based on the initial placement position as mentioned in the first manner, the overlapping area of all chip contacts in the target chip and all contacts corresponding to the plurality of reference positions may be calculated in a manner that the overlapping area is calculated as mentioned in the second manner, and finally, one reference position is selected from the plurality of reference positions as the target placement position according to the overlapping area corresponding to each reference position. The determination process of the reference position, the calculation process of the overlapping area, and the selection process of the target placement position are all similar to the first and second manners, and are not repeated one by one to avoid repetition.
The embodiment of the invention provides a method for adjusting a chip position, which comprises the following steps: the method comprises the steps of responding to a target chip arranged in a canvas, detecting an initial placing position of the target chip in the canvas, then determining a target placing position corresponding to the target chip based on the initial placing position, and adjusting the target chip to the target placing position. After the target chip is arranged in the canvas of the EDA tool, the EDA tool can automatically detect the placing position of the target chip in the canvas, namely the initial placing position, and judge whether the initial placing position is the target placing position. When the initial placing position is not the target placing position, the target placing position can be determined based on the initial placing position, and the target chip is automatically adjusted to the target placing position, so that the automatic adjustment of the position of the target chip is realized, the manual operation of designers is avoided, and the working efficiency is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The following are embodiments of the apparatus of the invention, reference being made to the corresponding method embodiments described above for details which are not described in detail therein.
Fig. 14 shows a schematic structural diagram of an apparatus for adjusting a chip position according to an embodiment of the present invention, and for convenience of description, only parts related to the embodiment of the present invention are shown, and the apparatus for adjusting a chip position includes a detection module 1401 and an adjustment module 1402, which are specifically as follows:
a detection module 1401, configured to detect an initial placement position of a target chip in a canvas in response to the target chip being disposed in the canvas, where the canvas includes a plurality of grid cells arranged in an array, and each grid cell in the plurality of grid cells is provided with a contact, and the contact is used for representing a contact point of an active silicon substrate;
the adjusting module 1402 is configured to determine a target placement position corresponding to the target chip based on the initial placement position, and adjust the target chip to the target placement position.
In a possible implementation manner, the adjusting module 1402 is further configured to detect whether the initial placement position is aligned with a preset reference position; and if the initial placing position is aligned with the preset reference position, taking the initial placing position as a target placing position corresponding to the target chip.
In a possible implementation manner, the device further includes a first search unit, where the first search unit is configured to, if the initial placement position is not aligned with a preset reference position, find whether there is a reference position in a search area formed by taking the initial placement position as a center and taking the first offset as a radius; and if the reference positions exist in the search area, determining the target placement position based on the number of the reference positions and the initial placement position.
In a possible implementation manner, the first searching unit is further configured to use the reference position as the target placement position if the number of the reference positions is one.
In a possible implementation manner, the first searching unit is further configured to select, as the target reference position, a position closest to the initial placement position from the plurality of reference positions if the number of reference positions is plural; and taking the target reference position as a target placing position.
In a possible implementation manner, the device further includes a second search unit, where the second search unit is configured to, if the reference position does not exist in the search area, expand the first offset until the reference position is found in the search area formed by taking the initial placement position as a center and the expanded first offset as a radius, and perform the step of determining the target placement position based on the number of the reference positions and the initial placement position.
In a possible implementation manner, the adjusting module 1402 is further configured to determine a plurality of candidate placing positions based on the initial placing position, where the candidate placing positions are obtained by using the initial placing position as a starting point and moving the target chip by using the second offset; and determining a target placing position based on the initial placing position and the plurality of candidate placing positions.
In a possible implementation manner, the adjusting module 1402 is further configured to calculate overlapping areas of all chip contacts in the target chip and all contacts corresponding to the initial placement positions, so as to obtain a first overlapping area; calculating the overlapping area of all chip joints in the target chip and all joints corresponding to each candidate placing position in the candidate placing positions to obtain a plurality of candidate overlapping areas, wherein the candidate placing positions correspond to the candidate overlapping areas one by one; and comparing the first overlapping area with the candidate overlapping areas to determine the target placement position.
In a possible implementation manner, the adjusting module 1402 is further configured to take the initial placement position as the target placement position if the first overlap area is larger than each candidate overlap area in the plurality of candidate overlap areas.
In a possible implementation manner, the adjusting module 1402 is further configured to rank the first overlap area and the multiple candidate overlap areas according to a forward rank to obtain all ranked overlap areas; and selecting the last overlapping area in all the sequenced overlapping areas as a target overlapping area, and taking the placing position corresponding to the target overlapping area as a target placing position.
In a possible implementation manner, the adjusting module 1402 is further configured to obtain, for each chip contact of all chip contacts in the target chip, a plurality of contacts corresponding to the chip contact, and determine an overlapping area of the chip contact and each contact of the plurality of contacts based on a distance between a center of the chip contact and a center of a circle of each contact of the plurality of contacts; summarizing and calculating the overlapping area of the chip contact and each contact in the plurality of contacts to obtain the overlapping area corresponding to the chip contact; and calculating the overlapping areas corresponding to all the chip joints to obtain a first overlapping area.
In a possible implementation manner, the adjusting module 1402 is further configured to determine, for each of the plurality of contacts, a distance interval to which a distance between a center of a circle of the chip contact and a center of the circle of the contact belongs; and acquiring the area corresponding to the distance interval, and taking the area as the overlapping area of the chip contact and the contact.
Fig. 15 is a schematic diagram of a terminal according to an embodiment of the present invention. As shown in fig. 15, the terminal 15 of this embodiment includes: a processor 1501, a memory 1502, and a computer program 1503 stored in the memory 1502 and operable on the processor 1501. The processor 1501 executes the computer program 1503 to implement the steps in the above-described embodiments of the method for adjusting the chip position, such as the steps 201 to 202 shown in fig. 2. Alternatively, the processor 1501, when executing the computer program 1503, implements the functions of the modules/units in the above-described embodiment of the apparatus for adjusting the chip position, such as the functions of the modules/units 1401 to 1402 shown in fig. 14.
The present invention also provides a readable storage medium, in which a computer program is stored, and the computer program is used for implementing the chip position adjusting method provided by the above various embodiments when executed by a processor.
The readable storage medium may be a computer storage medium or a communication medium. Communication media includes any medium that facilitates transfer of a computer program from one place to another. Computer storage media can be any available media that can be accessed by a general purpose or special purpose computer. For example, a readable storage medium is coupled to the processor such that the processor can read information from, and write information to, the readable storage medium. Of course, the readable storage medium may also be an integral part of the processor. The processor and the readable storage medium may reside in an Application Specific Integrated Circuits (ASIC). Additionally, the ASIC may reside in user equipment. Of course, the processor and the readable storage medium may also reside as discrete components in a communication device. The readable storage medium may be a read-only memory (ROM), a random-access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
The present invention also provides a program product comprising executable instructions stored on a readable storage medium. The at least one processor of the device may read the execution instruction from the readable storage medium, and the execution of the execution instruction by the at least one processor causes the device to implement the chip position adjustment method provided by the various embodiments described above.
In the above embodiments of the apparatus, it is understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of hardware and software modules.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.
Claims (15)
1. A method for adjusting chip position is characterized by comprising the following steps:
detecting an initial placement position of a target chip in a canvas in response to the target chip being arranged in the canvas, wherein the canvas comprises a plurality of grid cells arranged in an array, each grid cell of the grid cells is provided with a contact point, and the contact point is used for representing a contact point of an active silicon substrate;
and determining a target placing position corresponding to the target chip based on the initial placing position, and adjusting the target chip to the target placing position.
2. The method for adjusting chip position according to claim 1, wherein determining the target placement position corresponding to the target chip based on the initial placement position comprises:
detecting whether the initial placing position is aligned with a preset reference position;
and if the initial placing position is aligned with the preset reference position, taking the initial placing position as a target placing position corresponding to the target chip.
3. The method for adjusting the position of a chip according to claim 2, wherein the method further comprises:
if the initial placing position is not aligned with the preset reference position, searching whether the reference position exists in a search area formed by taking the initial placing position as a center and taking a first offset as a radius;
and if the reference positions exist in the search area, determining the target placing position based on the number of the reference positions and the initial placing position.
4. The method for adjusting chip position according to claim 3, wherein the determining the target placement position based on the number of the reference positions and the initial placement position comprises:
and if the number of the reference positions is one, taking the reference positions as the target placing positions.
5. The method for adjusting chip position according to claim 3, wherein the determining the target placement position based on the number of the reference positions and the initial placement position comprises:
if the number of the reference positions is multiple, selecting a position closest to the initial placement position from the multiple reference positions as a target reference position;
and taking the target reference position as the target placing position.
6. The method for adjusting the position of a chip according to claim 3, wherein the method further comprises:
if the reference position does not exist in the search area, expanding the first offset until the reference position is found in the search area formed by taking the initial placing position as the center and the expanded first offset as the radius, and executing the step of determining the target placing position based on the number of the reference positions and the initial placing position.
7. The method for adjusting chip position according to claim 1, wherein the determining the target placement position corresponding to the target chip based on the initial placement position comprises:
determining a plurality of candidate placing positions based on the initial placing positions, wherein the candidate placing positions are obtained by taking the initial placing positions as starting points and moving the target chip by using a second offset;
determining the target pose position based on the initial pose position and the plurality of candidate pose positions.
8. The method for adjusting chip position according to claim 7, wherein the determining the target placement position based on the initial placement position and the plurality of candidate placement positions comprises:
calculating the overlapping area of all chip joints in the target chip and all joints corresponding to the initial placing positions to obtain a first overlapping area;
calculating the overlapping area of all chip joints in the target chip and all joints corresponding to each candidate placing position in the candidate placing positions to obtain a plurality of candidate overlapping areas, wherein the candidate placing positions are in one-to-one correspondence with the candidate overlapping areas;
and comparing the first overlapping area with a plurality of candidate overlapping areas to determine the target placing position.
9. The method for adjusting chip positions according to claim 8, wherein the comparing the first overlap area with a plurality of candidate overlap areas to determine the target placement position comprises:
and if the first overlapping area is larger than each candidate overlapping area in the candidate overlapping areas, taking the initial placing position as the target placing position.
10. The method for adjusting chip positions according to claim 8, wherein the comparing the first overlap area with a plurality of candidate overlap areas to determine the target placement position comprises:
sorting the first overlap area and the candidate overlap areas according to a forward sorting to obtain all sorted overlap areas;
and selecting the last overlapping area in all the sequenced overlapping areas as a target overlapping area, and taking the placing position corresponding to the target overlapping area as the target placing position.
11. The method for adjusting chip positions according to claim 8, wherein the calculating the overlapping area of all chip contacts in the target chip and all contacts corresponding to the initial placement position to obtain a first overlapping area comprises:
acquiring a plurality of contacts corresponding to the chip contacts for each of all the chip contacts in the target chip, and determining the overlapping area of the chip contacts and each of the plurality of contacts based on the distance between the circle center of the chip contact and the circle center of each of the plurality of contacts;
summarizing and calculating the overlapping area of the chip contact and each contact in the plurality of contacts to obtain the overlapping area corresponding to the chip contact;
and calculating the overlapping areas corresponding to all the chip joints to obtain the first overlapping area.
12. The method for adjusting chip position according to claim 11, wherein said determining an overlapping area of the chip contact and each of the plurality of contacts based on a distance between a center of the chip contact and a center of a circle of each of the plurality of contacts comprises:
determining a distance interval to which a distance between the circle center of the chip contact and the circle center of the contact belongs, for each contact in the plurality of contacts;
and acquiring the area corresponding to the distance interval, and taking the area as the overlapping area of the chip contact and the contact.
13. An apparatus for adjusting a position of a chip, comprising:
the detection module is used for responding to the arrangement of a target chip in a canvas and detecting the initial arrangement position of the target chip in the canvas, wherein the canvas comprises a plurality of grid units arranged in an array, each grid unit in the grid units is provided with a contact point, and the contact points are used for representing contact points of an active silicon substrate;
and the adjusting module is used for determining a target placing position corresponding to the target chip based on the initial placing position and adjusting the target chip to the target placing position.
14. A terminal comprising a memory and one or more processors communicatively coupled to the memory;
the memory stores instructions executable by the one or more processors to cause the one or more processors to implement the method of adjusting chip position according to any one of claims 1 to 12.
15. A computer-readable storage medium characterized by comprising a program or instructions for implementing the chip position adjustment method according to any one of claims 1 to 12 when the program or instructions are run on a computer.
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| CN202211401335.5A CN115763342A (en) | 2022-11-09 | 2022-11-09 | Chip position adjusting method and device, terminal and storage medium |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116663483A (en) * | 2023-07-31 | 2023-08-29 | 全芯智造技术有限公司 | Method, apparatus and medium for chip layout |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116663483A (en) * | 2023-07-31 | 2023-08-29 | 全芯智造技术有限公司 | Method, apparatus and medium for chip layout |
| CN116663483B (en) * | 2023-07-31 | 2023-10-20 | 全芯智造技术有限公司 | Method, apparatus and medium for chip layout |
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