CN114141765A - Integrated circuit wiring method and device and terminal equipment - Google Patents
Integrated circuit wiring method and device and terminal equipment Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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Abstract
The application is applicable to the technical field of semiconductors and provides an integrated circuit wiring method, an integrated circuit wiring device and terminal equipment. The integrated circuit wiring method comprises the following steps: receiving an integrated circuit wiring instruction, wherein the integrated circuit wiring instruction comprises chip PAD position information and bonding finger position information; the chip PAD position information and the bonding finger position information meet the following conditions: the coordinate of the PAD of the chip to be designed is consistent with the coordinate of the center of each bonding finger to be designed; responding to an integrated circuit wiring instruction, and setting a chip to be designed and a bonding finger to be designed in a first layer based on chip PAD position information and bonding finger position information so as to realize communication between the chip PAD to be designed and the bonding finger to be designed; and carrying out wiring based on the connected PAD of the chip to be designed or each bonding finger to be designed. The method and the device can greatly reduce the workload of wiring of the integrated circuit and provide the efficiency of wiring of the integrated circuit.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a wiring method and device of an integrated circuit and terminal equipment.
Background
The conventional integrated circuit may include a chip, a plurality of bonding fingers, and a bonding wire, where the chip is connected to each bonding finger through the bonding wire, so as to implement data transmission between the chip inside the integrated circuit and an external device. Before the integrated circuit is trial-produced or mass-produced, the integrated circuit needs to be designed and simulated to determine the performance of the integrated circuit. Conventional integrated circuit design methods typically connect the PAD and the bonding fingers of the chip with bonding wires and then perform wiring. However, the inventors of the present application found in their studies that: when the number of bonding fingers in a designed integrated circuit is large, the design process for the integrated circuit takes much time.
Disclosure of Invention
In order to overcome the problems in the related art, the embodiments of the present application provide a method and an apparatus for routing an integrated circuit housing, and a terminal device.
The application is realized by the following technical scheme:
in a first aspect, an embodiment of the present application provides an integrated circuit wiring method, including:
receiving an integrated circuit wiring instruction, wherein the integrated circuit wiring instruction comprises chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information; the chip PAD position information and the bonding finger position information meet the following conditions: the coordinate of the PAD of the chip to be designed is consistent with the coordinate of the center of each bonding finger to be designed;
responding to the integrated circuit wiring instruction, and setting a chip to be designed and a bonding finger to be designed in a first layer based on the chip PAD position information and the bonding finger position information so as to realize the communication between the chip PAD to be designed and the bonding finger to be designed;
and carrying out wiring based on the connected PAD of the chip to be designed or each bonding finger to be designed.
According to the integrated circuit wiring method, after the integrated circuit wiring instruction is received, the chip to be designed and the bonding finger to be designed are arranged in the first layer based on the chip PAD position information and the bonding finger position information in the integrated circuit wiring instruction, so that the arranged chip PAD to be designed and the bonding finger to be designed can be directly communicated, bonding wires do not need to be arranged between the chip PAD and the bonding finger, and a large number of bonding wires are needed to be arranged for the chip PAD and the bonding finger.
As an implementation manner, the setting a chip to be designed and a bonding finger to be designed in a first layer based on the chip PAD position information and the bonding finger position information includes:
generating a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information;
and adjusting a chip to be designed and a bonding finger to be designed into the first layer.
As another possible implementation manner, the setting a chip to be designed and a bonding finger to be designed in the same layer based on the chip PAD position information and the bonding finger position information includes:
and jumping to the first layer, and generating a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information.
Optionally, the integrated circuit wiring instruction further includes chip parameter information and bonding finger parameter information;
the generating of the chip to be designed and the bonding finger to be designed includes:
and generating a chip to be designed according to the chip parameter information, and generating a bonding finger to be designed according to the bonding finger parameter information.
In some embodiments, after said receiving an integrated circuit routing instruction, the method further comprises: responding to the integrated circuit wiring instruction, and determining a first position of a chip PAD to be designed in a preset area based on the chip PAD position information;
setting the chip to be designed based on the chip PAD position information, comprising: and setting a chip to be designed into the first layer based on the position information of the chip PAD, so that the chip PAD to be designed is located at the first position.
In still other embodiments, after the receiving an integrated circuit routing instruction, the method further comprises: responding to the integrated circuit wiring instruction, and determining a second position of each bonding finger to be designed in a preset area based on the bonding finger position information;
setting each bonding finger to be designed based on the bonding finger position information, including: and setting each bonding finger to be designed into the first image layer based on the bonding finger position information, so that the center of the bonding finger to be designed is located at the second position.
In some possible implementations, the method further includes:
and when the chip to be designed and the bonding to be designed are detected to be positioned on the same layer, and the coordinate of the PAD of the chip to be designed and the coordinate of the center of each bonding finger to be designed are positioned in a preset range, communicating the PAD of the chip to be designed and the bonding finger to be designed.
In a second aspect, an embodiment of the present application provides an integrated circuit wiring device, including:
the integrated circuit wiring instruction comprises chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information; the chip PAD position information and the bonding finger position information meet the following conditions: the coordinate of the PAD of the chip to be designed is consistent with the coordinate of the center of each bonding finger to be designed;
the instruction response module is used for responding to the integrated circuit wiring instruction, and setting a chip to be designed and a bonding finger to be designed in a first layer based on the chip PAD position information and the bonding finger position information so as to realize the communication between the chip PAD to be designed and the bonding finger to be designed;
and the wiring module is used for carrying out wiring based on the connected PAD of the chip to be designed or each bonding finger to be designed.
In a third aspect, an embodiment of the present application provides a terminal device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the integrated circuit wiring method according to any one of the first aspect when executing the computer program.
In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the integrated circuit wiring method according to any one of the first aspect.
In a fifth aspect, the present application provides a computer program product, which when run on a terminal device, causes the terminal device to execute the integrated circuit wiring method according to any one of the first aspect.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the specification.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic flow chart diagram illustrating a method for routing an integrated circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of an integrated circuit layout design provided by an embodiment of the present application;
FIG. 3 is a schematic structural diagram of an integrated circuit wiring device according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The conventional integrated circuit may include a chip, a plurality of bonding fingers, and a bonding wire, where the chip is connected to each bonding finger through the bonding wire, so as to implement data transmission between the chip inside the integrated circuit and an external device. Before the integrated circuit is trial-produced or mass-produced, the integrated circuit needs to be designed and simulated to determine the performance of the integrated circuit. The conventional integrated circuit design method is generally to connect the PAD and the bonding finger of the chip through a bonding wire, and then to perform buried layer wiring.
However, the inventors of the present application found in their studies that: when the number of bonding fingers in the designed integrated circuit is large, a large number of bonding wires are needed to be arranged to connect the chip PAD and each bonding finger, which takes much time for the design process of the integrated circuit wiring and seriously affects the working efficiency.
In view of the above problems, embodiments of the present application provide an integrated circuit wiring method, and fig. 1 shows a schematic flowchart of the integrated circuit wiring method. Referring to fig. 1, the wiring method of the integrated circuit is described in detail as follows:
The chip PAD position information and the bonding finger position information meet the following conditions: and the coordinate of the PAD of the chip to be designed is consistent with the coordinate of the center of each bonding finger to be designed.
For example, the coordinates of the PAD of the chip to be designed are consistent with the coordinates of the center of each bonding finger to be designed, and may be the same as the coordinates of the center of each bonding finger to be designed, or the coordinates of the PAD of the chip to be designed and the coordinates of the center of each bonding finger to be designed are located in a preset range. The coordinates may be coordinates in an area for displaying the designed integrated circuit in the integrated circuit wiring interface displayed by the terminal device.
In some embodiments, before step 101, the integrated circuit routing method may include: and detecting a preset operation and generating an integrated circuit wiring instruction. The preset operation can be a specific operation applied by a user in an integrated circuit wiring interface of the terminal equipment.
For example, after the terminal device displays an integrated circuit wiring interface, a user inputs chip PAD position information, bonding finger position information and the like in the interface, and then applies a click operation to a control for starting integrated circuit wiring, and at this time, the terminal device detects the click operation and generates a basic circuit wiring instruction.
It should be noted that the PAD position information and the bonding finger position information of the chip may be specific position coordinates, for example, the two position information are two specific position coordinates in a preset area. Alternatively, the chip PAD position information and the bonding finger position information may be a relationship between two pieces of position information, for example, two pieces of position information indicating a distance range between the chip PAD and the bonding finger, and the like. Alternatively, the chip PAD position information and the bonding finger position information may be two position areas.
And step 102, responding to the integrated circuit wiring instruction, and setting a chip to be designed and a bonding finger to be designed in a first layer based on the chip PAD position information and the bonding finger position information so as to realize communication between the chip PAD to be designed and the bonding finger to be designed.
In some implementation manners, the setting a chip to be designed and a bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information may include: generating a chip to be designed and a bonding finger to be designed based on the position information of the PAD of the chip and the position information of the bonding finger; and adjusting the chip to be designed and the bonding finger to be designed into the first layer.
Specifically, a chip to be designed and a bonding finger to be designed can be generated based on the position information of the PAD of the chip and the position information of the bonding finger; and then, adjusting the generated chip to be designed and the bonding finger to be designed to the first layer for displaying.
In still other implementation manners, the setting a chip to be designed and a bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information may include: and jumping to the first layer, and generating a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information.
Specifically, the chip to be designed and the bonding finger to be designed may be directly generated and displayed in the first layer based on the chip PAD position information and the bonding finger position information.
Illustratively, the integrated circuit wiring instruction may further include chip parameter information and bonding finger parameter information. Correspondingly, the generating of the chip to be designed and the bonding finger to be designed may specifically include: and generating a chip to be designed according to the chip parameter information, and generating a bonding finger to be designed according to the bonding finger parameter information.
For example, the chip parameter information may include at least one of: chip model, chip performance, chip number, etc. And if the chip parameter information comprises the chip model, generating a chip to be designed according to the chip model, wherein the generated chip to be designed has the physical structure and function of the chip corresponding to the chip model. And if the chip parameter information comprises the chip performance, determining a corresponding chip in a chip database according to the chip performance, and further generating a chip to be designed. If the chip parameter information includes the number of chips, a common chip can be determined in a chip database, and a chip to be designed is generated according to the common chip and the number of chips. And if the chip parameter information comprises at least two of the chip model, the chip performance and the chip quantity, generating the chip to be designed according to the contained information.
For example, the bonding finger parameter information may include at least one of: number of bonding fingers, size of bonding fingers, shape of bonding fingers, etc. And if the bonding finger parameter information comprises the size of the bonding finger, determining the corresponding bonding finger in a bonding finger database according to the size of the bonding finger, and further generating the bonding finger to be designed. And if the bonding finger parameter information comprises the number of the bonding fingers, determining the common bonding fingers in a bonding finger database, and generating the bonding fingers to be designed according to the common bonding fingers and the number of the bonding fingers. If the bonding finger parameter information comprises the shape of the bonding finger, the corresponding bonding finger can be determined in the bonding finger database according to the shape of the bonding finger, and then the bonding finger to be designed is generated. And if the bonding finger parameter information comprises at least two of the number of the bonding fingers, the size of the bonding fingers and the shape of the bonding fingers, generating the bonding fingers to be designed according to the contained information.
In some embodiments, after step 101, the integrated circuit wiring method may further include: and determining a first position of the chip PAD to be designed in the preset area based on the position information of the chip PAD in response to the wiring instruction of the integrated circuit. Correspondingly, the step 102 of setting the chip to be designed based on the PAD position information of the chip includes: and setting the chip to be designed into the first layer based on the position information of the chip PAD, so that the chip PAD to be designed is located at the first position.
In some embodiments, after step 101, the integrated circuit wiring method may further include: and determining a second position of each bonding finger to be designed in the preset area based on the bonding finger position information in response to the integrated circuit wiring instruction. Correspondingly, in step 102, setting each bonding finger to be designed based on the bonding finger position information includes: and setting each bonding finger to be designed into the first layer based on the bonding finger position information, so that the center of the bonding finger to be designed is located at the second position.
In the embodiment of the application, if the chip to be designed and the bonding to be designed are located on the same layer and the coordinate of the PAD of the chip to be designed is consistent with the coordinate of the center of each bonding finger to be designed, the PAD of the chip to be designed and the bonding finger to be designed are communicated.
In one scenario, if it is detected that the chip to be designed and the bonding to be designed are located in the same layer, and the coordinate of the PAD of the chip to be designed is the same as the coordinate of the center of each bonding finger to be designed, as shown in fig. 2, the PAD of the chip to be designed and the bonding finger to be designed are communicated.
In another scenario, if it is detected that the chip to be designed and the bonding finger to be designed are located in the same layer, and the coordinate of the PAD of the chip to be designed and the coordinate of the center of each bonding finger to be designed are located in a preset range, the PAD of the chip to be designed and the bonding finger to be designed are communicated.
And 103, wiring is carried out based on the connected PAD of the chip to be designed or each bonding finger to be designed.
Illustratively, after the connected chip PAD to be designed and bonding fingers to be designed are obtained through steps 101 and 102, the wiring can be led out from the bonding fingers to be designed directly at the time of buried layer wiring or from the chip PAD to be designed. As shown in fig. 2, wiring is led out from the bonding fingers to be designed.
According to the integrated circuit wiring method, after the integrated circuit wiring instruction is received, the chip to be designed and the bonding finger to be designed are arranged in the first layer based on the chip PAD position information and the bonding finger position information in the integrated circuit wiring instruction, so that the arranged chip PAD to be designed and the bonding finger to be designed can be directly communicated, bonding wires do not need to be arranged between the chip PAD and the bonding finger, and a large number of bonding wires are needed to be arranged for the chip PAD and the bonding finger.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Fig. 3 shows a block diagram of the integrated circuit wiring device provided in the embodiment of the present application, corresponding to the integrated circuit wiring method described in the above embodiment, and only the parts related to the embodiment of the present application are shown for convenience of illustration.
Referring to fig. 3, the integrated circuit wiring device 200 in the embodiment of the present application may include an instruction receiving module 201, an instruction responding module 202, and a wiring module 203.
The instruction receiving module 201 is configured to receive an integrated circuit wiring instruction, where the integrated circuit wiring instruction includes chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information. The chip PAD position information and the bonding finger position information meet the following conditions: and the coordinate of the PAD of the chip to be designed is consistent with the coordinate of the center of each bonding finger to be designed.
And the instruction response module 202 is configured to respond to the integrated circuit wiring instruction, and set a chip to be designed and a bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information, so as to communicate the chip to be designed PAD with the bonding finger to be designed.
And the wiring module 203 is used for carrying out wiring based on the connected to-be-designed chip PAD or each to-be-designed bonding finger.
In one embodiment, the command response module 202 is configured to: generating a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information; and adjusting a chip to be designed and a bonding finger to be designed into the first layer.
In yet another possible implementation, the command response module 202 is configured to: and jumping to the first layer, and generating a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information.
Optionally, the integrated circuit wiring instruction further includes chip parameter information and bonding finger parameter information; the generating of the chip to be designed and the bonding finger to be designed includes: and generating a chip to be designed according to the chip parameter information, and generating a bonding finger to be designed according to the bonding finger parameter information.
In some embodiments, the integrated circuit wiring device 200 may further include: and the first position determining module is used for responding to the wiring instruction of the integrated circuit and determining the first position of the chip PAD to be designed in the preset area based on the position information of the chip PAD. Correspondingly, the instruction response module 200 sets the chip to be designed based on the PAD position information of the chip, including: and setting a chip to be designed into the first layer based on the position information of the chip PAD, so that the chip PAD to be designed is located at the first position.
In some embodiments, the integrated circuit wiring device 200 may further include: and the second position determining module is used for responding to the integrated circuit wiring instruction and determining the second position of each bonding finger to be designed in the preset area based on the bonding finger position information. Correspondingly, the instruction response module 200 sets each bonding finger to be designed based on the bonding finger position information, including: and setting each bonding finger to be designed into the first image layer based on the bonding finger position information, so that the center of the bonding finger to be designed is located at the second position.
Optionally, the integrated circuit wiring device 200 may further include: and the communication module is used for communicating the PAD of the chip to be designed and the bonding fingers to be designed when detecting that the chip to be designed and the bonding fingers to be designed are positioned on the same layer and the coordinate of the PAD of the chip to be designed and the coordinate of the center of each bonding finger to be designed are positioned in a preset range.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
An embodiment of the present application further provides a terminal device, and referring to fig. 4, the terminal device 500 may include: at least one processor 510, a memory 520, and a computer program stored in the memory 520 and executable on the at least one processor 510, the processor 510, when executing the computer program, implementing the steps of any of the various method embodiments described above, such as the steps 101 to 103 in the embodiment shown in fig. 2. Alternatively, the processor 510, when executing the computer program, implements the functions of the modules/units in the above-described device embodiments, such as the functions of the modules 201 to 203 shown in fig. 3.
Illustratively, the computer program may be divided into one or more modules/units, which are stored in the memory 520 and executed by the processor 510 to accomplish the present application. The one or more modules/units may be a series of computer program segments capable of performing specific functions, which are used to describe the execution of the computer program in the terminal device 500.
Those skilled in the art will appreciate that fig. 4 is merely an example of a terminal device and is not limiting and may include more or fewer components than shown, or some components may be combined, or different components such as input output devices, network access devices, buses, etc.
The Processor 510 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 520 may be an internal storage unit of the terminal device, or may be an external storage device of the terminal device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. The memory 520 is used for storing the computer programs and other programs and data required by the terminal device. The memory 520 may also be used to temporarily store data that has been output or is to be output.
The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.
The integrated circuit wiring method provided by the embodiment of the application can be applied to terminal equipment such as a computer, a tablet computer, a notebook computer, a netbook, a Personal Digital Assistant (PDA), a mobile phone and the like, and the embodiment of the application does not limit the specific type of the terminal equipment.
The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program can implement the steps in the various embodiments of the integrated circuit wiring method described above.
The embodiment of the present application provides a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the steps in the above-mentioned integrated circuit wiring method when executed.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/terminal apparatus, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other ways. For example, the above-described apparatus/network device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. An integrated circuit routing method, comprising:
receiving an integrated circuit wiring instruction, wherein the integrated circuit wiring instruction comprises chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information; the chip PAD position information and the bonding finger position information meet the following conditions: the coordinate of the PAD of the chip to be designed is consistent with the coordinate of the center of each bonding finger to be designed;
responding to the integrated circuit wiring instruction, and setting a chip to be designed and a bonding finger to be designed in a first layer based on the chip PAD position information and the bonding finger position information so as to realize the communication between the chip PAD to be designed and the bonding finger to be designed;
and carrying out wiring based on the connected PAD of the chip to be designed or each bonding finger to be designed.
2. The integrated circuit wiring method according to claim 1, wherein the setting of the chip to be designed and the bonding finger to be designed in the first layer based on the chip PAD position information and the bonding finger position information comprises:
generating a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information;
and adjusting a chip to be designed and a bonding finger to be designed into the first layer.
3. The integrated circuit wiring method of claim 1, wherein the setting of a chip to be designed and a bonding finger to be designed in the same layer based on the chip PAD position information and the bonding finger position information comprises:
and jumping to the first layer, and generating a chip to be designed and a bonding finger to be designed based on the chip PAD position information and the bonding finger position information.
4. The integrated circuit routing method of claim 2 or 3, wherein the integrated circuit routing instructions further comprise chip parameter information and bond finger parameter information;
the generating of the chip to be designed and the bonding finger to be designed includes:
and generating a chip to be designed according to the chip parameter information, and generating a bonding finger to be designed according to the bonding finger parameter information.
5. The integrated circuit routing method of claim 1, wherein after said receiving an integrated circuit routing instruction, the method further comprises: responding to the integrated circuit wiring instruction, and determining a first position of a chip PAD to be designed in a preset area based on the chip PAD position information;
setting the chip to be designed based on the chip PAD position information, comprising: and setting a chip to be designed into the first layer based on the position information of the chip PAD, so that the chip PAD to be designed is located at the first position.
6. The integrated circuit routing method of claim 1, wherein after said receiving an integrated circuit routing instruction, the method further comprises: responding to the integrated circuit wiring instruction, and determining a second position of each bonding finger to be designed in a preset area based on the bonding finger position information;
setting each bonding finger to be designed based on the bonding finger position information, including: and setting each bonding finger to be designed into the first image layer based on the bonding finger position information, so that the center of the bonding finger to be designed is located at the second position.
7. The integrated circuit routing method of claim 1, further comprising:
and when the chip to be designed and the bonding to be designed are detected to be positioned on the same layer, and the coordinate of the PAD of the chip to be designed and the coordinate of the center of each bonding finger to be designed are positioned in a preset range, communicating the PAD of the chip to be designed and the bonding finger to be designed.
8. An integrated circuit routing device, comprising:
the integrated circuit wiring instruction comprises chip PAD position information and bonding finger position information, the number of bonding fingers to be designed is multiple, and each bonding finger to be designed corresponds to one bonding finger position information; the chip PAD position information and the bonding finger position information meet the following conditions: the coordinate of the PAD of the chip to be designed is consistent with the coordinate of the center of each bonding finger to be designed;
the instruction response module is used for responding to the integrated circuit wiring instruction, and setting a chip to be designed and a bonding finger to be designed in a first layer based on the chip PAD position information and the bonding finger position information so as to realize the communication between the chip PAD to be designed and the bonding finger to be designed;
and the wiring module is used for carrying out wiring based on the connected PAD of the chip to be designed or each bonding finger to be designed.
9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111439922.9A CN114141765A (en) | 2021-11-30 | 2021-11-30 | Integrated circuit wiring method and device and terminal equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111439922.9A CN114141765A (en) | 2021-11-30 | 2021-11-30 | Integrated circuit wiring method and device and terminal equipment |
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| Publication Number | Publication Date |
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| CN114141765A true CN114141765A (en) | 2022-03-04 |
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| CN202111439922.9A Pending CN114141765A (en) | 2021-11-30 | 2021-11-30 | Integrated circuit wiring method and device and terminal equipment |
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| JP2001237317A (en) * | 2000-02-22 | 2001-08-31 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device, its designing method, and computer-readable recording medium recording i/o cell library |
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