CN115547965A - 智能电源模块 - Google Patents

智能电源模块 Download PDF

Info

Publication number
CN115547965A
CN115547965A CN202110727180.3A CN202110727180A CN115547965A CN 115547965 A CN115547965 A CN 115547965A CN 202110727180 A CN202110727180 A CN 202110727180A CN 115547965 A CN115547965 A CN 115547965A
Authority
CN
China
Prior art keywords
power module
intelligent power
chip
processing chips
bridge chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110727180.3A
Other languages
English (en)
Inventor
林容生
黄志丰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Richtek Technology Corp
Original Assignee
Richtek Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Richtek Technology Corp filed Critical Richtek Technology Corp
Priority to CN202110727180.3A priority Critical patent/CN115547965A/zh
Publication of CN115547965A publication Critical patent/CN115547965A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提出一种智能电源模块，其包含：一导线架；多个处理芯片，设置于导线架上；至少一桥接芯片，用于信号连接多个处理芯片之间；以及一封装结构，以封装导线架、处理芯片以及至少一桥接芯片。

Description

智能电源模块
技术领域
本发明涉及一种智能电源模块，特别是指一种通过桥接芯片用以信号连接各处理芯片的智能电源模块。
背景技术
背景技术中，智能电源模块需处理复杂的信号接线，例如图1的智能电源模块10的驱动芯片110与功率芯片115，需与周围导线架120的接点以及其他芯片，需要大空间的封装结构130，才够容置这些元件。智能电源模块10受限于导线架120的结构，无法提供复杂的信号联机(例如一个驱动芯片110搭配两个功率芯片115)。图2中智能电源模块20，包含设置微处理器220的一印刷电路板210，微处理器220所需的联机较多，需搭配印刷电路板210以提供多种不同信号线路，其线路连接选择多于图1的智能电源模块10。其中，智能电源模块20内需预留空间给印刷电路板210，也需预留空间给印刷电路板210的固定支架215，如此智能电源模块20的封装结构240尺寸十分庞大。此外，因印刷电路板210的生产技术限制，印刷电路板210上焊线W数量多且分散。因此，除了印刷电路板210、固定支架215外，智能电源模块20内更需提供空间给分散设置的焊线W(例如连接印刷电路板210、功率芯片230等)。此外，印刷电路板210的相关工艺，也非封装工艺的标准步骤，需与不同厂商、治具、工艺搭配，其复杂程度增加许多。
如此，背景技术中各种智能电源模块所需体积较大，其工艺复杂，生产质量难控制。如何使智能电源模块体积缩小、简化其工艺、提升生产质量，是很重要的课题。
发明内容
就其中一个观点言，本发明提供了一种智能电源模块，以解决前述的困扰，其具有缩小体积、工艺简单、焊线分布集中且理线布局容易、生产质量易控制等优点。此智能电源模块包含：一导线架(Lead frame)；多个处理芯片，设置于导线架上；至少一桥接芯片(Bridge die)，用于信号连接处理芯片；以及一封装结构，以封装导线架、处理芯片以及桥接芯片。
前述的桥接芯片，可用于提供处理芯片间多个通信线路，提供线路桥接的功能。桥接芯片内的线路，不提供运算功能，即无主动处理信号的功能。本发明的一些实施例中，在智能电源模块中的封装结构内，因采用桥接芯片，可不包含印刷电路板。
一实施例中，多个处理芯片可依搭配的桥接芯片进行信号连接组合。
一实施例中，桥接芯片的应用，可大幅地集中芯片间焊线的布局以及降低理线布局的混乱状态。如此，本发明所使用的驱动芯片，可不限于单相栅极驱动集成电路，而采用一多相栅极驱动集成电路。
一实施例中，桥接芯片可通过多个焊线以信号连接多个处理芯片。相较于背景技术中杂乱的焊线理线布局，本发明中经由桥接芯片的焊线理线布局集中许多，焊线的理线布局复杂度下降。又一实施例中，封装结构包覆的导线架的部分中包含多个内接点，内接点通过焊线以连接处理芯片、桥接芯片、或导线架。此外，除了焊线以外，桥接芯片也可通过多个硅信道以信号连接处理芯片。
导线架于该封装结构外的部分，具有多个外接点，用以传递芯片与智能电源模块外部间的信号。
以下通过具体实施例详加说明，会更容易了解本发明的目的、技术内容、特点及其所实现的效果。
附图说明
图1、2显示背景技术中智能电源模块的示意图。
图3显示根据本发明的智能电源模块的示意图。
图中符号说明
10，20，30：智能电源模块
110：驱动芯片
115：功率芯片
120：导线架
130：封装结构
210：印刷电路板
215：固定支架
220：微处理器
230：功率芯片
240：封装结构
310：导线架
312：内接点
314：外接点
320：微处理器
325：驱动芯片
327：功率芯片
330：桥接芯片
340：封装结构
C：焊线布线集中区
W：焊线
具体实施方式
本发明中的附图均属示意，主要意在表示各电路组成部分间的相互关系，至于形状与尺寸则并未依照比例绘制。
就其中一个观点言，图3中显示本发明的一种智能电源模块30，具有体积小、工艺简单、焊线W分布集中且理线布局容易等优点。其中，智能电源模块30包含：一导线架310(Lead frame)；多个处理芯片320、325、327(图3显示多个处理芯片，若需要，智能电源模块也可仅包含两个处理芯片)，设置于导线架310上；至少一桥接芯片330(Bridge die)，用于信号连接其中的处理芯片320、325、327；以及一封装结构340，封装结构340封装导线架310、处理芯片320以及桥接芯片330。重要地，图3仅用于举例说明，而非限制本发明的技术内容。其中各实施例，请参照其中的说明，而不必限制于图3中绘示的各元件关系。
前述的桥接芯片330，可为半导体工艺所制作的芯片，其中可具有单层或多层电路的线路。单层或多层电路可用于提供处理芯片320、325、327间多个通信线路，即作为线路桥接之用，如此可省略、简化或取代背景技术中智能电源模块的印刷电路板，提升智能电源模块内空间使用效率以及焊线W连接的理线布局。桥接芯片330内的线路，不提供运算功能，即无主动处理信号的功能，仅提供连接与传递信号。换言之，本发明的一些实施例中，在智能电源模块330中采用桥接芯片330，虽省略印刷电路板，却具有较好的空间使用效率以及理线效果。
前述的实施例中，智能电源模块30不需要容置印刷电路板，可进一步省略容置印刷电路板的固定支架的庞大空间、以及减少散布各处的焊线W所需的空间等，如此可大幅降低智能电源模块30的封装尺寸。
一实施例中，处理芯片的组合，可依主控制芯片与搭配的功能芯片进行信号连接组合。例如，主控制芯片为微处理器(MCU)，搭配的功能芯片为驱动芯片、功率芯片的组合。又例如，参照图3，主控制芯片为微处理器320与驱动芯片325，搭配的功能芯片为功率芯片327。处理芯片的组合，端视需要而定，也可为其他处理芯片的组合，无需受限于图3中所示的元件或元件数量。
一实施例中，处理芯片也可包含不同的半导体工艺，包含：绝缘栅双极晶体管(IGBT)、金属氧化物半导体场效晶体管(MOSFET)、或碳化硅(SiC)工艺等。若需要，任何适用于本发明半导体的设计方式，都可应用于本发明的智能电源模块。
参照图3，本发明中桥接芯片330的应用，可大幅地提升芯片间焊线W的理线布局简易度。若需要，更可以降低所需焊线W的数量。一实施例中，本发明所使用的驱动芯片325，可不限于单相栅极驱动集成电路，也可根据合并多个单相栅极驱动集成电路的方式，采用一多相栅极驱动集成电路，例如三相栅极驱动集成电路(Three phase gate driver IC)。如此的芯片功能合并，可降低驱动芯片325所需空间，并通过桥接芯片330集中焊线W的理线布局，进一步降低智能电源模块30的封装尺寸。或者，与背景技术相比，相同的封装尺寸中，本发明的智能电源模块30可具有更多的功能。此外，桥接芯片330中单层或多层集成电路，通过焊垫以及用于信号连接焊垫的焊线W，与处理芯片320、325、327或导线架310进行信号连接。
一实施例中，因桥接芯片330的使用，使搭配功率芯片327的驱动芯片325数量减少，提升智能电源模块30内部的空间使用率。例如，背景技术的图1中三个驱动芯片110搭配六组功率芯片115，而本发明的一个驱动芯片325搭配六组功率芯片327，如此可大幅提高空间使用率。然而，搭配功率芯片327的驱动芯片，可不限于图3中所示，可依需要而改变其设计或数量。
参照图3，一些实施例中，桥接芯片330可通过多个焊线W以信号连接多个处理芯片，使焊线W集中在桥接芯片330附近(例如图3中焊线布线集中区C)。相较于背景技术中焊线W理线布局的杂乱，本发明中经由桥接芯片330使焊线W的理线布局集中许多，焊线W的理线布局也随之简单许多。
一实施例中，封装结构340包覆的导线架310的部分中包含多个内接点312，内接点312通过焊线W以连接处理芯片320、325、327或桥接芯片330。一实施例中，除了焊线W以外，桥接芯片330也可选择通过硅信道以信号连接处理芯片320、325、或327，如此可进一步缩减焊线W的数量。前述的内接点312，导线架310于封装结构外，可具有多个外接点314。处理芯片320通过内接点312与外接点314，与智能电源模块30外进行信号传递。
以上已针对实施例来说明本发明，但以上所述，仅为使本领域技术人员易于了解本发明的内容，并非用来限定本发明的权利范围。在本发明的相同精神下，本领域技术人员可以想到各种等效变化，例如芯片、内外接点、或焊线的数量、相对位置与设计。本发明的范围应涵盖上述及其他所有等效变化。

Claims (10)

1.一种智能电源模块，其特征在于，包含：
一导线架；
多个处理芯片，设置于该导线架上；
至少一桥接芯片，用于信号连接该些处理芯片之间；以及
一封装结构，以封装该导线架、该些处理芯片以及该至少一桥接芯片。
2.如权利要求1所述的智能电源模块，其中，该桥接芯片具有多层的电路结构，其包含该些处理芯片间的多个通信线路。
3.如权利要求1所述的智能电源模块，其中，该些处理芯片不直接信号连接于一印刷电路板上。
4.如权利要求1所述的智能电源模块，其中，该些处理芯片包含微处理器、驱动芯片、功率芯片的组合。
5.如权利要求4所述的智能电源模块，其中，该驱动芯片包含一三相栅极驱动集成电路。
6.如权利要求1所述的智能电源模块，其中，该桥接芯片通过多个焊线以信号连接该些处理芯片与该导线架。
7.如权利要求6所述的智能电源模块，其中，该封装结构包覆的该导线架的部分中包含多个内接点，该些处理芯片或该桥接芯片通过至少一该焊线以信号连接该些内接点中的至少其一。
8.如权利要求1所述的智能电源模块，其中，该些处理芯片的半导体工艺包含：绝缘栅双极晶体管、金属氧化物半导体场效晶体管、或碳化硅工艺。
9.如权利要求1所述的智能电源模块，其中，该导线架于该封装结构外的部分，具有多个外接点，该些处理芯片通过该些外接点以信号连接至该智能电源模块外。
10.如权利要求1所述的智能电源模块，其中，该至少一桥接芯片包含半导体工艺所制作的单层或多层电路，该桥接芯片中包含焊垫，该智能电源模块包含信号连接该焊垫与该些处理芯片的焊线。
CN202110727180.3A 2021-06-29 2021-06-29 智能电源模块 Pending CN115547965A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110727180.3A CN115547965A (zh) 2021-06-29 2021-06-29 智能电源模块

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110727180.3A CN115547965A (zh) 2021-06-29 2021-06-29 智能电源模块

Publications (1)

Publication Number Publication Date
CN115547965A true CN115547965A (zh) 2022-12-30

Family

ID=84705783

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110727180.3A Pending CN115547965A (zh) 2021-06-29 2021-06-29 智能电源模块

Country Status (1)

Country Link
CN (1) CN115547965A (zh)

Similar Documents

Publication Publication Date Title
US8294256B2 (en) Chip package structure and method of making the same
USRE41869E1 (en) Semiconductor device
US8796831B2 (en) Complex semiconductor packages and methods of fabricating the same
US8680661B2 (en) Direct contact package for power transistors
US20140061885A1 (en) Power Quad Flat No-Lead (PQFN) Package
US7551455B2 (en) Package structure
US20140367846A1 (en) Power semiconductor device
US20120241934A1 (en) Semiconductor apparatus and method for manufacturing the same
US8575736B2 (en) Direct contact flip chip package with power transistors
US20140210061A1 (en) Chip arrangement and chip package
US20120292754A1 (en) Common Drain Exposed Conductive Clip for High Power Semiconductor Packages
JP6290758B2 (ja) 半導体装置
KR20120105920A (ko) 반도체 패키지
US20180301398A1 (en) SMD Package
TWI755338B (zh) 智能電源模組
CN115547965A (zh) 智能电源模块
US7808088B2 (en) Semiconductor device with improved high current performance
CN101404271B (zh) 音频功率放大器封装结构
US10892210B2 (en) Package structures
US20090091889A1 (en) Power electronic module having improved heat dissipation capability
EP4123699A1 (en) A semiconductor device and a method of manufacturing of a semiconductor device
CN202564281U (zh) 半导体模块
JP2012084817A (ja) 半導体装置
CN117153835A (zh) 半导体装置
JPH1174302A (ja) 樹脂封止型半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination