CN115411010A - 在运行中具有改善的性能并且在功率芯片布置中具有改善的灵活性的半导体器件 - Google Patents

在运行中具有改善的性能并且在功率芯片布置中具有改善的灵活性的半导体器件 Download PDF

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Publication number
CN115411010A
CN115411010A CN202210585079.3A CN202210585079A CN115411010A CN 115411010 A CN115411010 A CN 115411010A CN 202210585079 A CN202210585079 A CN 202210585079A CN 115411010 A CN115411010 A CN 115411010A
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metal layer
semiconductor device
upper metal
interposer
insulating
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CN202210585079.3A
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English (en)
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E·菲尔古特
A·毛德
S·福斯
M·格鲁贝尔
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本公开提供一种在运行中具有改善的性能并且在功率芯片布置中具有改善的灵活性的半导体器件。该半导体器件包括：绝缘内插器，所述绝缘内插器包括设置于第一上金属层和第二下金属层之间的绝缘层；附接到第一上金属层的至少一个半导体晶体管管芯，所述半导体晶体管管芯包括第一主面和与第一主面相反的第二主面、以及设置于第一主面上并且电连接到绝缘内插器的第一金属层的漏极或集电极焊盘、设置于第二主面上的源极或发射电极焊盘、以及设置于所述第二主面上的栅电极焊盘；连接到所述绝缘内插器的引线框架，所述引线框架包括多个引线，其中，第一引线与所述绝缘内插器的所述第一上金属层连接，第二引线通过至少一个第一电连接器与所述源极电极焊盘连接。

Description

在运行中具有改善的性能并且在功率芯片布置中具有改善的 灵活性的半导体器件
技术领域
本公开涉及一种半导体器件，所述半导体器件包括绝缘内插器(interposer)衬底、附着到绝缘内插器衬底的至少一个半导体管芯、以及连接到绝缘内插器的引线框架。具体而言，本公开涉及在散热、安全隔离方面具有改善的性质、且在功率芯片布置方面具有高度灵活性的半导体功率器件。
背景技术
功率密度增大是功率半导体市场之内的主要趋势。除了其他方面之外，热沉对于功率半导体器件而言非常重要，因为器件在运行期间会消耗功率，并且还因为器件必须要在其中运行的环境。通常，改善的热沉允许功率半导体器件以更高功率密度运行。
另一个重要方面是，与诸如逻辑或存储器器件的其他电子半导体器件相比，功率器件被设计成在相对高的电压，典型为500V甚至更高电压下运行。在常规封装的功率半导体器件中，封装的后侧可能会在正常运行下受到这些电压的作用。因此，同样非常重要的是确保功率器件和后方热沉之间的良好电绝缘。
现有功率器件的再一个问题是布置功率器件和/或其接触焊盘缺乏灵活性，这可能导致从负载电流路径到控制电流路径的不希望有的耦合。
出于这些和其他原因，存在对本公开的需求。
发明内容
本公开的第一方面涉及一种半导体器件，包括：
-绝缘内插器，所述绝缘内插器包括设置于下金属层和第一上金属层之间的绝缘层；
-附接到所述第一上金属层的至少一个半导体晶体管管芯，所述半导体晶体管管芯包括第一主面和与所述第一主面相反的第二主面、以及设置于所述第一主面上并且电连接到所述绝缘内插器的第一上金属层的漏极或集电极焊盘、设置于所述第二主面上的源极或发射电极焊盘、以及设置于所述第二主面上的栅电极焊盘；
-连接到所述绝缘内插器的引线框架，所述引线框架包括多个引线，其中，第一引线与所述绝缘内插器的所述第一上金属层连接，并且第二引线与所述源极电极焊盘连接，
其特征在于，
所述绝缘内插器包括第二上金属层，并且所述引线框架包括第三引线，所述第三引线与所述第二上金属层连接，并且其中，
第二电连接器连接于所述栅电极焊盘和所述第三上金属层之间，使其在基本正交于所述第一电连接器的延伸方向的方向上延伸。
本公开的第二方面涉及一种半导体器件，包括：
-绝缘内插器，所述绝缘内插器包括设置于下金属层和第一上金属层之间的绝缘层；
-附接到所述第一上金属层的至少一个半导体晶体管管芯，所述半导体晶体管管芯包括第一主面和与所述第一主面相反的第二主面、以及设置于所述第一主面上并且电连接到所述绝缘内插器的第一上金属层的漏极或集电极焊盘、设置于所述第二主面上的源极或发射电极焊盘、以及设置于所述第二主面上的栅电极焊盘；
-连接到所述绝缘内插器的引线框架，所述引线框架包括多个引线，其中，第一引线与所述绝缘内插器的所述第一上金属层连接，并且第二引线与所述源极电极焊盘连接，
其中，所述第一引线被分成两个部分，其中，第一部分与前端部分连接，并且第二部分与所述绝缘内插器的所述第一上金属层的后端部分连接。
本公开的第三方面涉及一种半导体器件，包括：
-绝缘内插器，所述绝缘内插器包括设置于下金属层和第一上金属层之间的绝缘层；
-附接到所述第一上金属层的至少一个半导体晶体管管芯，所述半导体晶体管管芯包括第一主面和与所述第一主面相反的第二主面、以及设置于所述第一主面上并且电连接到所述绝缘内插器的第一上金属层的漏极或集电极焊盘、设置于所述第二主面上的源极或发射电极焊盘、以及设置于所述第二主面上的栅电极焊盘；
-连接到所述绝缘内插器的引线框架，所述引线框架包括多个引线，其中，第一引线与所述绝缘内插器的所述第一上金属层连接，并且第二引线与所述源极电极焊盘连接，
其中，所述第一上金属层的面积小于所述绝缘内插器的所述下金属层的面积。
本公开的第四方面涉及一种半导体器件，包括：
-绝缘内插器衬底，所述绝缘内插器衬底包括设置于下金属层和第一上金属层之间的绝缘层；
-附接到所述第一上金属层的至少一个半导体晶体管管芯，所述半导体晶体管管芯包括第一主面和与所述第一主面相反的第二主面、以及设置于所述第一主面上并且电连接到所述绝缘内插器的第一上金属层的漏极或集电极焊盘、设置于所述第二主面上的源极或发射电极焊盘、以及设置于所述第二主面上的栅电极焊盘；
-连接到所述绝缘内插器的引线框架，所述引线框架包括多个引线，其中，第一引线与所述绝缘内插器衬底的所述第一上金属层连接，并且第二引线与所述源极电极焊盘连接；
其中，所述内插器包括另一金属层，所述另一金属层与所述半导体管芯的所述源极焊盘和所述引线框架的所述第二引线连接。
本公开的第五方面涉及一种半导体器件，包括：
-绝缘内插器衬底，所述绝缘内插器衬底包括设置于下金属层和第一上金属层之间的绝缘层；
-附接到所述第一上金属层的至少一个半导体晶体管管芯，所述半导体晶体管管芯包括第一主面和与所述第一主面相反的第二主面、以及设置于所述第一主面上并且电连接到所述绝缘内插器的第一上金属层的漏极或集电极焊盘、设置于所述第二主面上的源极或发射电极焊盘、以及设置于所述第二主面上的栅电极焊盘；
-连接到所述绝缘内插器的引线框架，所述引线框架包括多个引线，其中，第一引线与所述绝缘内插器衬底的所述第一上金属层连接，并且第二引线与所述源极电极焊盘连接；
其中，所述绝缘内插器包括条状另一上金属层，所述条状另一上金属层在所述第一上金属层旁边并且在朝向所述引线框架的方向上横向延伸，并且与所述第二引线连接。
本公开的第六方面涉及一种半导体器件，包括：
-绝缘内插器衬底，所述绝缘内插器衬底包括设置于下金属层和第一上金属层之间的绝缘层；
-附接到所述第一上金属层的至少一个半导体晶体管管芯，所述半导体晶体管管芯包括第一主面和与所述第一主面相反的第二主面、以及设置于所述第一主面上并且电连接到所述绝缘内插器的第一上金属层的漏极或集电极焊盘、设置于所述第二主面上的源极或发射电极焊盘、以及设置于所述第二主面上的栅电极焊盘；
-连接到所述绝缘内插器的引线框架，所述引线框架包括多个引线，其中，第一引线与所述绝缘内插器衬底的所述第二上金属层连接，并且第二引线与所述源极电极焊盘连接；
其中，所述第一下金属层包括在所述内插器的前端侧减小至少10％或至少20％或至少30％的量的面积。
附图说明
附图被包括在其中以提供对各实施例的进一步理解，并被并入且构成本说明书的部分。附图示出了各实施例，并与说明书一起用以解释各实施例的原理。其他实施例和各实施例的期望优点的很多优点将容易理解，因为参考以下具体实施方式，它们变得更好理解。
附图的元件并不必然彼此相对成比例。类似附图标记指示对应的类似部分。
图1A和图1B在从上方看的视图(A)和透视图(B)中示出了根据第一方面的半导体器件的示例。
图2A到图2C在透视图(A)、从另一观察方向看的另一透视图(B)和截面侧视图(C)中示出了根据第二方面的半导体器件的示例。
图3A和图3B在从上方看的透视图(A)和从下方看的透视图(B)中示出了根据第三方面的半导体器件的示例。
图4A和图4B在具有连接源极焊盘的键合引线(A)和具有连接源极焊盘的夹具(B)的透视图中示出了包括与源极/感测焊盘连接的另一金属层的半导体器件的示例。
图5示出了包括围绕第一金属层的另一金属层的半导体器件的示例。
图6A到图6C在具有连接于源极焊盘与角的部分之间和角的另一部分与第二引线之间的键合引线(A)、连接于源极焊盘与角的部分之间的键合引线和连接于角的另一部分与第二引线之间的夹具(B)、以及连接于源极焊盘与角的部分之间的夹具和连接于角的另一部分与第二引线之间的夹具(C)的透视图中示出了根据第四方面的半导体器件的示例。
图7A和图7B在透视图(A)和从另一观察方向看的另一透视图(B)中示出了根据第五方面的半导体器件的示例。
图8A到图8C在透视图中示出了半导体器件的不同示例，所有所示的器件都包括连接于绝缘内插器的金属层之间的电器件。
图9A和图9B在从下方看的具有正常尺寸的第一下金属层的透视图(A)以及从下方看的具有减小的面积的第一下金属层的透视图(B)中示出了根据第六方面的半导体器件的示例。
具体实施方式
在以下具体实施方式中将引用附图，附图形成其一部分，并且在附图中以举例方式示出了可实践本公开的具体实施例。就这一点而言，方向性术语，例如“顶部”、“底部”、“前”、“后”、“首”、“尾”等，是参考所描述附图的取向使用的。因为实施例的部件可以定位成若干不同取向，所以方向性术语用于例示的目的，而非进行限制。应当理解，在不背离本公开的范围的情况下，可以采用其他实施例，并且可以做出结构和逻辑上的改变。因此，以下详细描述不应该被理解为限制性的意义，并且本公开的范围仅由所附权利要求界定。
要理解的是，本文描述的各示范性实施例的特征可以彼此组合，除非具体做出其他表述。相同的附图标记是指相同或相似的部件。
如本说明书所用，术语“键合”、“附接”、“连接”、“耦合”和/或“电连接/电耦合”并非意在表示元件或层必须直接接触在一起；可以分别在“键合”、“附接”、“连接”、“耦合”和/或“电连接/电耦合”的元件之间提供居间元件或层。然而，根据本公开，任选地，上述术语也可以具有元件或层直接一起接触的具体含义，即，在“键合”、“附接”、“连接”、“耦合”和/或“电连接/电耦合”的元件之间未分别提供居间元件或层。
此外，结合形成于或位于表面“上方”的部分、元件或材料层使用的词语“上方”可以在此用于表示该部件、元件或材料层可以间接位于(例如，放置、形成、沉积于等)所暗示表面“上”，其中，在所暗示表面和该部分、元件或材料层之间布置有一个或多个额外部分、元件或层。然而，结合形成于或位于表面“上方”的部分、元件或材料层使用的词语“上方”任选地也可以具有如下具体含义：该部分、元件或材料层直接位于(例如，放置、形成、沉积于等)所暗示表面的“上”，例如，直接接触所暗示表面。
图1A和图1B在从上方(A)看的视图和透视图(B)中示出了根据第一方面的半导体器件的示例。
具体而言，图1A和图1B示出了半导体器件10，其包括绝缘内插器11，该绝缘内插器包括设置于下金属层(图1A和图1B中未示出)和第一上金属层11B之间的绝缘层11A。绝缘内插器11可以包括，例如，直接铜键合(DCB)、活性金属钎焊(AMB)或绝缘金属衬底(IMS)中的一种。
半导体器件10还包括附着到第一上金属层11B的两个半导体晶体管管芯12和16。半导体晶体管管芯12和16可以是相同类型，并且可以是例如IGBT管芯或MOSFET管芯。第一半导体晶体管管芯12包括第一主面和与第一主面相反的第二主面、以及设置于第一主面上并且电连接到绝缘内插器11的第一上金属层11B的漏极或集电极焊盘(未示出)、设置于第二主面上的源极或发射电极焊盘12A、以及设置于第二主面上的栅电极焊盘12B。第二晶体管管芯16可以与第一晶体管管芯12以类似方式具有电接触焊盘，在图1A和图1B中为了表现清晰，未向接触焊盘提供附图标记。
如图1A和图1B所示，可以提供多个源极焊盘12A以便提供相应的多个电流路径。可以以绝缘层(例如，聚酰亚胺层)中开口的形式提供源极焊盘12A。
采用以下方式将两个半导体晶体管管芯12和16彼此电连接，即，使它们的漏极接触焊盘两者都电连接到绝缘内插器11的第一金属层11B，并且它们的源极接触焊盘利用键合引线(或夹具，如将在以下进一步实施例中所见)直接彼此连接。两个半导体晶体管管芯12和16从而彼此并联电连接。
两个半导体晶体管管芯12和16可以包括任何半导体材料。具体而言，两个半导体晶体管管芯12和16可以包括SiC作为半导体材料，因为已经发现，由于更好的冷却条件，SiC晶体管管芯的效率随着晶体管管芯的尺寸减小而增大。两个小的SiC晶体管管芯比具有相同有源面积的一个大的SiC晶体管管芯工作效率更高。此外，更小的半导体管芯可以具有更好的良率，因此并联几个小的管芯可以比使用一个拥有与小管芯之和相同电流容量的大管芯更有成本效率。
半导体器件10还包括连接到绝缘内插器11的引线框架13，该引线框架13包括多个引线，其中，第一引线13.1与绝缘内插器11的第一上金属层11B连接，因此与两个半导体管芯12和16的公共漏极电极连接，并且第二引线13.2与源极电极焊盘12A连接，在图1A和图1B的实施例中利用多个相应的键合引线14与第一和第二晶体管管芯的多个源极焊盘连接。而且，可以将夹具用作电连接器，如将在以下进一步实施例中所见到的。
绝缘内插器11还包括第二上金属层11C，而引线框架13包括第三引线13.3，该第三引线通过键合引线18与第二上金属层11C连接，其中，键合引线15连接于栅电极焊盘12B和第二上金属层11C之间，使得键合引线15在基本正交于键合引线14的延伸方向的方向上延伸。“基本正交”可以尤其表示键合引线14和键合引线15的延伸方向之间的角度在从75°到105°，更具体地从80°到100°，更具体地从85°到95°的范围中。键合引线14和15的延伸方向之间的正交性具有重要的效果，即减少从键合引线14的负载电流路径到键合引线15的控制电流路径的电耦合。
键合引线14和15的延伸方向之间的正交性基本通过如下方式实现：以相对于第一金属层11B放置成横向关系的细长条层11C的形式布置第二金属层11C，使得可以直接从半导体管芯12向外布设键合引线15，以在栅极连接和源极/漏极负载电流连接之间生成更大距离。条层11C指向第三引线13.3，并且能够通过另一个键合引线18与第三引线13.3连接。
第二半导体晶体管管芯16的栅极焊盘可以通过与第一半导体管芯12的栅极焊盘相同的方式与第二金属层11C连接，即利用基本正交于键合引线14的键合引线连接，在图1A和图1B中为了表示清晰，未向键合引线提供附图标记。
第一半导体晶体管管芯12还包括源极/感测焊盘12C，并且引线框架包括第四引线13.4，其中，仅第二半导体晶体管管芯16的源极/感测焊盘利用键合引线连接到第四引线13.4。
图1B还示出了部分断裂的封装物17，封装物17可以通过模制技术(例如，转移模制、压缩模制)之一被施加。
封装物17可以包括常规模制化合物，例如树脂材料，尤其是环氧树脂材料。此外，封装物17可以在不同聚集体状态下，例如在液态形式下，作为球粒、或作为颗粒被施加。具体而言，封装物17的材料可以包括树脂，像填充有标准填充材料(例如球形和/或片形的SiO2)和/或填充有例如由Al2O3、BN、AlN、Si3N4、金刚石制成的导热颗粒或任何其他导热颗粒的环氧树脂材料。封装物17也可以由可电镀(plateable)的模制化合物制成。
图2A到图2C示出了根据第二方面的半导体器件的示例。
图2A到图2C示出了半导体器件20。应当指出，半导体器件20可以具有与图1A和图1B的半导体器件10类似的性质。具体而言，半导体器件20可以包括半导体器件10的特征的一些或全部，在图2A到图2C中利用与图1A和图1B中相同的附图标记指示这些特征。
半导体器件20在一个特征中与图1A和图1B的半导体器件10不同，即在引线框架23的设计方面。具体而言，半导体器件20的引线框架23包括分成两个部分的第一引线23.1，其中，第一部分23.1A与前端部分连接，并且第二部分23.1B与绝缘内插器11的第一金属层11B的后端部分连接。在图2A和图2C中，可以看出，在内插器外部，引线23.1是一体的，且在到达内插器之前短距离内，引线23.1被分成两个部分23.1A和23.1B。应当指出，在制造过程的稍晚时，例如，在模制工艺之后，将去除引线23.1、23.2和23.3之间的互连(这里未示出)，以避免对应电信号之间的短路。然后将第一部分23.1A降低到第一金属层11B，而第二部分23.1B保持在初始高度，并在到达图2C左手侧的第一金属层11B的后端部分之前降低到第一金属层11B。
引线框架的这种修改设计获得了内插器与引线框架的弹性或弹簧式连接。另一个优点是通过分裂第一引线实现的增大的电流承载容量。除了这种弹簧功能之外的另一个优点是引线框架下沉使得能够无需过多的模制溢料(mold-flash)而进行封装。通过采用膜辅助模制甚至能够进一步改善模制溢料程度。
图3A和图3B示出了根据第三方面的半导体器件的示例。
图3A和图3B示出了半导体器件30。应当指出，半导体器件30可以具有与图1A和图1B的半导体器件10类似的性质。具体而言，半导体器件30可以包括半导体器件10的特征的一些或全部，在图3A和图3B中利用与图1A和图1B中相同的附图标记指示这些特征。与图1A和图1B不同的是，内插器31不包括用于栅极布线的第二金属层11C。相反，栅极焊盘直接与第三引线13.3引线键合。
通常，并且因此在图1A和图1B以及图2A到图2C的先前示例中，对内插器的第一金属层的面积进行最大化，以允许实现最大管芯尺寸，并还实现更好的散热。不过，第一金属层还为热沉(其可能处于地电势)提供了额外的电容漏极，在每次开关循环都不得不对该电容充电。对于现有功率开关(即使已经是基于Si的)而言，这个电容也对总体开关损失具有显著贡献。例如，经由绝缘箔(CD,Heatsink～20pF)将TO-220封装中的当前CoolMOS器件(例如，CoolMOS C6,180mOhm,600V)附接到热沉会使截止损失增加～60％。截止损失的相对增大与半导体开关的输出电容和经由绝缘箔的电容之间的关系强相关。SiC-MOSFET具有更低的面比导通状态电阻(area-specific on-state resistance)，导致在相同额定导通状态电阻下更小的芯片面积，从而在相同导通状态电阻下有更低的输出电容，对于SiC-MOSFET而言，这种效应可能甚至更高。
因此，在图3A和图3B的实施例中，减小了前侧的漏极面积以减小耦合电容和开关损失。更具体而言，图3A和图3B示出了半导体器件30，其包括绝缘内插器31，该绝缘内插器31包括设置于第一上金属层31B和下金属层31C之间的绝缘层31A。如在图3A和图3B中可以看出的，第一金属层31B的面积小于金属层31C的面积。第一金属层31B的面积可以比金属层31C的面积小至少10％、或至少20％、或至少30％。在极端情况下，可以使第一金属层31B的面积非常小，使得可以恰好在其上放置两个半导体管芯12和16。
图4A和图4B示出了半导体器件的另一示例。
图4A示出了半导体器件40。应当指出，半导体器件40可以具有与图1A和图1B的半导体器件10类似的性质。具体而言，半导体器件40可以包括半导体器件10的特征的一些或全部，在图4A和图4B中利用与图1A和图1B中相同的附图标记指示这些特征。与图1A和图1B不同的是，可以使用例如图3A和图3B中的第一金属层面积减小的内插器。
根据图4A，绝缘内插器11还包括第三上金属层11D，其被配置为横向位于第一金属层11B和第二金属层11C旁边的条状层。键合引线46以与图1A和图1B中的键合引线15相似的方式(即，以使它在基本正交于键合引线14的延伸方向的方向上延伸的方式)连接于第二半导体管芯16的源极/感测焊盘和第三上金属层11D之间。
半导体器件40从而组合若干措施以进一步改善器件的功能性。首先像先前的实施例中那样，再次在内插器上进行栅极布线，以提供更大的电容CG_Ground来用于对栅极信号进行低通滤波，并且减小对振荡的敏感性。此外，提供了一种配置，其中，第三金属层11D被用作第二金属(栅极连接)层11C针对第一金属(漏极连接)层11B上的高dVDS/dt的静电屏蔽。由于第一金属层11B的面积减小(像在图3A和图3B的实施例中那样)，所以可以加大第一(漏极)层11B和第三(源极/感测)层11D之间的间隙，以获得更小的磁耦合，优选与第二(栅极)金属层11C和第三(源极/感测)金属层11D之间的小环路组合。
图4B中所示的半导体器件40采用带44(或夹具)来连接源极焊盘与第二引线13.2，而不是采用如图4A的实施例中的键合引线14。其他每项都可以如图4A的实施例中那样。
图5示出了包括围绕第一金属层的另一金属层的半导体器件的示例。
图5示出了半导体器件50。应当指出，半导体器件50可以具有与图3A和图3B的半导体器件30类似的性质。具体而言，半导体器件50可以包括半导体器件30的特征的一些或全部，在图5中利用与图3A和图3B中相同的附图标记指示这些特征。
除了图3A和图3B的实施例之外，半导体器件50包括另一金属层31D，其至少部分地围绕绝缘内插器31的第一金属层31B，该另一金属层31D利用电连接器54与第二引线13.3连接，该电连接器54可以是键合引线、夹具或带。另一个选项是将另一金属层31D与第四引线13.4连接。
在这一方面应当指出，图5的实施例具有关于电容耦合减小的优点，但对于弓度设计(bow engineering)或散热而言，第一层31B的金属面积减小也有缺点，这些缺点可以通过添加另一金属层31D并将其与第二引线13.2连接(即，连接到源极电势)来克服，在很多情况下，源极电势连接到地或另一个固定电势。应当指出，本文使用的术语“弓度设计”是指，如果内插器的上下侧上金属层的面积非常不同，在处理的特定步骤中内插器的较大弓度的方面。
图6A到图6C示出了根据第四方面的半导体器件的示例。
图6A到图6C示出了半导体器件60。应当指出，半导体器件60可以具有与图4A和图4B的半导体器件40类似的性质，尤其是关于在内插器61上提供金属层61C和61D方面，这些层与图4A和图4B的层11C和11D相当，并且用于连接内插器61上的栅极和源极/感测焊盘。
除此之外，内插器61包括与半导体管芯12和16的源极焊盘连接的另一金属层61E。
在内插器61上使用这样的另一金属层61E减小了负载路径中因为内插器第二(后)侧金属层上诱发的涡流造成的杂散电感。
具体而言，对于两个半导体管芯12和16而言，第一金属层61B可以包括凹陷部，其中，在第一金属层61B上的凹陷部的相对侧上设置两个半导体管芯12和16。另一金属层61E可以包括延伸到第一金属层61B的凹陷部中的部分。具体而言，另一金属层61E可以包括角的形状，该角的一个部分延伸到第一金属层61B中的凹陷部中。两个半导体管芯12和16然后可以利用键合引线62连接到角形另一金属层61E的一个部分。角形另一金属层61E的另一部分然后可以利用键合引线63连接到第二引线13.3。
图6B示出了半导体器件60的另一实施例，与图6A的实施例不同之处在于，使用带或夹具64将角形另一金属层61E的下部与第二引线13.3连接。
图6C示出了半导体器件60的另一个实施例，其与图6A和图6B的实施例不同之处在于，使用带或夹具65将源极焊盘与角形另一金属层61E连接。
图7A和图7B示出了根据第五方面的半导体器件的示例。
图7A和图7B示出了半导体器件70。应当指出，半导体器件70可以具有与图6A到图6C的半导体器件60类似的性质，尤其是关于在内插器71上提供金属层71C和71D方面，这些层与图6A到图6C的层61C和61D相当，并且用于连接内插器71上的栅极和源极/感测焊盘。
除此之外，内插器71包括通过键合引线(或带或夹具)与半导体管芯12和16的源极焊盘连接的条状另一金属层71E。该另一金属层71E沿着第一金属层71B的侧边缘并在朝向引线框架的方向上横向延伸，并且与第二引线连接。
器件运行时的第一金属层71B向半导体管芯12、16传导负载电流。负载电流形成围绕第一金属层71B的磁场。另一金属层71E形成负载电流的返回路径。于是，围绕另一金属层71E的磁场部分地补偿了围绕第一金属层71B的磁场。减小了突出穿过由金属层71C和71D形成的环路以向半导体管芯12、16的栅极提供控制信号的净磁场，使得负载电流对控制电路的干扰减小。
也可以进一步增大另一金属层71E和层71D之间的间隙，以减小到控制电路的磁耦合。
图8A到图8C示出了半导体器件的不同示例，所有所示的器件都包括连接于绝缘内插器的金属层之间的电器件。
图8A示出了半导体器件80，其与图7A和图7B中所示的半导体器件70相当。此外，半导体器件80包括连接于金属层71B和71E之间的电器件81。
图8B示出了半导体器件80，其与图5中所示的半导体器件50相当。此外，半导体器件80包括连接于金属层31B和31E之间的电器件82。
图8C示出了半导体器件80，其与图6C中所示的半导体器件60相当。此外，半导体器件80包括连接于金属层61B和61E之间的电器件83。
电器件81、82或83可以是抑制二极管、雪崩二极管或配置成在过电流或短路的情况下主动截止栅极的任何其他器件。
图9A和图9B在从下方看的具有正常尺寸的第一下金属层的透视图(A)以及从下方看的具有减小的面积的第一下金属层的透视图(B)中示出了根据第六方面的半导体器件的示例。
如在图9B中可以看出的，减小了第二金属层91C的面积，以便降低从引线到第二金属层的爬电电流的危险。利用封装物97填充所得的间隙。如还可以看出的，回缩在无源区域(即，引线框架到内插器前侧的连接的区域)下方进行，而不在功率半导体的下方以免影响到热阻。
回缩可以是内插器91的总长度在从第一引线13.1离开的方向上至少10％或至少20％或至少30％。此外，减小的金属层导致半导体管芯的漏极与热沉的电容耦合减小，因此，导致更低的开关损失，如图3A和图3B的描述中解释的那样。
此外，尽管可能已经相对于几种实施方式的仅一种公开了本公开实施例的特定特征或方面，但可以在对于任何给定或特定应用需要并有利的情况下，将这样的特征或方面与其他实施方式的一个或多个其他特征或方面组合。此外，在术语“包括”、“具有”或其变体用于具体实施方式中或权利要求的程度上，这样的术语意在为以类似于术语“包括”的方式而是包括性的。此外，应当理解，可以在离散电路、部分集成电路或完全集成电路或编程模块中实施本公开的实施例。而且，术语“示范性”仅仅表示示例，而非最佳或最优。还要认识到，出于理解简单容易的目的，本文绘示的特征和/或元件被例示以彼此相对具有特定尺度，而实际尺度可以与本文例示的显著不同。
尽管本文已经例示和描述了具体实施例，但本领域的普通技术人员将认识到，可以用多种替代和/或等价实施方式替代所示和所述的具体实施例而不脱离本公开的范围。本申请意在涵盖本文讨论的具体实施例的任何调整或变化。因此，意在使本公开仅受到权利要求及其等价体的限制。

Claims (14)

1.一种半导体器件(10)，包括：
-绝缘内插器(11)，所述绝缘内插器包括设置于下金属层和第一上金属层(11B)之间的绝缘层(11A)；
-附接到所述第一上金属层(11B)的至少一个半导体晶体管管芯(12)，所述半导体晶体管管芯(12)包括第一主面和与所述第一主面相反的第二主面、以及设置于所述第一主面上并且电连接到所述绝缘内插器(11)的所述第一上金属层(11B)的漏极或集电极焊盘、设置于所述第二主面上的源极或发射电极焊盘(12A)、以及设置于所述第二主面上的栅电极焊盘(12B)；
-连接到所述绝缘内插器(11)的引线框架(13)，所述引线框架(13)包括多个引线，其中，第一引线(13.1)与所述绝缘内插器(11)的所述第一上金属层(11B)连接，并且第二引线(13.2)与所述源极电极焊盘(12A)连接，
其特征在于，
所述绝缘内插器(11)包括第二上金属层(11C)，并且所述引线框架(13)包括第三引线(13.3)，所述第三引线(13.3)与所述第二上金属层(11C)连接，并且其中，
电连接器(15)连接于所述栅电极焊盘(12B)和所述第二上金属层(11C)之间，使得所述电连接器在基本正交于所述第一电连接器(14)的延伸方向的方向上延伸。
2.根据权利要求1所述的半导体器件(10)，其中，
所述第二上金属层(11C)在所述第一上金属层(11B)旁边并且在朝向所述引线框架(13)的方向上横向延伸，并且通过另一电连接器(17)连接到所述引线框架(13)的所述第三引线(13.3)。
3.根据权利要求1或2所述的半导体器件(10)，其中，
所述绝缘内插器(11)包括直接铜键合(DCB)、活性金属钎焊(AMB)或绝缘金属衬底(IMS)中的一种。
4.根据前述权利要求中的任一项所述的半导体器件(10)，其中，
所述半导体晶体管管芯(12)包括IGBT或MOSFET管芯。
5.根据前述权利要求中的任一项所述的半导体器件(10)，还包括：
第一半导体晶体管管芯(12)和第二半导体晶体管管芯(16)，所述第一半导体晶体管管芯(12)和第二半导体晶体管管芯(16)两者均附接到所述第一金属层(11B)，其中，所述第一半导体管芯和第二半导体管芯并联连接。
6.根据前述权利要求中的任一项所述的半导体器件(40)，还包括：
所述半导体管芯(16)包括源极/感测焊盘；
所述绝缘内插器(11)包括第三上金属层(11D)，其中，另一电连接器(46)连接于所述源极/感测焊盘和所述第三上金属层(11D)之间。
7.根据权利要求6所述的半导体器件(40)，其中，
所述第三上金属层(11D)设置于所述第一上金属层(11B)和所述第二上金属层(11C)之间。
8.根据前述权利要求中的任一项所述的半导体器件(20)，其中，
所述第一引线(23.1)被分成两个部分，其中，第一部分(23.1A)与所述绝缘内插器(11)的所述第一上金属层(11B)的前端部分连接，并且第二部分(23.1B)与所述绝缘内插器(11)的所述第一上金属层(11B)的后端部分连接。
9.根据前述权利要求中的任一项所述的半导体器件(30)，其中，
所述第一上金属层(31B)的面积小于所述绝缘内插器(31)的所述下金属层的面积。
10.根据权利要求9所述的半导体器件(50)，还包括：
另一金属层(31D)，所述另一金属层(31D)至少部分地围绕所述绝缘内插器(31)的所述第一上金属层(31B)，所述另一金属层(31D)与所述第二引线(13.2)或所述第四引线(13.4)连接。
11.根据前述权利要求中的任一项所述的半导体器件(60)，其中，
所述内插器(61)包括另一上金属层(61E)，所述另一上金属层(61E)与所述半导体管芯(12)的所述源极焊盘(12A)和所述引线框架(13)的所述第二引线(13.2)连接。
12.根据前述权利要求中的任一项所述的半导体器件(70)，其中，
所述绝缘内插器(71)包括条状另一上金属层(71E)，所述条状另一上金属层(71E)在所述第一上金属层(71B)旁边并且在朝向所述引线框架的方向上横向延伸，并且与所述第二引线连接。
13.根据权利要求12所述的半导体器件(80)，还包括：
连接于所述绝缘内插器的所述金属层之间的电器件(81，82，83)，所述电器件(81，82，83)是以下中的一个或多个：抑制二极管、雪崩二极管、或配置成在过电压、过电流或短路的情况下主动截止栅极的任何其他器件。
14.根据前述权利要求中的任一项所述的半导体器件(90)，其中，
所述内插器(91)的所述下金属层(91C)包括在所述内插器(91)的前端侧减小至少10％或至少20％或至少30％的量的面积。
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