CN209896058U - 功率半导体器件和封装件 - Google Patents

功率半导体器件和封装件 Download PDF

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CN209896058U
CN209896058U CN201920468185.7U CN201920468185U CN209896058U CN 209896058 U CN209896058 U CN 209896058U CN 201920468185 U CN201920468185 U CN 201920468185U CN 209896058 U CN209896058 U CN 209896058U
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die
metal layer
package
regions
semiconductor device
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C·G·斯特拉
A·米诺蒂
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STMicroelectronics SRL
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STMicroelectronics SRL
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Abstract

本公开的实施例提供了一种功率半导体器件和封装件。该功率半导体器件包括第一裸片和第二裸片，每个裸片包括钝化区域和多个导电接触区域，钝化区域包括多个突出电介质区域和多个窗口。相邻窗口由对应的突出电介质区域隔开，每个导电接触区域布置在对应的窗口内。表面安装型封装件容纳第一裸片和第二裸片。该封装件包括分别承载第一裸片和第二裸片的第一底部绝缘多层和第二底部绝缘多层。覆盖金属层布置在第一裸片和第二裸片的顶部，并且包括延伸到窗口中以与对应的导电接触区域电耦合的突出金属区域。此外，覆盖金属层形成介于突出金属区域之间以便覆盖对应的突出电介质区域的多个腔体。

Description

功率半导体器件和封装件
技术领域
本公开涉及一种功率半导体器件，其具有表面安装型封装件并且包括成对岛。
背景技术
众所周知，半导体器件广泛用于很多领域。例如，在功率转换领域，半导体器件被广泛使用，其在运行中受到高压或极高压偏置(即，具有高达1000-2000V的值)并且被可能迅速切换的电流穿过。
因此，需要用于制造对应封装件的特定解决方案，以便保证所需要的电绝缘以及连接到器件的端子的引线之间的足够的分离距离，以及确保向外充分的散热。
通常，参考功率器件来指示能够承受上述偏置电压和电流的半导体器件。
功率器件包括例如所谓的功率MOSFET，每个功率MOSFET设置在半导体材料(通常为硅)的裸片中，裸片具有承载漏极接触焊盘的第一主表面(后表面)以及与主表面相对的第二主表面(前表面)，第二主表面承载接触焊盘，特别是源极焊盘和栅极焊盘。
裸片固定到被称为“引线框架”的导电支撑件上，导电支撑件设有用于功率MOSFET的端子的外部连接的引线。特别地，通常通过将漏极焊盘接合到引线框架的支撑部分来将裸片固定到引线框架，该支撑部分还具有散热功能。引线通过接合线或夹具耦合到栅极焊盘和源极焊盘。由裸片和引线框架组成的整体被封装在大量树脂或其他绝缘封装材料中。
用于功率MOSFET的传统封装件通常竖直布置并且包括引脚，引脚形成对应引线并且从封装结构的单个底侧向下突出(其具有通常为平行六面体的形状)，用于电耦合到印刷电路板(PCB)。适当的散热器(通常是金属板)耦合到封装结构，封装结构也相对于印刷电路板竖直布置。
功率MOSFET器件广泛用于例如具有无桥型功率因数校正(PFC)的所谓的开关模式电源(SMPS)领域。特别地，功率MOSFET器件用于提供能够以电控方式中断交流电流的所谓的双向AC开关。在这方面，AC开关通常包括以背靠背模式连接的成对功率MOSFET器件，即通过将相应源极端子连接在一起。此外，形成AC开关的两个功率MOSFET器件是前面描述的类型；因此，它们是离散型的，并且它们中的每个具有竖直类型的相应封装件，具有对应竖直销。遗憾的是，尽管保证了最佳的散热和高水平的电绝缘，但是这些封装件特别笨重并且不能将两个功率MOSFET器件集成在一起。
实用新型内容
本公开的目的是提供一种功率半导体器件和封装件，以至少部分地解决现有技术中存在的上述问题。
本公开的实施例提供了一种功率半导体器件，其将至少部分克服现有技术的缺点。
根据本公开的一个实施例，一种功率半导体器件包括第一裸片和第二裸片，每个裸片包括钝化区域和多个导电接触区域，钝化区域包括多个突出电介质区域和多个窗口。相邻窗口由对应的突出电介质区域隔开，每个导电接触区域布置在对应的窗口内。该器件包括容纳第一裸片和第二裸片的表面安装型封装件。该封装件包括第一底部绝缘多层和第二底部绝缘多层，第一底部绝缘多层和第二底部绝缘多层分别承载第一裸片和第二裸片并且均包括相应顶部金属层、相应底部金属层和介于对应的顶部金属层与对应的底部金属层之间的相应中间绝缘层。覆盖金属层布置在第一裸片和第二裸片的顶部，并且包括延伸到窗口中以便与对应的导电接触区域电耦合的突出金属区域。此外，覆盖金属层形成介于突出金属区域之间以便覆盖对应的突出电介质区域的多个腔体。
在一个实施例中，所述功率半导体器件还包括顶部绝缘多层，所述顶部绝缘多层包括相应顶部金属层、所述覆盖金属层、以及介于所述相应顶部金属层与所述覆盖金属层之间的相应中间绝缘层。
在一个实施例中，所述功率半导体器件还包括由金属材料制成的第一支撑件和第二支撑件，所述第一支撑件和第二支撑件分别承载所述第一底部绝缘多层和所述第二底部绝缘多层。
在一个实施例中，所述封装件还包括：封装件涂层，其覆盖所述第一裸片和所述第二裸片以及所述第一底部绝缘多层和所述第二底部绝缘多层；以及第一引线，其包括从所述封装件涂层暴露的部分；并且其中所述覆盖金属层电耦合到所述第一引线。
在一个实施例中，所述封装件涂层覆盖所述第一支撑件和所述第二支撑件，并且其中所述第一支撑件和所述第二支撑件中的每个支撑件包括从所述封装件涂层暴露的相应部分。
在一个实施例中，所述封装件还包括第二引线和第三引线，所述第二引线和所述第三引线中的每个引线包括从所述封装件涂层暴露的相应部分，并且其中所述第一底部绝缘多层和所述第二底部绝缘多层的顶部金属层分别电耦合到所述第二引线和所述第三引线。
在一个实施例中，所述第一裸片和所述第二裸片中的每个裸片包括多个金属化线，每个金属化线涂覆有对应的突出电介质区域。
在一个实施例中，所述第一裸片和所述第二裸片分别包括第一晶体管和第二晶体管；以及所述第一裸片和所述第二裸片的所述金属化线是相应晶体管的栅极线；以及所述第一裸片和所述第二裸片的所述导电接触区域是相应晶体管的源极接触区域。
在一个实施例中，所述第一裸片和所述第二裸片中的每个裸片包括相应底部接触金属化部；以及所述第一裸片和所述第二裸片的所述底部接触金属化部分别电耦合到所述第一底部绝缘多层和所述第二底部绝缘多层的顶部金属层。
在一个实施例中，所述覆盖金属层在距所述第一裸片和所述第二裸片的钝化区域一距离处延伸。
根据本公开的另一方面，提供了一种功率半导体器件，包括：
第一裸片和第二裸片，所述第一裸片和所述第二裸片中的每个裸片具有第一表面和与所述第一表面相对的第二表面并且还包括在所述第一表面上的钝化区域和多个导电接触区域，所述钝化区域包括多个突出电介质区域和在相邻的突出电介质区域之间限定的多个窗口，所述多个导电接触区域中的每个导电接触区域布置在所述多个窗口中的对应的窗口内；以及
封装件，包含所述第一裸片和所述第二裸片，所述封装件包括：
第一底部绝缘多层和第二底部绝缘多层，所述第一裸片和所述第二裸片的所述第二表面分别位于所述第一底部绝缘多层和所述第二底部绝缘多层上，所述第一底部绝缘多层和所述第二底部绝缘多层中的每个底部绝缘多层包括相应顶部金属层、相应底部金属层和在所述顶部金属层与所述底金属层之间的相应中间绝缘层；以及
在所述第一裸片和所述第二裸片的所述第一表面上的覆盖金属层，所述覆盖金属层包括延伸到所述多个窗口中以将所述覆盖金属层电耦合到所述多个导电接触区域中的相应导电接触区域的突出金属区域，所述覆盖物金属层还包括介于所述突出金属区域之间的多个腔体，所述多个腔体中的每个腔体被定位成覆盖所述多个突出电介质区域中的对应的突出电介质区域。
在一个实施例中，所述封装件包括表面安装封装件。
在一个实施例中，所述功率半导体器件还包括在所述第一裸片和所述第二裸片的所述第一表面上的顶部绝缘多层，所述顶部绝缘多层包括顶部金属层、所述覆盖金属层和介于所述顶部金属层与所述覆盖金属层之间的中间绝缘层。
在一个实施例中，所述功率半导体器件还包括第一金属支撑件和第二金属支撑件，所述第一底部绝缘多层和所述第二底部绝缘多层分别位于所述第一金属支撑件和所述第二金属支撑件上。
在一个实施例中，所述封装件还包括：封装件涂层，覆盖所述第一裸片和所述第二裸片以及所述第一底部绝缘多层和所述第二底部绝缘多层；以及第一引线，电耦合到所述覆盖金属层，所述第一引线包括从所述封装件涂层暴露的部分。
在一个实施例中，所述封装件涂层还覆盖所述第一金属支撑件和第二金属支撑件，并且其中所述第一金属支撑件和第二金属支撑件中的每个金属支撑件包括从所述封装件涂层暴露的部分。
根据本公开的又一方面，提供了一种封装件，包括：
第一底部绝缘多层和第二底部绝缘多层，分别被配置为承载第一裸片和第二裸片，每个底部绝缘多层包括顶部金属层、底部金属层和位于所述顶部金属层与所述底部金属层之间的中间绝缘层；以及
覆盖金属层，布置在所述第一裸片和所述第二裸片的顶部，所述覆盖金属层包括突出金属区域，所述突出金属区域被配置为分别延伸到所述第一裸片和所述第二裸片上的第一钝化区域和第二钝化区域中的窗口中，所述第一钝化区域和所述第二钝化区域包括多个突出电介质区域，并且所述覆盖金属层被配置为电接触在所述窗口内的所述第一裸片和所述第二裸片上暴露的导电接触区域，所述覆盖金属层还包括位于所述突出金属区域之间的多个腔体，所述多个腔体中的每个腔体位于所述多个突出电介质区域中的对应的突出电介质区域之上。
在一个实施例中，所述封装件包括表面安装型封装件。
在一个实施例中，所述第一裸片和所述第二裸片中的每个裸片包括功率MOSFET器件。
在一个实施例中，所述封装件还包括：第一导电支撑件和第二导电支撑件，分别被配置为支撑所述第一底部绝缘多层和所述第二底部绝缘多层。
根据本公开的实施例能够提供多种有益效果。特别地，本实用新型的封装件在竖直方向上可以具有2-3mm的最大厚度。此外，该封装件提供了在两侧(顶部和底部)冷却的可能性。再次，顶部绝缘多层在桥式配置中的存在(即延伸以覆盖两个裸片)保证了相当大的热效率，降低了寄生封装电效应(特别是电感效应)并且降低了接触电阻。再次，与功率MOSFET的源极区域的连接不需要使用接线键合。
附图说明
为了更好地理解本公开，现在参考附图，仅通过非限制性示例描述其优选实施例，在附图中：
图1是本半导体器件的一个实施例的部分简化的示意性透视图，其中部分被移除；
图2是图1所示的器件的示意性截面图；
图3是图1和2所示的器件的裸片的示意性俯视平面图，其中部分被移除；
图4是图3所示的裸片的示意性透视图；
图5是本器件的另一实施例的示意性透视图；以及
图6是本器件的另一实施例的示意性截面图。
具体实施方式
图1示出了用于半导体器件2(特别是双向AC开关)的封装件1。如下文中将强调的，封装件1是双岛表面安装型。
详细地，封装件1包括由绝缘材料(例如，环氧树脂)制成的封装件涂层5(图2中示出，但图1中未示出)、以及第一部分P1和第二部分P2。在没有暗示任何通用性损失的情况下，第一部分P1和第二部分P2彼此相同并且以对称的方式布置在半导体器件2内，另一方面，第一裸片6和第二裸片106也是如此。在下文中，为简洁起见，仅描述封装件1的第一部分P1。此外，第二部分P2的部件由与第一部分P1的部件相同的附图标记增加100来表示。
详细地，第一部分P1包括引线框架3的支撑件4，支撑件4由金属板形成(例如，由铜制成并且具有平行六面体形状)并且具有顶表面4a和底部表面4b。支撑件4以本身已知的方式也称为“岛”或“裸片焊盘”。
支撑件4的底部表面4b形成封装件1(图2中所示)的暴露的底部表面1b，底部表面1b本身可以用作散热器或者(以本文未示出的方式)耦合到外部散热器，以便增加向外散热的能力。
封装件涂层5尤其在支撑件4的顶部和侧表面4c处包覆和涂覆(使其底部表面4b暴露，如前所述)。
封装件1的第一部分P1还包括布置在支撑件4的顶部的底部绝缘多层26。具体地，底部绝缘多层26是DBC(直接键合铜)型的多层，并且因此由均由铜制成的相应顶部金属层26a和相应底部金属层26b以及由陶瓷材料制成的相应中间层26c(例如，氧化铝(Al2O3)、或者氮化铝(AlN)或氧化铍(BeO))形成。顶部金属层26a、底部金属层26b和中间层26c彼此堆叠地布置，并且借助于在高温下的直接共晶接合而耦合在一起；中间层26c使顶部金属层26a和底部金属层26b电绝缘。
底部金属层26b借助于第一焊膏层7a(图2中所示)耦合到支撑件4的顶表面4a。
半导体器件2还包括内部分别形成有第一功率MOSFET M1和第二功率MOSFET M2的第一裸片6和第二裸片106。在没有暗示任何通用性损失的情况下，第一裸片6和第二裸片106彼此相同并且以对称的方式布置在半导体器件2内。在下文中，为简洁起见，仅描述第一裸片6。此外，第二裸片106的部件由与第一裸片6的部件相同的附图标记增加100来表示。此外，第一裸片6和第二裸片106分别以同样的方式耦合到封装件1的第一部分P1和第二部分P2。因此，在下文中，仅描述将第一裸片6接合到封装件1的第一部分P1。另外，可以注意到在图1中如何定性地示出第一裸片6和第二裸片106，关于与下文中定义为“顶部绝缘多层16”的元件的耦合的相应细节也是如此，如下所述；对于这些细节，关于第一裸片6和第二裸片106的细节也是如此，读者因此参考图2的描述。
详细地，第一裸片6布置在封装件1的第一部分P1的底部绝缘多层26上。
更详细地，第一裸片6具有前表面6a、后表面6b和中间表面6c。此外，第一裸片6包括由半导体材料(例如，硅)制成的本体9，本体9中以本身已知且本文中未详细示出的方式集成有第一功率MOSFET M1的多个基本单元，多个基本单元布置成条状并且具有例如竖直柱状结构，每个单元设置有相应栅极区域和相应源极区域。半导体本体9在顶部处由前述中间表面6c界定，并且形成第一功率MOSFET M1的栅极区域和源极区域。
此外，第一裸片6包括漏极金属化部8，漏极金属化部8布置在半导体本体9下方，与半导体本体9直接接触，并且形成第一裸片6的后表面6b。漏极金属化部8形成第一功率MOSFET M1的漏极焊盘。另外，漏极金属化部8以及因此第一裸片6的后表面6b通过第二焊膏层7b的插入而耦合到底部绝缘多层26的顶部金属层26a。因此，漏极金属化部8电连接和热连接到绝缘多层26的顶部金属层26a。此外，第一功率MOSFET M1的漏极金属化部8与支撑件4电绝缘。
第一裸片6还包括钝化区域13，钝化区域13在半导体本体9上延伸并且形成上述顶表面6a。在这方面，应当注意，如前所述，在图1中第一裸片6如何整体示出，即，除了其他之外，没有示出半导体本体9、钝化区域13和漏极金属化部8。
如图3中更详细地所示(然而，为了更加清楚，未示出钝化区域13)，第一裸片6包括多个栅极金属化线10(所谓的“栅极指状物”)，这些栅极金属化线10使得能够对第一功率MOSFET M1的单元的栅极区域进行偏置(以未示出但本身已知的方式)。就此而言，在图3所示的实施例中，仅存在一条栅极金属化线10，而这并不暗示任何通用性损失。
栅极金属化线10在钝化区域13下方延伸并且彼此平行。另外，栅极金属化线10可以是连续的，或者如在所示的示例中，沿其纵向延伸具有中断。另外，栅极金属化线10在俯视图中界定钝化区域13的部分11(仅在图3中示出)，这些部分11在下文中称为“顶部钝化区域11”。
如图4所示，在顶部钝化区域11内形成有对应的窗口18(图4中所示)，这些窗口18在钝化区域13内从顶表面6a开始延伸一段深度以便不穿透半导体本体9。特别地，每个窗口18由对应的顶部钝化区域11的两个部分横向界定。
如图2至图4中可见，第一裸片6还包括源极接触区域12(也称为源极焊盘)，源极接触区域12由导电材料(例如，金属)制成，与第一功率MOSFET M1的单元的源极区域电接触，并且与上述栅极金属化线10绝缘。另外，每个源极接触区域12在底部处界定对应的窗口18。
在所示的示例中，源极接触区域12在俯视图中是矩形的，并且此外具有彼此相同的尺寸。特别地，第一裸片6中存在两个顶部钝化区域11，顶部钝化区域11内存在两个窗口18，窗口18内部布置有对应的源极接触区域12。然而，如前所述，栅极金属化线10、顶部钝化区域11和源极接触区域12的分布和数目可以根据功率半导体器件2的特性和要求而变化。此外，通常假定连续的任意数目的顶部钝化区域11，连续的顶部初始和最终钝化区域仅通过相应栅极金属化线10在相应侧(特别是面向其他顶部钝化区域的一侧)界定。因此，考虑到对应的两个窗口18中的每个，对应的顶部钝化区域11的界定它们的两个部分之一(特别是面向外的部分)不包含任何栅极金属化线。
如前所述，前述源极接触区域12布置在顶部钝化区域11内，相对于栅极金属化线10在大约相同的高度。此外，源极接触区域12在底部处界定对应的窗口18。
再次参考栅极金属化线10，它们中的每个被钝化区域13的对应部分10'覆盖，该部分在下文中称为“对应的主钝化部分10”。特别地，每个栅极金属化线10涂覆有对应的主钝化部分10'。
第一裸片6还包括一个或多个栅极焊盘15，这些栅极焊盘15仅在图1和图4中可见(其中仅示出了一个，大致且定性地布置在第一裸片6上)。具体地，参考图4，为了简化表示，这将栅极焊盘15示出为布置成与半导体本体9接触，即使实际上栅极焊盘15布置在距半导体本体9的特定(短)距离处。每个栅极焊盘15电耦合到对应的栅极金属化线10。此外，钝化区域13使栅极焊盘15暴露。在没有暗示任何通用性损失的情况下，在图1至图4所示的示例中，第一裸片6仅包括一个栅极焊盘15。
再次参考封装件1的第一部分P1，它还包括漏极引线27和栅极引线29，这些引线具有例如平行六面体的形状，由与制作支撑件4的金属材料相同的金属材料制成，并且彼此物理地分离以及与支撑件4物理分离。借助于由导电材料(例如，铜)制成的所谓的夹具28(图1中所示)，在下文中称为“漏极夹具28”，漏极引线27连接到绝缘多层26的顶部金属层26a，并且特别地连接到顶部金属层26a的没有被第一裸片6覆盖一部分。以其本身已知的方式，漏极夹具28在其端部处通过对应的焊膏区域(未示出)连接到顶部金属层26a的上述部分和漏极引线27。
第一裸片6的栅极焊盘15借助于导线15'(即借助于接线键合)连接到封装件1的第一部分P1的栅极引线29。
再次参考封装件1的第一部分P1，如图5所示，对应的漏极引线27和栅极引线29横向暴露在下面；也就是说，它们没有涂覆涂层5。换言之，假定涂层5具有包络形状，例如平行六面体，其底部和顶部基部由底部表面1b和顶部表面1a形成，除了形成底部表面1b之外，漏极引线27和栅极引线29还形成上述壳体的第一侧表面PW1。另一方面，支撑件4的一部分也横向暴露，因为它例如伸出到第二侧表面PW2上。再次参考图5，应当注意，在没有暗示任何通用性损失的情况下，参考其中支撑件4具有与平行六面体不同的形状的实施例，因为它包括具有平行六面体形状的主体和多个突起，多个突起从主体的同一侧面分支，直到它们伸出到上述侧表面PW2上。
封装件1还包括源极引线31，如下文更详细描述的，源极引线31在封装件1的第一部分P1与第二部分P2之间共享。电流引线31也横向暴露在下面。
功率半导体器件2的封装件1还包括(再次参见图1和2)另一绝缘多层16，另一绝缘多层16在下文中称为“顶部绝缘多层16”。
详细地，顶部绝缘多层16是DBC多层并且包括由铜制成的相应顶部金属层16a和相应底部金属层16b、以及例如由陶瓷材料(与制造中间绝缘层26c的材料相同的材料)制成的相应中间绝缘层16c。顶部金属层16a和中间绝缘层16c的厚度可以等于例如底部绝缘多层26的对应层的厚度。中间绝缘层16c使顶部金属层16a和底部金属层16b电绝缘。
顶部绝缘多层16的顶部金属层16a形成封装件1的顶表面1a的一部分，该部分本身可以用作散热器或者(以本文中未示出的方式)耦合到另外的外部散热器，以便增加向外散热的能力。
顶部绝缘多层16的底部金属层16b以与第一裸片6和第二裸片106的构造相对应的方式成形。具体地，底部金属层16b包括第一外围部分30和第二外围部分130以及中央部分32。
第一外围部分30和第二外围部分130彼此相同并且以相同的方式分别耦合到第一裸片6和第二裸片106。换言之，第一外围部分30和第一裸片6的相对布置与第二外围部分130和第二裸片106的相对布置相同。因此，下面仅描述第一外围部分30及其到第一裸片6的对应耦合。此外，第二外围部分130的元件用与第一外围部分30相同的附图标记增加100来表示。
详细地，底部金属层16b的第一外围部分30具有与第一裸片6的栅极金属化线10的布置相对应的形状，并且更确切地说，与对应的主钝化部分10'的布置相对应的形状，以及与源极接触区域12的布置相对应的形状。
更详细地，并且参考图2，顶部绝缘多层16的底部金属层16b的第一外围部分30具有梳状构造。实际上，第一外围部分30包括平面区域34和多个接触区域36，接触区域36作为凸块从平面区域34开始朝向下面的第一裸片6延伸。具体地，每个接触区域36延伸直到它穿透到下面的第一裸片6的对应的窗口18中，以便机械地和电气地耦合到对应的源极接触区域12。例如，每个接触区域36具有平行六面体形状并且具有相应底部平面表面，该底部平面表面通过对应的焊膏区域19的插入而机械地和电气地耦合到对应的源极接触区域12。此外，每个接触区域36从对应的窗口18的侧壁延伸一段距离，以便不接触对应的主钝化区域11。
继而，成对的相邻接触区域36横向地界定对应的绝缘腔体40，绝缘腔体40在顶部由平面区域34的对应部分界定并且在底部处开口。因此，绝缘腔体40是介于接触区域36之间的沟槽(例如，具有矩形横截面，对于平行于栅极金属化线10的延伸方向的平移不变)，以便在一定距离上覆盖对应的栅极金属化线10。每个沟槽的顶壁由平面区域34形成，而侧壁由对应的接触区域36形成。图2中仅存在一个绝缘腔体40，因为纯粹作为示例，假定第一裸片6包括仅两个源极接触区域12和仅一个栅极金属化线10。然而，很明显，绝缘腔体40的数目、形状和布置可以如何根据栅极金属化线10和源极接触区域12的布置和构造而不同。
在实践中，绝缘腔体40相对于窗口18横向交错，相对于窗口18，绝缘腔体40还布置为处于更大的高度。此外，绝缘腔体40和窗口18具有相反的凹面；即，绝缘腔体40向下开口，而窗口18向上开口。
更详细地，每个绝缘腔体40覆盖在对应的主钝化部分10'上，如上所述，主钝化部分10'继而覆盖对应的栅极金属化线10并且从相邻窗口18朝向相应绝缘腔体40突出。在没有暗示任何通用性损失的情况下，每个主钝化部分10'的突出使得最大高度点是布置在下面的栅极金属化线10上方的第一近似值。
特别地，每个主钝化部分10'设置在距相应绝缘腔体40一定距离处；即，它不接触相应绝缘腔体40的顶壁或侧壁，即使它可以至少部分穿透到对应的绝缘腔体40中，并且更确切地说，可以穿入由对应绝缘腔体40界定的容积中；换言之，在每个主钝化部分10'与对应的绝缘腔体40之间存在间隙，该间隙防止主钝化部分10'与绝缘腔体40的侧壁和顶壁之间的接触。以这种方式，接触区域36跨越或者绕过主钝化部分10'，因为它们横向散布在后者中。因此，防止了接触区域36(接触区域36实现源极接触区域12的接触)损坏主钝化部分10'和下面的栅极金属化线10。
关于顶部绝缘多层16的底部金属层16b的中央部分32，它连接底部金属层16b的第一外围部分30和第二外围部分130的平面区域34、134，以与后者形成单个部件。平面区域34、134和中央部分32的顶部形成分层区域，该分层区域的厚度可以例如等于底部绝缘多层26的底部金属层26b的厚度。
从图1中可以看出，底部金属层16b的中央部分32的底部还形成源极夹具14的主部分14'。该源极夹具14还包括将上述主部分14'连接到源极引线31的连接部分14”。该连接部分14”可以与主部分14'一体地设置，并且因此与底部金属层16b的中央部分32一体地设置。在任何情况下变型都是可能的，其中例如，源极夹具14不与底部金属层16b形成单个部件，而是通过对应的焊膏区域的插入耦合到后者。
实际上，顶部绝缘多层16的底部金属层16b使第一功率MOSFET M1和第二功率MOSFET M2的源极端子短路，从而形成经由源极引线31可电访问的节点。相反，第一功率MOSFET M1的漏极和栅极端子分别经由漏极引线27和栅极引线29可访问；相反，第二功率MOSFET M2的漏极和栅极端子分别经由漏极引线127和栅极引线129可访问。
所公开的解决方案的优点从上面已经描述的内容中清楚地显现出来。
特别地，就累赘而言，本实用新型的功率器件使得可以受益于来自表面安装型封装件的优点，虽然保证了良好的电绝缘性和相当大的散热能力。
特别地，本实用新型的封装件在竖直方向上可以具有2-3mm的最大厚度。此外，该封装件提供了在两侧(顶部和底部)冷却的可能性。再次，顶部绝缘多层在桥式配置中的存在(即延伸以覆盖两个裸片)保证了相当大的热效率，降低了寄生封装电效应(特别是电感效应)并且降低了接触电阻。再次，与功率MOSFET的源极区域的连接不需要使用接线键合。
特别地，关于散热，顶部金属层16a与第一MOSFET M1和第二功率MOSFET M2的源极区域绝缘的这一事实意味着它可以自由地调节尺寸以优化功耗，而没有由于需要保证一定的电流而产生的限制因素。在这方面，可以确定底部金属层16b的厚度的尺寸以使得电流的流动不受此限制，而是受漏极夹具28和128的限制。
另外，例如，参考封装件1的第一部分P1，底部绝缘多层26的顶部金属层26a的存在使得可以具有用于漏极夹具28的最佳耦合区域。此外，引线框架支撑件与第一MOSFET M1和第二功率MOSFET M2的漏极区域绝缘的这一事实意味着它们处于同一电位。因此，引线框架支撑件可以彼此非常靠近地布置，从而减小了封装件1的竖直累赘。
最后，清楚的是，在不脱离如所附权利要求中限定的本公开的保护范围的情况下，可以对本文中描述和说明的内容进行修改和变化。
绝缘多层的金属层可以由除了铜之外的金属材料制成。
夹具连接可以用对应的接线键合代替，即使夹具保证了更大的热量抽取和被更高电流穿过的能力。
引线框的支撑件的形状可以与所描述的不同；例如，它可以包括连接在一起并且关于彼此竖直交错的成对平面子区域。
栅极、源极和漏极引线以及在封装件外部伸出的支撑件的各部分可以相对于封装件的壳体突出，而不是与封装件的相应壁齐平。
关于顶部绝缘多层的底部金属层的第一外围部分和第二外围部分中的每个，对应的接触区域可以以与所描述的不同的方式分布。另外，前述第一外围部分和第二外围部分中的每个可以包括相应平面子部分，而没有接触区域。
此外，图6所示类型的实施例是可能的，其中不存在顶部金属层16a和顶部绝缘多层16的中间层16c。在这种情况下，底部金属层16b形成封装件1的顶表面1a的一部分。
最后，除了MOSFET之外的对应半导体器件(诸如纯粹作为示例的IGBT)可以被集成在裸片中。本实用新型的封装件实际上可以管理顶部绝缘多层与任何半导体器件之间的耦合，其中存在有钝化区域，钝化区域覆盖布置在对应的裸片的半导体本体上的金属化线并且介于要偏置的接触区域之间。
可以组合上述各种实施例以提供其他实施例。根据以上详细描述，可以对实施例进行这些和其他改变。通常，在以下权利要求中，所使用的术语不应当被解释为将权利要求限制于说明书和权利要求中公开的特定实施例，而是应当被解释为包括所有可能的实施例以及这样的权利要求有权享有的等同物的全部范围。因此，权利要求不受本公开的限制。

Claims (20)

1.一种功率半导体器件，其特征在于，包括：
第一裸片和第二裸片，所述第一裸片和所述第二裸片中的每个裸片包括钝化区域和多个导电接触区域，所述钝化区域包括多个突出电介质区域和多个窗口，相邻窗口由对应的突出电介质区域隔开，每个导电接触区域布置在对应的窗口内；以及
表面安装型封装件，容纳所述第一裸片和所述第二裸片，其中所述封装件包括：
第一底部绝缘多层和第二底部绝缘多层，分别承载所述第一裸片和所述第二裸片，并且每个底部绝缘多层包括相应顶部金属层、相应底部金属层和介于对应的顶部金属层与对应的底部金属层之间的相应中间绝缘层；以及
覆盖金属层，布置在所述第一裸片和所述第二裸片的顶部，并且包括延伸到所述窗口中以与对应的导电接触区域电耦合的突出金属区域，所述覆盖金属层具有多个腔体，所述多个腔体介于所述突出金属区域之间以覆盖对应的突出电介质区域。
2.根据权利要求1所述的功率半导体器件，其特征在于，还包括顶部绝缘多层，所述顶部绝缘多层包括相应顶部金属层、所述覆盖金属层、以及介于所述相应顶部金属层与所述覆盖金属层之间的相应中间绝缘层。
3.根据权利要求2所述的功率半导体器件，其特征在于，还包括由金属材料制成的第一支撑件和第二支撑件，所述第一支撑件和第二支撑件分别承载所述第一底部绝缘多层和所述第二底部绝缘多层。
4.根据权利要求3所述的功率半导体器件，其特征在于，所述封装件还包括：
封装件涂层，其覆盖所述第一裸片和所述第二裸片以及所述第一底部绝缘多层和所述第二底部绝缘多层；以及
第一引线，其包括从所述封装件涂层暴露的部分；并且
其中所述覆盖金属层电耦合到所述第一引线。
5.根据权利要求4所述的功率半导体器件，其特征在于，所述封装件涂层覆盖所述第一支撑件和所述第二支撑件，并且其中所述第一支撑件和所述第二支撑件中的每个支撑件包括从所述封装件涂层暴露的相应部分。
6.根据权利要求5所述的功率半导体器件，其特征在于，所述封装件还包括第二引线和第三引线，所述第二引线和所述第三引线中的每个引线包括从所述封装件涂层暴露的相应部分，并且其中所述第一底部绝缘多层和所述第二底部绝缘多层的顶部金属层分别电耦合到所述第二引线和所述第三引线。
7.根据权利要求1所述的功率半导体器件，其特征在于，所述第一裸片和所述第二裸片中的每个裸片包括多个金属化线，每个金属化线涂覆有对应的突出电介质区域。
8.根据权利要求7所述的功率半导体器件，其特征在于，
所述第一裸片和所述第二裸片分别包括第一晶体管和第二晶体管；以及
所述第一裸片和所述第二裸片的所述金属化线是相应晶体管的栅极线；以及
所述第一裸片和所述第二裸片的所述导电接触区域是相应晶体管的源极接触区域。
9.根据权利要求1所述的功率半导体器件，其特征在于，
所述第一裸片和所述第二裸片中的每个裸片包括相应底部接触金属化部；以及
所述第一裸片和所述第二裸片的所述底部接触金属化部分别电耦合到所述第一底部绝缘多层和所述第二底部绝缘多层的顶部金属层。
10.根据权利要求1所述的功率半导体器件，其特征在于，所述覆盖金属层在距所述第一裸片和所述第二裸片的钝化区域一距离处延伸。
11.一种功率半导体器件，其特征在于，包括：
第一裸片和第二裸片，所述第一裸片和所述第二裸片中的每个裸片具有第一表面和与所述第一表面相对的第二表面并且还包括在所述第一表面上的钝化区域和多个导电接触区域，所述钝化区域包括多个突出电介质区域和在相邻的突出电介质区域之间限定的多个窗口，所述多个导电接触区域中的每个导电接触区域布置在所述多个窗口中的对应的窗口内；以及
封装件，包含所述第一裸片和所述第二裸片，所述封装件包括：
第一底部绝缘多层和第二底部绝缘多层，所述第一裸片和所述第二裸片的所述第二表面分别位于所述第一底部绝缘多层和所述第二底部绝缘多层上，所述第一底部绝缘多层和所述第二底部绝缘多层中的每个底部绝缘多层包括相应顶部金属层、相应底部金属层和在所述顶部金属层与所述底金属层之间的相应中间绝缘层；以及
在所述第一裸片和所述第二裸片的所述第一表面上的覆盖金属层，所述覆盖金属层包括延伸到所述多个窗口中以将所述覆盖金属层电耦合到所述多个导电接触区域中的相应导电接触区域的突出金属区域，所述覆盖物金属层还包括介于所述突出金属区域之间的多个腔体，所述多个腔体中的每个腔体被定位成覆盖所述多个突出电介质区域中的对应的突出电介质区域。
12.根据权利要求11所述的功率半导体器件，其特征在于，所述封装件包括表面安装封装件。
13.根据权利要求11所述的功率半导体器件，其特征在于，还包括在所述第一裸片和所述第二裸片的所述第一表面上的顶部绝缘多层，所述顶部绝缘多层包括顶部金属层、所述覆盖金属层和介于所述顶部金属层与所述覆盖金属层之间的中间绝缘层。
14.根据权利要求13所述的功率半导体器件，其特征在于，还包括第一金属支撑件和第二金属支撑件，所述第一底部绝缘多层和所述第二底部绝缘多层分别位于所述第一金属支撑件和所述第二金属支撑件上。
15.根据权利要求14所述的功率半导体器件，其特征在于，所述封装件还包括：
封装件涂层，覆盖所述第一裸片和所述第二裸片以及所述第一底部绝缘多层和所述第二底部绝缘多层；以及
第一引线，电耦合到所述覆盖金属层，所述第一引线包括从所述封装件涂层暴露的部分。
16.根据权利要求15所述的功率半导体器件，其特征在于，所述封装件涂层还覆盖所述第一金属支撑件和第二金属支撑件，并且其中所述第一金属支撑件和第二金属支撑件中的每个金属支撑件包括从所述封装件涂层暴露的部分。
17.一种封装件，其特征在于，包括：
第一底部绝缘多层和第二底部绝缘多层，分别被配置为承载第一裸片和第二裸片，每个底部绝缘多层包括顶部金属层、底部金属层和位于所述顶部金属层与所述底部金属层之间的中间绝缘层；以及
覆盖金属层，布置在所述第一裸片和所述第二裸片的顶部，所述覆盖金属层包括突出金属区域，所述突出金属区域被配置为分别延伸到所述第一裸片和所述第二裸片上的第一钝化区域和第二钝化区域中的窗口中，所述第一钝化区域和所述第二钝化区域包括多个突出电介质区域，并且所述覆盖金属层被配置为电接触在所述窗口内的所述第一裸片和所述第二裸片上暴露的导电接触区域，所述覆盖金属层还包括位于所述突出金属区域之间的多个腔体，所述多个腔体中的每个腔体位于所述多个突出电介质区域中的对应的突出电介质区域之上。
18.根据权利要求17所述的封装件，其特征在于，所述封装件包括表面安装型封装件。
19.根据权利要求17所述的封装件，其特征在于，所述第一裸片和所述第二裸片中的每个裸片包括功率MOSFET器件。
20.根据权利要求19所述的封装件，其特征在于，还包括：第一导电支撑件和第二导电支撑件，分别被配置为支撑所述第一底部绝缘多层和所述第二底部绝缘多层。
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