CN115346917A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN115346917A CN115346917A CN202210658260.2A CN202210658260A CN115346917A CN 115346917 A CN115346917 A CN 115346917A CN 202210658260 A CN202210658260 A CN 202210658260A CN 115346917 A CN115346917 A CN 115346917A
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Abstract
本发明实施例涉及半导体器件及其制造方法。在制造半导体器件的方法中,在衬底上方形成第一导电层。在第一导电层上方形成第一光刻胶层。以第一光刻胶层为蚀刻掩模蚀刻第一导电层,以形成第一导电层的岛状图案,岛状图案与第一导电层的汇流条图案通过环形沟槽间隔开。形成连接图案以连接岛状图案和汇流条图案。在第一导电层和连接图案上方形成第二光刻胶层。第二光刻胶层包括在岛状图案上方的开口。在开口中形成在岛状图案上的第二导电层。去除第二光致光刻胶层,并去除连接图案,从而形成凸块结构。
Description
技术领域
本发明实施例涉及半导体器件及其制造方法。
背景技术
随着具有更好性能的消费设备响应于消费者需求而变得越来越小,这些设备的各个组件的尺寸也必然减小。构成诸如移动电话、平板电脑等消费设备的主要组件的半导体器件已经变得越来越小。半导体器件尺寸的减小伴随着半导体制造技术的进步,诸如在半导体器件和另外电子器件或电路板之间形成连接。
发明内容
根据本发明实施例的一个方面,提供了一种制造半导体器件的方法,方法包括:形成下部导电图案,下部导电图案包括多个导电图案在第一方向上排列的第一列图案和多个导电图案在第一方向上排列的第二列图案,第一列和第二列在与第一方向交叉的第二方向上彼此相邻;以及形成上部导电图案,上部导电图案包括多个导电图案在第一方向上排列的第三列图案和多个导电图案在第一方向上排列的第四列图案,第三列和第四列在第二方向上彼此相邻,其中:第一列和第三列在平面图中至少部分地彼此重叠,第二列和第四列在平面图中至少部分地彼此重叠,并且上部导电图案形成为使得在第一列和第二列的第一方向上延伸的第一中心线从第三列和第四列的在第一方向上延伸的第二中心线在第二方向上以大于0.1μm的偏移量偏移。
根据本发明实施例的另一个方面,提供了一种制造半导体器件的方法,方法包括:形成在第一方向上排列并且嵌入第一介电层中的多个第一导电图案;在多个第一导电图案和第一介电层上方形成第二介电层;通过第一图案化操作在第二介电层中形成多个开口,每个开口位于多个第一导电图案中的对应一个上方;在第二介电层上方和多个开口中形成导电材料的毯式层;通过第二图案化操作图案化导电材料的毯式层以形成与多个第一导电图案中的对应一个连接的多个第二导电图案;以及在多个第二导电图案上方形成第三介电层,其中,在第一图案化操作中,多个开口作为整体在第一方向上从多个第一导电图案作为整体在平面图中以大于0.1μm的偏移量偏移。
根据本发明实施例的又一个方面,提供了一种半导体器件,半导体器件包括:半导体电路,设置在衬底上方;下部导电图案,设置在半导体电路上方并且电耦合到半导体电路,下部导电图案包括多个导电图案在第一方向上排列的图案的第一列和多个导电图案在第一方向上排列的图案的第二列,第一列和第二列在平面图中在与第一方向交叉的第二方向上相邻;第一介电层,设置在下部导电图案上方;上部导电图案,设置在下部导电图案上方,上部导电图案包括多个导电图案在第一方向上排列的图案的第三列和多个导电图案在第一方向上排列的图案的第四列,第三列和第四列在平面图中在第二方向上相邻;以及第二介电层,设置在上部导电图案上方,其中:在平面图中,在第一列和第二列之间在第一方向上延伸的第一中心线从在第三列和第四列之间在第一方向上延伸的第二中心线在第二方向上偏移。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该强调,根据工业中的标准实践,各个部件未按比例绘制并且仅用于说明的目的。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1示出了根据本公开实施例的半导体器件的顺序制造操作的阶段中的一个。
图2示出了根据本公开实施例的半导体器件的顺序制造操作的阶段中的一个。
图3示出了根据本公开实施例的半导体器件的顺序制造操作的阶段中的一个。
图4示出了根据本公开实施例的半导体器件的顺序制造操作的阶段中的一个。
图5示出了根据本公开实施例的半导体器件的顺序制造操作的阶段中的一个。
图6A和图6B示出了根据本公开实施例的半导体器件的顺序制造操作的阶段中的一个。
图7示出了根据本公开实施例的半导体器件的顺序制造操作的阶段中的一个。
图8A和图8B示出了根据本公开实施例的半导体器件的视图。
图9A和图9B示出了根据本公开实施例的半导体器件的视图。
图10示出了根据本公开实施例的半导体器件的视图。
图11示出了根据本公开实施例的半导体器件的视图。
图12示出了根据本公开实施例的半导体器件的视图。
图13示出了根据本公开实施例的半导体器件的视图。
图14示出了根据本公开实施例的半导体器件的视图。
图15示出了根据本公开实施例的半导体器件的视图。
图16示出了根据本公开实施例的半导体器件的视图。
图17示出了根据本公开实施例的半导体器件的视图。
图18示出了根据本公开实施例的半导体器件的顺序制造操作的流程。
图19示出了根据本公开实施例的光掩模的顺序制造操作的流程。
图20示出了本公开的实施例的有益效果。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然,这些仅是实例而不旨在限制。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成附加的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可以在各个示例中重复参考数字和/或字母。该重复是为了简单和清楚的目的,并且其本身不指示讨论的各个实施例和/或配置之间的关系。
此外,为了便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的间隔关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,间隔关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位),并且在本文中使用的间隔关系描述符可以同样地作相应地解释。此外,术语“由……组成”可以意味着“包括”或“由……构成”。下文描述的数值、范围、尺寸、材料、工艺、配置和/或布置仅仅是示例并且不限于所公开的那些数值、范围、尺寸、材料、工艺、配置和/或布置,并且除非另有说明,其他数值、范围、尺寸、材料、工艺、配置和/或布置可以在本公开的范围内。
随着电子工业发展了基于硅贯通孔(TSV)技术的三维集成电路(3DIC),正在积极研究用于互连堆叠的芯片的最顶部电极(诸如焊盘电极或焊盘电极上的凸块)的处理和可靠性。焊盘电极由一个或多个钝化绝缘膜覆盖以保护形成在焊盘电极下方的半导体器件。钝化层的可靠性也是制造半导体器件的重要因素。在一些实施例中,凸块电极形成在焊盘电极上,而在其他实施例中,接合布线(bonding wire)直接附接到焊盘电极。
在本公开中,提供了可以提高半导体器件的可靠性的形成焊盘电极和钝化层的新技术。
图1至图7示出了根据本公开实施例的半导体电路上方的凸块结构的顺序制造操作的各种视图。可以理解的是,可以在图1至图7所示的工艺之前、期间和之后提供附加的操作,并且对于方法的附加实施例,可以替换或消除下面描述的操作中的一些。操作/工艺的顺序可以互换。
如图1所示,其上要形成凸块电极的多个最顶部布线图案20形成在半导体电路15上方的层间介电(ILD)或金属间介电(IMD)层18中,半导体电路15形成在衬底10上。最顶部布线图案20由合适的导电金属形成,导电金属包括铝、铜、银、金、镍、钨、钛、它们的合金和/或它们的多层。在一些实施例中,最顶部布线图案20由Cu或其中大部分(超过50%)为Cu的Cu合金制成。最顶部布线图案20由合适的金属沉积操作形成,沉积操作包括电镀或化学镀、物理气相沉积(PVD)(包括溅射)、化学气相沉积(CVD)、原子层沉积(ALD)、热蒸发或电子束蒸发。在一些实施例中,通过使用镶嵌技术形成最顶部布线图案20。
在一些实施例中,半导体电路15包括晶体管(例如,场效应晶体管(FET))、电容器、电感器、电阻器、或者在一些实施例中的类似器件。最顶部布线图案20通过下面的互连层电耦合到半导体电路15,下面的互连层包括形成在介电层(诸如在一些实施例中的ILD层或IMD层)中的布线层和通孔。互连层的布线层和通孔可以由铜或铜合金(例如,AlCu)、铝、钨、镍或任何其他合适的金属形成。可以使用镶嵌工艺形成布线层和通孔。
在一些实施例中,衬底10由从硅、金刚石、锗、SiGe、SiGeSn、SiGeC、GeSn、SiSn、GaAs、InGaAs、InAs、InP、InSb、GaAsP、GaInP和SiC组成的组中选择的至少一种形成。在一些实施例中,半导体衬底10是硅晶圆或硅衬底。在一些实施例中,ILD或IMD层18包括氧化硅、氮化硅、SiOC、SiON、SiOCN、SiCN、低k介电材料或任何其他合适的介电材料中的一种或多种。
在一些实施例中,如图2所示,一个或多个顶部介电层22形成在最顶部布线图案20上方。顶部介电层22包括一层或多层的氧化硅、氮化硅、SiON、SiC、SiOCN、SiCN或任何其他合适的绝缘层。在一些实施例中,顶部介电层22的厚度在从约0.1μm到约2.0μm的范围内,以及在从约0.2μm到约1.0μm的范围内。通过包括PVD、CVD或ALD的合适的金属沉积操作形成顶部介电层22。
使用合适的光刻和蚀刻操作图案化顶部介电层22以形成开口24。如图2所示,在顶部介电层22上形成具有开口的光刻胶图案25,并且通过一个或多个蚀刻操作图案化顶部介电层22。如图3所示,通过蚀刻暴露最顶部布线图案20的部分。在一些实施例中,开口24具有如图3所示的锥形。
然后,如图4所示,一个或多个导电层30L形成为顶部导电层22和暴露的最顶部布线图案20上方的毯式层。在一些实施例中,毯式导电层30L通过合适的金属沉积操作来形成,合适的金属沉积操作包括电镀、PVD(包括溅射)、CVD、ALD、热蒸发和电子束蒸发。在一些实施例中,毯式导电层30L包括合适的导电金属,包括铝、铜、银、金、镍、钨、钛、它们的合金和/或它们的多层。在一些实施例中,毯式导电层30L由Al或其中大部分(超过50%)为Al的Al合金制成。在一些实施例中,顶部介电层22上方的毯式导电层30L的厚度在从约0.5μm到约5.0μm的范围内,以及在其他实施例中,在从约1.0μm到约3.0μm的范围内。在一些实施例中,如图4所示,在开口24上方形成反映顶部介电层22的形状的凹部或凹坑32。在一些实施例中,凹部或凹坑32具有V形、U形或倒梯形。在一些实施例中,凹部或凹坑32的深度在从约0.05μm到约0.5μm的范围内,以及在其他实施例中,在从约0.1μm到约0.4μm的范围内。
在一些实施例中,在形成毯式导电层30L之前形成一个或多个阻挡层。在一些实施例中,阻挡层包括Ti、TiN、Ta、TaN或TiW。
进一步,如图5所示,在毯式导电层30L上方形成光刻胶图案35,并且通过使用一个或多个蚀刻操作将毯式导电层30L图案化为焊盘电极30。在一些实施例中,如图6A所示,焊盘电极30具有锥形,锥形具有锥角,锥角相对于朝向最顶部布线图案20的上表面的法线方向在从约5度到约15度的范围内。在其他实施例中,如图6B所示,焊盘电极30具有倒锥形,倒锥形具有锥角,锥角相对于法线方向在从约-5度到约-15度的范围内。
接下来,如图7所示,在焊盘电极30和顶部介电层22上方形成钝化层40。在一些实施例中,钝化层40包括一层或多层的氧化硅、氮化硅、SiOC、SiON、SiOCN、SiCN或任何其他合适的介电材料层。在一些实施例中,氮化硅被用作钝化层40。在一些实施例中,距焊盘电极30的顶部的钝化层40的厚度在从约1.0μm到约10μm的范围内,以及在从约2.0μm到约5.0μm的范围内。钝化层40通过包括PVD、CVD或ALD的合适的沉积操作形成。如图7所示,钝化层40具有在焊盘电极30上方的峰和在焊盘电极30之间的谷。
此外,在一些实施例中,通过一个或多个光刻和蚀刻操作图案化钝化层40,以在焊盘电极30上方形成开口以用于外部电连接(通过布线或通过凸块)。
在如图8A所示的一些实施例中,最顶部布线图案20以行-列(X-Y)排列布置。在一些实施例中,最顶部布线图案20具有矩形,矩形在平面图中具有沿着行(X)方向的第一边(宽度L1)和沿着列(Y)方向的第二边(宽度L2)。在一些实施例中,0.8≤L1/L2≤1.2,并且在其他实施例中,0.95≤L1/L2≤1.05(基本正方形)。在一些实施例中,L1和L2在从约2μm到10μm的范围内,并且在其他实施例中,在从约4μm到6μm的范围内。在一些实施例中,最顶部布线图案20的矩形或正方形在平面图中具有圆角。在一些实施例中,多个最顶部布线图案20以行-列排列布置,行-列排列具有约2.5μm到约15μm的节距P1(相邻的布线图案20之间的间隔在从约0.5μm到约5.0μm的范围内)。在一些实施例中,沿着行方向的节距与沿着列方向的节距相同或不同。在一些实施例中,最顶部布线图案20的厚度在从约1.0μm到约5.0μm的范围内,并且在其他实施例中,在从约3.0μm到约4.0μm的范围内。
最顶部布线图案20的2×4排列在图8A中示出,但本公开不限于2×4排列。在一些实施例中,排列为2×N排列,其中N为4或更大(例如,高达100)。包括更少或更多数量的顶部布线图案20的行或列的其他排列包括在本公开的范围内。例如,排列可以是M×N排列,其中M和N是自然数,并且M和N中的至少一个是2或多达约100。在一些实施例中,在与M×N排列距离L0内的相同布线层级处,M×N排列没有其他布线图案,其中L0是M×N排列的节距的两倍到十倍。在一些实施例中,最顶部布线图案20的矩阵的行长度或列长度中的至少一个在从约200μm到2mm的范围内。
类似地,在如图8A所示的一些实施例中,焊盘电极30以行-列排列布置。在一些实施例中,由于焊盘电极30分别形成在最顶部布线图案20上方,所以焊盘电极30的排列或布局与最顶部布线图案20的排列或布局基本相同。在一些实施例中,在平面图中,焊盘电极30具有矩形,矩形具有沿着行方向的第一边(宽度L3)和沿着列方向的第二边(宽度L4)。在一些实施例中,0.8≤L3/L4≤1.2,并且在其他实施例中,0.95≤L3/L4≤1.05(基本正方形)。在一些实施例中,焊盘电极30的矩形或正方形在平面图中具有圆角。在一些实施例中,L3和L4在从约2μm到10μm的范围内,并且在其他实施例中,在从约4μm到6μm的范围内。在一些实施例中,L3和L4分别小于L1和L2。
如图8B所示,钝化层40具有在焊盘电极30上方的峰和在焊盘电极30之间的谷。在一些实施例中,谷的底部位于最顶部布线图案20的顶部与焊盘电极30的顶部之间的水平处。当相邻的两行焊盘电极30(顶部介电层上方的上部部分)的中心线和相邻的两行最顶部布线图案20(两行焊盘电极30形成在其上)的中心线彼此基本对准(差异小于0.1μm)时,谷的底部位于最顶部布线图案20之间的间隔上方,如图8B所示。
在本公开的一些实施例中,如图9A所示,相邻的两列焊盘电极30的中心线从相邻的两列最顶部布线图案20的中心线例如向+行方向偏移。在一些实施例中,偏移量D1大于0.1μm。在一些实施例中,D1等于或大于S1/2(S1的一半),其中S1是在行方向上相邻的最顶部布线图案20之间的间隔(见图10)。当偏移量D1等于或大于S1/2时,相邻的两列焊盘电极30的中心线与最顶部布线图案的相邻列中的一列重叠,如图9A和图9B所示。因此,钝化层40的谷的底部也位于最顶部布线图案的相邻列中的一列的上方,如图9B所示。在一些实施例中,偏移量D1为S1/2+Δ,其中Δ在从约0.1μm到约1.0μm的范围内(例如,0.1μm、0.2μm、0.3μm、0.4μm或0.5μm)。
当在列方向上的列长度较长时,例如大于约200μm时,沿着在列方向上的两个列之间的间隔在钝化层40中形成长的谷。这样长的谷可能会在钝化层中造成裂纹45,如图10所示。然而,在图9A和图9B所示的本实施例中,由于可能是裂纹起源的谷的底部位于最顶部布线图案20上方,则裂纹45(如果形成)在最顶部布线图案20的表面处停止,并且因此,可以防止裂纹到达最顶层布线层20下方的电路区域。沿着列方向,裂纹可能会在相邻的最顶部布线图案20之间的间隔处渗透到顶部介电层22和ILD/IMD层中,由于相邻的最顶部布线图案20之间的间隔足够地小于最顶部布线图案20的尺寸,因此裂纹45不会渗透深入到顶层介电层22和/或ILD/IMD层中。在一些实施例中,裂纹45的底部位于在列方向上的最顶部布线图案之间的间隔中的最顶部布线图案20的顶面和底面之间。
在一些实施例中,最顶部布线图案20的宽度L11在从约2μm到10μm的范围内,并且在其他实施例中,在从约4μm到6μm的范围内。在一些实施例中,焊盘电极30的底部的宽度L21在从约1.2μm到6μm的范围内,并且在其他实施例中在,在从约2.4μm到3.6μm的范围内。在一些实施例中,焊盘电极30的最大宽度L22在从约1.6μm到8μm的范围内,并且在其他实施例中,在从约3.2μm到4.8μm的范围内。在一些实施例中,间隔S1在从约0.5μm到2.0μm的范围内,并且在其他实施例中,在从约0.8μm到1.2μm的范围内。
在一些实施例中,偏移量D1被设置为使得开口24的外边缘在最顶部布线图案20内。在一些实施例中,当图5所示的焊盘电极30的光刻胶图案35与开口24对准时,D1对应于开口24(见图3)的中心与最顶部布线图案20的中心之间的差异。换言之,焊盘电极30的下部部分(嵌入顶部介电层22中)和焊盘电极30的上部部分(顶部介电层22的上表面上方)基本彼此对准(在一些实施例中,重叠误差小于0.1μm)。在一些实施例中,D1等于或大于S1/2(S1的一半),并且等于或小于(L11-L21)/2。在一些实施例中,焊盘电极30的上部部分具有大于焊盘电极30的下部部分的厚度。
在其他实施例中,如图11所示,焊盘电极30的下部部分(嵌入顶部介电层22中)与最顶部布线层20基本对准(在一些实施例中,重叠误差小于0.1μm),并且焊盘电极30的上部部分以偏移量D1偏移。在一些实施例中,D1等于或大于S1/2(S1的一半),并且等于或小于(L22-L21')/2,其中宽度L21'为焊盘电极30的下部部分的顶部的宽度。在一些实施例中,D1等于或大于S1/2+Δ,其中Δ为约0.1μm。
在其他实施例中,焊盘电极30的下部部分和上部部分都相对于最顶部布线图案20偏移,使得焊盘电极30的上部部分从最顶部布线层20以量D1偏移。
图12示出了另一实施例,其中焊盘电极30具有倒锥形。与前述实施例类似,焊盘电极30相对于最顶部布线图案20偏移,使得相邻的两列焊盘电极30的中心线与一列或两列最顶部布线图案20重叠,两列焊盘电极30形成在最顶部布线图案20上。因此,钝化层40的谷恰好位于最顶部布线图案20上方。
如从图8A和图9A中理解的,图9A至图11中所示的结构是通过相对于最顶部布线图案20偏移开口24和焊盘电极30的光刻胶图案中的一者或两者来获得的。这样的图案偏移可以通过向使用原始光掩模的光刻装置输入套刻(overlay)调整值(不同于机器误差或除了机器误差(所谓的“套刻误差”之外))而实现,原始光掩模被设计为完美地对准下面的图案(例如,最顶部布线图案)。在这样的情况下,不需要制造用于图案化开口24和/或焊盘电极30的附加光掩模,并且通过使用光掩模形成的所有图案都以相同的量偏移。
在其他实施例中,制造具有有意的图案偏移的新光掩模,并且当形成光刻胶图案时没有套刻偏移(除了微小调整之外)输入到光刻装置中。在一些实施例中,仅偏移图案的某些必要部分。
图13和图14示出了根据本公开实施例的图案布局。
在一些实施例中,最顶部布线图案20和焊盘电极30不仅包括矩阵图案MX,还包括一个或多个岛状图案IL,如图13和图14所示。在一些实施例中,岛状图案IL与矩阵图案分开或者与最接近的图案分开距离L0,其中L0是矩阵排列的节距的两倍到十倍或更多倍。当形成钝化层40时,钝化层在岛状图案IL上方形成平缓的上表面轮廓,因此由于与相邻(例如,最近)图案的距离足够长,在岛状图案周围基本没有形成谷。
在一些实施例中,如图13所示,矩阵图案MX和岛状图案IL的焊盘电极30都相对于最顶部布线图案20在行方向上偏移。如图13所示,矩阵图案的相邻两列焊盘电极30的中心线CL在平面图中与两列最顶部布线图案20中的一列重叠。如上所述,这可以通过向使用原始光掩模或使用专门制造的光掩模的光刻装置输入套刻调整值而实现。在一些实施例中,如图13所示,最顶部布线图案20包括其上没有形成焊盘电极的一个或多个图案。
在其他实施例中,如图14所示,虽然矩阵图案MX的焊盘电极30的整体相对于最顶部布线图案20的整体在行方向上偏移,但是岛状图案IL的焊盘电极30基本与对应的最顶部布线图案20对准(没有偏移或偏移量小于0.1μm,这可能是由机器误差(所谓的“套刻误差”)引起)。如上所述,这可以通过使用专门制造的光掩模来实现。
在一些实施例中,不需要图案偏移的岛状图案包括具有小于100μm的行或列长度的小矩阵。在一些实施例中,如图13或图14所示的一个或多个岛状图案IL是设置在围绕半导体芯片的划线道上的伪图案(用于测量(套刻或对准)的图案或测试电路的部分)。
图15和图16示出了根据本公开实施例的图案布局。
在一些实施例中,最顶部布线图案20和焊盘电极30的图案矩阵为M×N排列,其中M和N为四或更大,和/或,行长度和/或列长度大于100μm。
在一些实施例中,如图15所示,焊盘电极30的整体矩阵仅在一个方向(例如行方向)上偏移,使得相邻的两列焊盘电极30的中心线CL与其上形成两列焊盘电极30的两列最顶部布线图案20中的一列重叠。在一些实施例中,焊盘电极30(特别是上部部分)的矩阵的中心(几何中心或重心)相对于最顶部布线图案20的矩阵的中心在一个方向上以偏移量偏移。
在其他实施例中,如图16所示,焊盘电极30的整个矩阵在行和列方向上偏移,使得焊盘电极30的相邻两列的中心线CL与两列最顶部布线图案20中的一列重叠,并且相邻的两行焊盘电极30的中心线CL'与两行最顶部布线图案20中的一行重叠。在一些实施例中,焊盘电极30(特别是上部部分)的矩阵的中心相对于最顶部布线图案20的矩阵的中心在两个方向上以偏移量偏移。
图17示出了根据本公开实施例的图案布局。
在一些实施例中,焊盘电极30围绕半导体芯片的外围排列,如图17所示。在一些实施例中,半导体芯片的外围或外围区域是与芯片区域(电路区域)和划线之间的边界距离500μm以内的区域。在一些实施例中,两列焊盘电极排列在半导体芯片的左侧和右侧,并且两行焊盘电极排列在半导体芯片的顶侧和底侧。
在一些实施例中,位于半导体芯片左侧和右侧处的焊盘电极30的列沿着行方向(从左到右)偏移,使得相邻的两列焊盘电极30的中心线与其上形成两列焊盘电极30的两列最顶部布线图案20中的一列重叠。在一些实施例中,位于半导体芯片顶部和底部处的焊盘电极30的行沿着列方向(从上到下)偏移,使得相邻的两行焊盘电极30的中心线与其上形成两行焊盘电极30的两行最顶部布线图案20中的一行重叠。
在一些实施例中,位于半导体芯片的左侧的焊盘电极30的列的偏移方向与位于右侧的焊盘电极30的列的偏移方向相同,例如,相对于最顶部布线图案向左,如图17所示。在其他实施例中,位于半导体芯片的左侧的焊盘电极30的列相对于最顶部布线图案的偏移方向与位于右侧的焊盘电极30的列的偏移方向不同。类似的布置应用于位于半导体芯片顶部和底部的焊盘电极的行。在一些实施例中,焊盘电极30相对于半导体芯片的四个侧的最顶部布线图案朝向半导体芯片外部偏移,并且在其他实施例中,焊盘电极相对于半导体芯片的四个侧的最顶部布线图案朝向半导体芯片内部偏移。
在一些实施例中,焊盘电极30的行和焊盘电极30的列都类似于图16在行方向和列方向上相对于最顶部布线图案偏移。
图18示出了根据本公开实施例的制造半导体器件的流程图。可以理解,可以在图18所示的工艺之前、期间和之后提供附加的操作,并且对于方法的其他实施例,可以替换或消除下面描述的一些操作。操作/工艺的顺序可以互换。
在以上实施例中,图案20是最顶部布线图案,最顶部布线图案是在垂直方向上距离焊盘电极最近的布线层并且连接到焊盘电极,并且图案30是焊盘电极。然而,配置不限于此。在其他实施例中,图案30是其上形成凸块电极的凸块下金属化(UBM)层。
在工艺框S801处,在衬底上方的ILD层中形成布线图案,例如,如上所描述的最顶部布线图案20。在工艺框S802处,在ILD层中形成的布线图案上方形成第一介电层,例如,如上所描述的顶部介电层22。在工艺框S803处,在第一介电层上方形成用于形成开口/窗口(例如,如上所描述的开口24)的第一光刻胶图案。在一些实施例中,在光刻工艺中,除了由对准工艺的缺陷引起的套刻补偿值之外,还实施套刻偏移量OL1。在一些实施例中,在光刻工艺中实施小于0.1μm的套刻偏移量OL1。在一些实施例中,是相对于布线图案设置OL1。在工艺框S804处,使用第一光刻胶图案作为蚀刻掩模来图案化第一介电层,以在布线图案上方形成开口,例如,如上所描述的开口24。在工艺框S805处,在开口中和第一介电层上形成毯式导电层,例如如上所描述的导电层30L。在工艺框S806处,在导电层上方形成用于形成电极(例如,如上所描述的焊盘电极30)的第二光刻胶图案。在一些实施例中,在光刻工艺中,除了由对准工艺的缺陷引起的套刻补偿值(约小于0.1μm)之外,还实施套刻偏移量OL2。在工艺框S807处,使用第二光刻胶图案作为蚀刻掩模图来案化毯式导电层以形成电极,例如如上所描述的焊盘电极30。在工艺框S808处,在第一介电层和图案化的电极上方形成第二介电层,例如,如上所描述的钝化层40。
在一些实施例中,工艺框S804和S806中使用的光掩模中的一者或两者被设计为使得电极或者电极和开口与对应的布线图案对准。在这种情况下,套刻偏移量OL2相对于布线图案被设置为大于0.1μm,或被设置为S1/2+Δ,其中S1是布线图案之间的间隔,并且Δ在约0.1μm到约1.0μm的范围内。在一些实施例中,OL1为零。在其他实施例中,套刻偏移量OL1+OL2的和相对于布线图案被设置为大于0.1μm,或被设置为S1/2+Δ,其中S1是布线图案之间的间隔,并且当相对于开口设置OL2时Δ在从约0.1μm到约1.0μm的范围内。
在一些实施例中,工艺框S804和S806中使用的光掩模中的一者或两者被设计为使得电极相对于对应的布线图案偏移。在这种情况下,OL1和OL2都为零,并且如果需要,仅向光刻装置输入由对准工艺的缺陷引起的套刻补偿值。
图19示出了根据本公开实施例的制造光掩模的流程图。可以理解,可以在图19所示的工艺之前、期间和之后提供附加的操作,对于方法的其他实施例,可以替换或消除下面描述的一些操作。操作/工艺的顺序可以互换。
在工艺框S901处,准备开口图案(例如开口24)的原始布局(第一光刻胶图案25)和电极图案(例如焊盘电极30)的原始布局。在原始布局中,开口图案和电极图案被设计为与下面的图案(诸如在其上形成开口的布线图案,例如最顶部布线图案20)对准。类似于图8A的实施例中所示的配置,相邻的两行电极图案的中心线与相邻的两行布线图案的中心线对准。
在工艺框S902处,搜索并检测将在上覆的绝缘层处创建长的谷(例如,超过200μm)的一组或多组电极图案(行和/或列)。在一些实施例中,当电极图案排列成至少两行和/或两列、相邻的行/列之间的间隔在预定范围内并且行/列的长度大于阈值长度时,确定电极图案组会在上覆的绝缘层处创建长的谷。这可以通过图案的一个或多个尺寸调整和/或布尔操作来实现。例如,通过在一个方向(两侧)上扩展图案,消除了尺寸小于阈值长度的间隔,从而形成连续图案,然后确定连续图案的长度大于阈值长度。在一些实施例中,预定范围是从约0.5μm到2.0μm,并且在其他实施例中是从约0.8μm到1.2μm。在一些实施例中,阈值长度为约200μm,并且在其他实施例中为约400μm。
在工艺框S903处,当找到关键的图案组时,在穿过谷(其将以其他方式出现)的方向上以偏移量偏移电极图案组。偏移量被确定为使得电极图案的相邻的行/列的中心线与下面的布线图案重叠,如以上所解释的。
在一些实施例中,在工艺框S904处,与电极图案的偏移量相同或不同的偏移量偏移对应于关键的电极图案组的开口图案。
然后,在工艺框S905处,将修改后的布局作为掩模数据输出,并且根据掩模数据制造一个或多个光掩模,并且制造的光掩模例如用于图18所示的工艺中。
在一些实施例中,图19中所示的工艺(特别是S901-S904)可以是由包括一个或多个处理器和存储程序的存储介质(存储器)的计算机系统执行。当执行程序时,被执行的程序可以执行图19所示的操作的至少部分。
在一些实施例中,工艺框S901-S904中的一个或多个由计算机系统执行。在一些实施例中,计算机系统配备有计算机,计算机包括光盘只读存储器(例如,CD-ROM或DVD-ROM)驱动器和磁盘驱动器、键盘、鼠标以及监视器。除了光盘驱动器和磁盘驱动器之外,计算机还配备有:一个或多个处理器(诸如微处理单元(MPU)),存储诸如启动程序的程序的ROM,连接到MPU并在其中临时存储应用程序的命令并提供临时存储区域的随机存取存储器(RAM),其中存储应用程序、系统程序和数据的硬盘,以及连接MPU、ROM等的总线。注意,计算机系统可以包括用于提供到LAN的连接的网卡(未示出)。使计算机系统执行用于执行上述掩码数据生成操作的装置的功能的程序可以存储在插入到光盘驱动器或磁盘驱动器中的光盘或磁盘中,并被发送到硬盘。可选地,程序可以通过网络(未示出)传输到计算机并存储在硬盘中。在执行时,程序被加载到RAM中。程序可以从光盘或磁盘加载,也可以直接从网络加载。程序不一定必须包括例如操作系统(OS)或第三方程序以使计算机执行前述实施例中的光掩模数据生成装置的功能。程序可以仅包括命令部分以在受控模式下调用适当的功能(模块)并获得期望的结果。
图20示出了本实施例的有益效果。制作了具有不同的行/列长度(“PRL”)和不同偏移量的各种样本,并且计数了钝化层(200nm的氮化硅)中的裂纹到达最顶层布线图案下方的情况。相邻的最顶部布线层之间的图案间隔S1为0.75μm。
如图20所示,当行/列的长度较长(例如,400μm或更大)时,穿透到最顶部布线图案下方的裂纹发生(约0.2%),但是根据本公开实施例,当引入了足够的套刻(OVL)偏移时,消除了这样的裂纹。
在前述实施例中,即使由焊盘电极图案的行和/或列的形貌形成钝化层中的长的谷部分(可能是裂纹的起源),但是因为焊盘电极图案的行和/或列相对于下面的布线图案偏移,使得谷位于下面的布线图案上方,可能防止裂纹到穿透布线图案下方。在一些实施例中,这种图案偏移是通过在曝光装置中引入套刻偏移来实现的,并且不需要新的光掩模。
应当理解,并非所有优点都必须在本文中讨论,所有实施例或示例不需要特定的优点,并且其他实施例或示例可以提供不同的优点。
根据本公开的一方面,在制造半导体器件的方法中,形成下部导电图案。下部导电图案包括多个导电图案在第一方向上排列的第一列图案和多个导电图案在第一方向上排列的第二列图案,并且在平面图中,第一列和第二列在与第一方向交叉的第二方向上彼此相邻。形成上部导电图案。上部导电图案包括多个导电图案在第一方向上排列的第三列图案和多个导电图案在第一方向上排列的第四列图案,并且在平面图中,第三列和第四列在第二方向上彼此相邻。第一列和第三列在平面图中至少部分地彼此重叠,第二列和第四列在平面图中至少部分地彼此重叠,并且,上部导电图案形成为使得在第一列和第二列的第一方向上延伸的第一中心线从第三列和第四列的在第一方向上延伸的第二中心线在第二方向上以大于0.1μm的偏移量偏移。在前述或以下实施例中的一个或多个中,第二中心线在平面图中与第二列重叠。在前述或以下实施例中的一个或多个中,形成上部导电图案包括通过光刻装置形成与上部导电图案对应的光刻胶图案,并且在光刻操作中,向光刻装置输入在第二方向上的非零的套刻偏移,使得在第一列和第二列的方向上延伸的第一中心线从在第三列和第四列的方向上延伸的第二中心线在第二方向上偏移。在前述或以下实施例中的一个或多个中,还在上部导电图案上方形成绝缘层。在前述或以下实施例中的一个或多个中,绝缘层包括在第三列和第四列上方的峰以及在第三列和第四列之间的谷。在前述或以下实施例中的一个或多个中,谷与第二列重叠。在前述或以下实施例中的一个或多个中,绝缘层包括从谷到第二列的多个导电图案中的至少一个的裂纹。在前述或以下实施例中的一个或多个中,第一列和第二列之间的间隔小于第三列和第四列之间的间隔。在前述或以下实施例中的一个或多个中,偏移量大于第一列和第二列之间的间隔的一半。在前述或以下的一个或多个实施例中,第一列和第二列之间的间隔在从0.8μm到1.2μm的范围内,第三列和第四列之间的间隔在从1.6μm到2.4μm的范围内,并且偏移量在从0.8μm到1.0μm的范围内。在前述或以下的一个或多个实施例中,第一列的总长度大于200μm。在前述或以下的一个或多个实施例中,第一列和第二列中的多个导电图案中的每个具有带圆角的正方形形状。在前述或以下实施例中的一个或多个中,第三列和第四列中的多个导电图案中的每个在平面图中具有带圆角的正方形形状。
根据本公开的另一方面,在制造半导体器件的方法中,形成在第一方向上排列并且嵌入第一介电层中的多个第一导电图案。在多个第一导电图案和第一介电层上方形成第二介电层。通过第一图案化操作在第二介电层中形成多个开口,每个开口位于多个第一导电图案中的对应一个上方。在第二介电层上方和多个开口中形成导电材料的毯式层。通过第二图案化操作图案化导电材料的毯式层以形成与多个第一导电图案中的对应一个连接的多个第二导电图案。在多个第二导电图案上方形成第三介电层。在第一图案化操作中,多个开口作为整体在第一方向上从多个第一导电图案作为整体在平面图中以大于0.1μm的偏移量偏移。在前述或以下实施例中的一个或多个中,在平面图中在第一方向上的多个第一导电图案中的相邻两个的中心线从在第一方向上的多个第二导电图案中的相邻两个的中心线在第一方向上以偏移量偏移。在前述或以下实施例中的一个或多个中,多个第一导电图案的厚度大于第二介电层上方的多个第二导电图案的厚度。在前述或以下实施例的一个或多个中,多个第一导电图案的厚度在从3μm到5μm的范围内,第二介电层上方的多个第二导电图案的厚度在从1.0微米到3.0微米的范围内。在前述或以下实施例中的一个或多个中,多个开口中的每个的顶部尺寸小于多个第二导电图案中的每个的最大宽度。
根据本公开的另一个方面,在一种制造半导体器件的方法中,形成以列-行矩阵排列的下部导电图案,其中相邻列之间的第一间隔在从0.8μm到1.2μm的范围内。在下部导电图案上方形成第一介电层。上部导电图案形成在下部导电图案上方并且以列-行矩阵排列,并且相邻列之间的第二间隔大于第一间隔。在平面图中,下部导电图案的相邻列的中心线从多个上部导电图案的相邻两列的中心线在行方向上以大于0.1μm的偏移量偏移。在前述或以下实施例中的一个或多个中,第一岛状图案设置在与下部导电图案相同的水平处,第二岛状图案设置在与上部导电图案相同的水平处,并且第一岛状图案的中心与第二岛状图案的中心对准。
据本公开的另一方面,一种半导体器件包括:半导体电路,设置在衬底上方;下部导电图案,设置在半导体电路上方并且电耦合到半导体电路,下部导电图案包括多个导电图案在第一方向上排列的图案的第一列和多个导电图案在第一方向上排列的图案的第二列,第一列和第二列在平面图中在与第一方向交叉的第二方向上相邻;第一介电层,设置在下部导电图案上方;上部导电图案,设置在下部导电图案上方,上部导电图案包括多个导电图案在第一方向上排列的图案的第三列和多个导电图案在第一方向上排列的图案的第四列,第三列和第四列在平面图中在第二方向上相邻;以及第二介电层,设置在上部导电图案上方,其中:在平面图中,在第一列和第二列之间在第一方向上延伸的第一中心线从在第三列和第四列之间在第一方向上延伸的第二中心线在第二方向上偏移。在前述或以下实施例中的一个或多个中,第二中心线与第一列或第二列中的一个重叠。
据本公开的另一方面,一种半导体器件包括:半导体电路,设置在衬底上方;下部导电图案,设置在半导体电路上方并且电耦合到半导体电路,下部导电图案包括多个导电图案在第一方向上排列的图案的第一列和多个导电图案在第一方向上排列的图案的第二列,第一列和第二列在平面图中在与第一方向交叉的第二方向上相邻;第一介电层,设置在下部导电图案上方;上部导电图案,设置在下部导电图案上方,上部导电图案包括多个导电图案在第一方向上排列的图案的第三列和多个导电图案在第一方向上排列的图案的第四列,第三列和第四列在平面图中在第二方向上相邻;以及第二介电层,设置在上部导电图案上方。在平面图中,在第一列和第二列之间在第一方向上延伸的第一中心线从在第三列和第四列之间在第一方向上延伸的第二中心线在第二方向上以大于0.1μm的偏移量偏移。在前述或以下实施例中的一个或多个中,第二中心线与第一列或第二列中的一个重叠。在前述或以下实施例中的一个或多个中,偏移量大于S/2,其中S是第一列和第二列之间的间隔。在前述或以下实施例中的一个或多个中,偏移量大于S/2+0.1μm。在前述或以下实施例中的一个或多个中,S在从0.8μm到1.2μm的范围内。在前述或以下实施例中的一个或多个中,第二介电层包括位于第三列和第四列上方的峰以及位于第三列和第四列之间的谷。在前述或以下实施例中的一个或多个中,在平面图中谷与第一列或第二列中的一个重叠。在前述或以下实施例中的一个或多个中,第二介电层包括从谷到第二列的多个导电图案中的至少一个的裂纹。在前述或以下实施例中的一个或多个中,裂纹不穿透到下部导电图案的底部以下。在前述或以下实施例中的一个或多个中,下部导电图案在平面图中具有矩形形状,矩形形状具有沿着第一方向的宽度L1的第一边和沿着第二方向的宽度L2的第二边,并且0.95≤L1/L2≤1.05。在前述或以下实施例中的一个或多个中,上部导电图案在平面图中具有矩形形状,矩形形状具有沿着第一方向的宽度L3的第一边和沿着第二方向的宽度L4的第二边,并且0.95≤L3/L4≤1.05。在前述或以下实施例中的一个或多个中,宽度L3和L4小于宽度L1和L2。
根据本公开的另一方面,一种半导体器件包括:半导体电路,设置在衬底上方;布线图案,嵌入第一层间介电(ILD)层中,并且设置在半导体电路上方并电耦合到半导体电路;第二ILD层,设置在布线图案上方;焊盘电极,分别设置在布线图案上方并且连接到布线图案;以及钝化层,设置在焊盘电极上方。焊盘电极中的每个包括嵌入在第二ILD层中的下部部分和位于第二ILD层的表面上方的上部部分。布线图案包括图案的第一矩阵,并且焊盘电极的上部部分包括图案的第二矩阵。第二矩阵的中心在平面图中相对于第一矩阵的中心以大于0.1μm的偏移量横向偏移。在前述或以下实施例中的一个或多个中,第一矩阵和第二矩阵分别为M×N矩阵,其中M和N为自然数,M或N中的至少一个为4或更大,并且M×N矩阵的列长度和列长度中的至少一个大于100μm。在一个或多个前述或以下实施例中,M为2且N为4或更大。在前述或以下实施例中的一个或多个中,偏移量大于S/2+0.1μm,其中S为相邻布线图案之间的间隔。在前述或以下实施例中的一个或多个中,布线图案由Cu或以Cu为主的Cu合金制成,并且焊盘电极由Al或以Al为主的Al合金制成。
根据本公开的另一方面,一种半导体器件包括:半导体电路,设置在衬底上方;布线图案,设置在外围区域上,其中布线图案嵌入在第一层间介电(ILD)层中,并且设置在半导体电路上方并电耦合到半导体电路;第二ILD层,设置在布线图案上方;焊盘电极,设置在外围区域上,并且分别设置在布线图案上方并且连接到布线图案;以及钝化层,设置在焊盘电极上方。布线图案包括2×N矩阵,焊盘电极包括2×N矩阵,其中N为4或更大的自然数,第二矩阵的中心横向相对于第一矩阵的中心在平面图中朝向外围区域外部或外围区域内部以大于0.1μm的偏移量偏移。在前述或以下实施例中的一个或多个中,外围区域具有框架形状。在前述或以下实施例中的一个或多个中,偏移量大于S/2+0.1μm,其中S为相邻布线图案之间的间隔。
上述概述了几个实施例的特征,以便本领域技术人员可以更好地理解本公开的各个方面。本领域技术人员应当理解,他们可以容易地使用本公开作为设计或修改用于实现本文所介绍的实施例的相同目的和/或实现其相同优点的其它过程和结构的基础。本领域技术人员还应当认识到,此类等效结构不背离本发明的精神和范围,并且它们可以在不背离本发明的精神和范围的情况下在本发明中进行各种改变、替换以及改变。
Claims (10)
1.一种制造半导体器件的方法,包括:
形成下部导电图案,所述下部导电图案包括多个导电图案在第一方向上排列的第一列图案和多个导电图案在所述第一方向上排列的第二列图案,所述第一列和所述第二列在与所述第一方向交叉的第二方向上彼此相邻;以及
形成上部导电图案,所述上部导电图案包括多个导电图案在所述第一方向上排列的第三列图案和多个导电图案在所述第一方向上排列的第四列图案,所述第三列和所述第四列在所述第二方向上彼此相邻,其中:
所述第一列和所述第三列在平面图中至少部分地彼此重叠,
所述第二列和所述第四列在平面图中至少部分地彼此重叠,并且
所述上部导电图案形成为使得在所述第一列和所述第二列的所述第一方向上延伸的第一中心线从在所述第三列和所述第四列的所述第一方向上延伸的第二中心线在所述第二方向上以大于0.1μm的偏移量偏移。
2.根据权利要求1所述的方法,其中,所述第二中心线在平面图中与所述第二列重叠。
3.根据权利要求1所述的方法,其中:
所述形成上部导电图案包括通过光刻装置形成与所述上部导电图案对应的光刻胶图案,并且
在光刻操作中,向所述光刻装置输入在所述第二方向上的非零的套刻偏移,使得在所述第一列和所述第二列的方向上延伸的所述第一中心线从在所述第三列和所述第四列的方向上延伸的所述第二中心线在所述第二方向上偏移。
4.根据权利要求1所述的方法,还包括在所述上部导电图案上方形成绝缘层。
5.根据权利要求4所述的方法,其中,所述绝缘层包括在所述第三列和所述第四列上方的峰以及在所述第三列和所述第四列之间的谷。
6.根据权利要求5所述的方法,其中,所述谷与所述第二列在平面图中重叠。
7.根据权利要求6所述的方法,其中,所述绝缘层包括从所述谷到所述第二列的所述多个导电图案中的至少一个的裂纹。
8.根据权利要求1所述的方法,其中,所述第一列和所述第二列之间的间隔小于所述第三列和所述第四列之间的间隔。
9.一种制造半导体器件的方法,包括:
形成在第一方向上排列并且嵌入第一介电层中的多个第一导电图案;
在所述多个第一导电图案和所述第一介电层上方形成第二介电层;
通过第一图案化操作在所述第二介电层中形成多个开口,每个开口位于所述多个第一导电图案中的对应一个上方;
在所述第二介电层上方和所述多个开口中形成导电材料的毯式层;
通过第二图案化操作图案化所述导电材料的毯式层以形成与所述多个第一导电图案中的对应一个连接的多个第二导电图案;以及
在所述多个第二导电图案上方形成第三介电层,
其中,在所述第一图案化操作中,在平面图中所述多个开口整体在所述第一方向上从所述多个第一导电图案整体以大于0.1μm的偏移量偏移。
10.一种半导体器件,包括:
半导体电路,设置在衬底上方;
下部导电图案,设置在所述半导体电路上方并且电耦合到所述半导体电路,所述下部导电图案包括多个导电图案在第一方向上排列的图案的第一列和多个导电图案在所述第一方向上排列的图案的第二列,所述第一列和所述第二列在平面图中在与所述第一方向交叉的第二方向上相邻;
第一介电层,设置在所述下部导电图案上方;
上部导电图案,设置在所述下部导电图案上方,所述上部导电图案包括多个导电图案在所述第一方向上排列的图案的第三列和多个导电图案在所述第一方向上排列的图案的第四列,所述第三列和所述第四列在平面图中在所述第二方向上相邻;以及
第二介电层,设置在所述上部导电图案上方,其中:
在平面图中,在所述第一列和所述第二列之间在所述第一方向上延伸的第一中心线从在所述第三列和所述第四列之间在所述第一方向上延伸的第二中心线在所述第二方向上偏移。
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US8446007B2 (en) * | 2009-10-20 | 2013-05-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-uniform alignment of wafer bumps with substrate solders |
JP5493166B2 (ja) * | 2009-12-03 | 2014-05-14 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
US8473072B2 (en) * | 2010-06-08 | 2013-06-25 | Axelgaard Manufacturing Company, Ltd. | Customizable medical electrode |
CN110024017B (zh) * | 2016-12-01 | 2021-05-04 | 夏普株式会社 | 连接用配线 |
US10290596B2 (en) * | 2016-12-14 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a passivation layer and method of making the same |
JP6869209B2 (ja) * | 2018-07-20 | 2021-05-12 | 日本特殊陶業株式会社 | 配線基板 |
-
2022
- 2022-01-28 US US17/587,605 patent/US20230021655A1/en active Pending
- 2022-02-07 DE DE102022102730.9A patent/DE102022102730A1/de active Pending
- 2022-03-29 KR KR1020220039183A patent/KR20230015263A/ko not_active Application Discontinuation
- 2022-06-10 CN CN202210658260.2A patent/CN115346917A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115497842A (zh) * | 2022-11-17 | 2022-12-20 | 合肥新晶集成电路有限公司 | 半导体结构的制备方法及半导体结构 |
Also Published As
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TW202305945A (zh) | 2023-02-01 |
DE102022102730A1 (de) | 2023-01-26 |
KR20230015263A (ko) | 2023-01-31 |
US20230021655A1 (en) | 2023-01-26 |
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