CN110660685A - 制作集成电路的方法 - Google Patents
制作集成电路的方法 Download PDFInfo
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- CN110660685A CN110660685A CN201910538203.9A CN201910538203A CN110660685A CN 110660685 A CN110660685 A CN 110660685A CN 201910538203 A CN201910538203 A CN 201910538203A CN 110660685 A CN110660685 A CN 110660685A
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- layer
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- nitride
- oxide
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
此处提供半导体装置、集成电路、与其形成方法。在一实施例中,制作集成电路的方法包括:形成钝化层于第一接点结构上;形成第二接点结构于钝化层上并穿过钝化层,以电性连接至第一接点结构;以及形成多层钝化结构于第二接点结构与钝化层上。形成多层钝化结构的步骤包括沉积第一氮化物层、沉积氧化物层于第一氮化物层上、以及沉积第二氮化物层于氧化物层上。
Description
技术领域
本发明实施例关于半导体装置,更特别关于其多层钝化结构。
背景技术
半导体集成电路产业已经历快速成长。集成电路材料与设计的技术进展,使每一代的集成电路比前一代具有更小且更复杂的电路。然而这些进展亦增加制造与处理集成电路的复杂性。为实现这些进展,制造与处理集成电路的方法亦需类似进展。在集成电路演进中,功能密度(比如单位芯片面积的内连线装置数目)通常随着几何尺寸(比如采用的制作制程所能产生的最小构件)缩小而增加。
举例来说,集成电路形成于半导体基板上。每一集成电路芯片更贴合(如接合)至电路板,比如电子产品中的印刷电路板。在现有技术中,芯片的多种接合垫经由打线接合连接至电路板。在进阶技术中,翻转电路芯片并将电路芯片直接接合至电路板以降低成本。在此技术中,导电金属线路的重布线层形成于芯片上,以自芯片的边缘至中心重新布线接合连接。钝化物层耦接至重布线层,以保护半导体表面免于电性与化学污染。然而一些钝化层易于产生应力与裂缝,且可能导致潜在的空洞于相邻的金属接点之间。虽然现有钝化层与其制作方法一般适用于其发展目的,但无法完全适用于任何方面。
发明内容
本发明一实施例提供的制作集成电路的方法,包括:形成钝化层于第一接点结构上,且钝化层包括介电层;形成第二接点结构于钝化层上并穿过钝化层,且第二接点结构电性连接至第一接点结构;以及形成多层钝化结构于第二接点结构与钝化层上,其中形成多层钝化结构的步骤包括沉积第一氮化物层、沉积氧化物层于第一氮化物层上、以及沉积第二氮化物层于氧化物层上。
本发明一实施例提供的半导体装置,包括:下侧接点结构,位于基板上;介电层,位于下侧接点结构上;上侧接点结构,位于介电层上并穿过介电层,且上侧接点结构电性连接至下侧接点结构;以及钝化结构,位于第二接点结构与介电层上,其中钝化结构包括第一氮化物层、第二氮化物层、与位于第一氮化物层与第二氮化物层之间的氧化物层。
本发明一实施例提供的方法,包括:形成顶金属接点于半导体基板上;沉积第一介电层于顶金属接点上;形成金属-绝缘层-金属结构于第一介电层上;沉积第二介电层于金属-绝缘层-金属结构上;形成金属通孔,其电性耦接至金属-绝缘层-金属结构及顶金属接点;形成钝化结构于金属接点及第二介电层上,其形成钝化结构的步骤包括:沉积第一氮化物层于金属通孔与第二介电层上;沉积氧化物层于第一氮化物层上;以及沉积第二氮化物层于氧化物层上;以及形成接合垫,其电性耦接至金属通孔。
附图说明
图1是本发明实施例中,制作半导体装置所用的方法的流程图。
图2A、2B、2C、2D、2E、2F、2G、2H、2I、2J、2K、2L、2M、2N、2O、2P、2Q、2R、2S、2T、与2U是本发明实施例中,半导体装置于多种制作阶段的剖视图。
其中,附图标记说明如下:
A1、A2 角度
Pc 间隙距离
T 锥形剖面
Tc 厚度
W 墙部
10 方法
12、14、16、18、20、22、24、26、28、30、32 步骤
100 半导体装置
102 基板
110 内连线层
120 碳化物层
130、150、184 氧化物层
140 蚀刻停止层
152 氮氧化硅层
153、154、155、175、176、177 接点结构
156、182、186 氮化物层
158、164、167、168 介电层
160 金属-绝缘层-金属结构
162 电容底金属层
166 电容中间金属层
169 电容顶金属层
170、180 多层钝化结构
171、172、173 开口
178 阻障层
188 材料层
190 接合垫
192 凸块下金属层
194 凸块层
196 焊料层
198 裂缝
具体实施方式
可以理解的是,下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件与排列的实施例是用以简化本发明内容而非局限本发明。举例来说,形成第一构件于第二构件上的叙述包含两者直接接触的实施例,或两者之间隔有其他额外构件而非直接接触的实施例。此外,本发明实施例的结构形成于另一结构上、连接至另一结构、及/或耦接至另一结构中,结构可直接接触另一结构,或可形成额外结构于结构及另一结构之间(即结构未接触另一结构)。此外,本发明的多个实例可重复采用相同标号以求简洁,但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。此外,可由不同比例任意示出多种结构使附图简化清楚。
此外,空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件,而非局限于图示方向。元件亦可转动90°或其他角度,因此方向性用语仅用以说明图示中的方向。
此外,当数值或数值范围的描述有“约”、“近似”、或类似用语时,除非特别说明否则其包含所述数值的+/-10%。举例来说,用语“约5nm”包含的尺寸范围介于4.5nm至5.5nm之间。
在许多集成电路芯片上形成导电金属线路的重布线层,以自芯片的边缘至中心重新布线接合连接。钝化层耦接至重布线层,以保护半导体表面免于电性与化学污染。然而一些钝化层采用阻障材料所组成的单一层,其易产生应力与裂缝。
本发明实施例提供多层钝化结构与其形成方法,以解决上述问题。在一些实施例中,钝化结构并非具有单一钝化层,而是具有至少三层,比如包括两个氮化硅层与一个夹设于氮化硅层之间的氧化物层。在一例中,形成三层钝化结构于重布线层上的方法,可包括经由化学气相沉积或物理气相沉积法沉积第一氮化硅层、经由高密度等离子体沉积法沉积氧化物层于第一氮化硅层上、以及经由化学气相沉积或物理气相沉积法沉积第二氮化硅层于氧化物层上。由于氧化物层比氮化硅较不硬脆,三层的钝化结构较不易造成裂缝与应力。如此一来,最终的半导体装置具有较佳可信度及/或较高效能。
本发明多种实施例将搭配附图详述如下。图1是本发明实施例中,制作半导体装置100所用的方法10的流程图。方法10仅用以举例,而非局限本发明实施例至方法10中实际说明的内容。在方法10之前、之中、与之后可进行额外步骤,且方法的其他实施例可置换、省略、或调换一些所述步骤。此处不详述所有步骤以简化说明。方法10搭配图2A至2U说明如下,其为本发明实施例的半导体装置100在不同制作阶段的部分剖视图。
在方法10一开始的步骤12中(图1),提供的半导体装置(或半导体结构)100已具有多种层状物形成其上。如图2A所示,半导体装置100一开始包含基板102,其组成可为硅或其他半导体材料如锗。基板102亦可包含半导体化合物如碳化硅、砷化镓、砷化铟、或磷化铟。在一些实施例中,基板102可包括半导体合金如硅锗、碳化硅锗、磷砷化镓、或磷化镓铟。在一些实施例中,基板102可包括外延层,比如基体半导体上的外延层。多种微电子构件可形成于基板102之中或之上,且微电子构件可为包括源极/漏极及/或栅极的晶体管构件、包括浅沟槽隔离的隔离结构、或任何其他合适构件。
半导体装置100亦包含内连线层110。内连线层110可为多层内连线结构中的一内连线层,其可形成于基板102上并包括多个图案化的介电层与导电层,以提供半导体装置100的多种微电子构件之间的内连线(如打线)。在内连线层110与基板102之间可为中间层或中间构件,但未图示这些层或构件以简化附图。在一实施例中,内连线层110的厚度介于约169nm至约230nm之间。
内连线层110可包含多个导电构件,以及部分地或完全地围绕导电构件的层间介电构件。导电构件可包含接点、通孔、或金属线路。层间介电构件可为含硅的氧化物材料,其硅以多种合适的形式存在。在一例中,层间介电构件包括氧化硅或低介电常数的介电材料(其介电常数小于氧化硅的介电常数如4)。在一些实施例中,低介电常数的介电材料包括孔洞状的有机硅酸盐薄膜如碳氢氧化硅、四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃、掺杂氧化硅(如硼磷硅酸盐玻璃、掺杂氟的硅酸盐玻璃、磷硅酸盐玻璃、掺杂氟的氧化硅、掺杂碳的氧化硅)、孔洞状的氧化硅、孔洞状的掺杂碳的氧化硅、碳氮化硅、碳氮氧化硅、旋转涂布的硅为主的聚合物介电层、或上述的组合。
在一实施例中,碳化物层120沉积于内连线层110上。沉积制程包含化学气相沉积、物理气相沉积、原子层沉积、或上述的组合。在一些实施例中,碳化物层120一般具有一致的厚度,其介于约45nm至约70nm之间。碳化物层120可采用任何合适种类的碳化物材料,比如碳化硅。
在一实施例中,氧化物层130沉积于碳化物层120上。上述沉积方法可蔡用任何合适的沉积制程,包括化学气相沉积、物理气相沉积、原子层沉积、或上述的组合。在一些实施例中,氧化物层130包含未掺杂的氧化硅。在一实施例中,内连线层110、碳化物层120、与氧化物层130可取代为一或多个内连线结构。
在一实施例中,蚀刻停止层140沉积于氧化物层130上。在一些实施例中,蚀刻停止层140的厚度介于约45nm至约55nm之间。蚀刻停止层140可包含碳氮化硅、碳氮氧化硅、碳化硅、氮化硅、或上述的组合。
另一氧化物层150可沉积于蚀刻停止层140上。在一些实施例中,氧化物层150包括未掺杂的氧化硅。在一些实施例中,氧化物层150的厚度介于约800nm至约1000nm之间。
接着在方法10的步骤14中(图1),图案化氧化物层150以形成沟槽于其中。如图2B至2E所示,图案化氧化物层150的步骤关于多重制程。如图2B所示,沉积氮氧化硅层152于氧化物层150上。在一些实施例中,氮氧化硅层152的厚度介于约54nm至约66nm之间。如图2C所示,可采用光微影制程图案化氮氧化硅层152。如图2D所示,采用氮氧化硅层152作为蚀刻遮罩,蚀刻氧化物层150以形成沟槽于其中。如图2E所示移除作为蚀刻遮罩的氮氧化硅层152之后,保留图案化的氧化物层150。
如图2F所示,方法10的步骤16(图1)形成一或多个下侧的接点结构(如接点结构153、154、与155)于氧化物层150的沟槽中。虽然接点结构153、154、与155位于下方位置(与下述的其他接点结构相较),接点结构153、154、与155有时可称作顶金属接点,因其可位于晶体管结构(未图示)上。此外,接点结构有时称作金属接点、通孔、或金属线路。每一接点结构包括阻障层与金属填充层。因此形成接点结构153、154、与155的方法关于多重制程。在一些实施例中,在每一金属接点形成阻障层,接着形成金属填充层于阻障层上。在一些实施例中,阻障层包括氮化钛、钽、氮化钽、或上述的组合。在一些实施例中,金属填充层包括金属或金属合金,比如铜、钴、镍、铝、钨、钛、或上述的组合。在一些实施例中,以沉积或电镀形成金属填充层,接着进行化学机械研磨制程。在一实施例中,化学机械研磨制程亦移除氧化物层150其约5%至约10%的厚度。
如图2G所示,方法10的步骤18(图1)沉积氮化物层156于接点结构153、154、与155上。在一些实施例中,氮化物层156的厚度介于约65nm至约85nm之间。氮化物层156可包含碳氮化硅、氮化硅、及/或可保护接点结构153、154、与155免于氧化的其他合适材料。步骤18亦沉积介电层158于氮化物层156上。在一些实施例中,介电层158的厚度介于约300nm至约500nm之间。介电层158可包含氧化物材料,比如未掺杂的氧化硅或其他合适材料。
在方法10的步骤20中,形成金属-绝缘层-金属结构160于介电层158上。如图2H与2I所示,形成金属-绝缘层-金属结构160的方法关于多重制程。如图2H所示,形成图案化的电容底金属层162于介电层158上。形成电容底金属层162的步骤本身可关于多重制程,比如沉积、光微影、显影、及/或蚀刻等制程。可对电容底金属层162进行表面处理,比如采用一氧化二氮气体的侧壁钝化制程。在一些实施例中,电容底金属层162的厚度介于约35nm至约45nm之间。如图2I所示,介电层164形成于电容底金属层162上。在一实施例中,介电层164沉积于半导体装置100上并具有通常一致的厚度,比如在电容底金属层162的上表面与侧壁表面上具有大致相同的厚度。如图2J所示,图案化的电容中间金属层166形成于介电层164上。电容中间金属层166的形成方法可与电容底金属层162的形成方法类似,但电容中间金属层166的图案与电容底金属层162的图案不同。如图2K所示,介电层168形成于电容中间金属层166上。在一实施例中,沉积的介电层168在半导体装置100的上表面上具有通常一致的厚度,比如在电容中间金属层166的上表面与侧壁表面上具有大致相同的厚度。如图2L所示,图案化的电容顶金属层169形成于介电层168上。电容顶金属层169的形成方法可与电容中间金属层166或电容底金属层162的形成方法类似,但电容顶金属层169的图案不同于电容中间金属层166或电容底金属层162的图案。
如图2L所示,在形成金属-绝缘层-金属结构160之后,其包含的多个金属层如电容底金属层162、电容中间金属层166、与电容顶金属层169可作为电容的金属板。金属-绝缘层-金属结构160亦包括多个介电层,比如位于电容底金属层162与电容中间金属层166之间的介电层164与位于电容中间金属层166与电容顶金属层169之间的介电层168。金属-绝缘层-金属结构160用于实施一或多个电容器,其可连接至其他电子构件如晶体管(平面场效晶体管或鳍状场效晶体管,未图示)。多层金属-绝缘层-金属结构160可让电容器在垂直方向与水平方向更紧密地挤在一起,以减少实施电容器所需的横向空间。如此一来,金属-绝缘层-金属结构160可包含超高密度电容器。
在一些实施例中,为增加电容值,介电层164及/或介电层168采用高介电常数的介电材料,其介电常数大于氧化硅的介电常数。介电层164与168可较薄以增加电容值,但介电层164与168维持最小厚度以避免金属-绝缘层-金属结构160中潜在的电容崩溃(比如两个电容板具有高电位差时,电流可能在两个电容板间漏电而造成崩溃)。在一些实施例中,介电层164或168的厚度介于约50nm至约70nm之间。此外,一些实施例中的介电层164(或168)为三层结构,其自下至上为第一氧化锆层、氧化铝层、与第二氧化锆层,且每一层的厚度介于约15nm至约25nm之间。
如图2M所示,方法10的步骤22(图1)形成介电层167于金属-绝缘层-金属结构160上。在一些实施例中,介电层167的厚度介于约400nm至约500nm之间。介电层158可包括氧化物材料,比如未掺杂的氧化硅或其他合适材料。在一些实施例中,介电层167的形成方法为沉积厚约900nm至约1000nm的氧化物材料,接着进行化学机械研磨制程以达最终厚度。如图2M所示,金属-绝缘层-金属结构160夹设于两个介电层158与167之间,而介电层158与167可具有相同材料及/或相同厚度。在一些实施例中,氮化物层156、介电层158、金属-绝缘层-金属结构160、与介电层167可视作多层钝化结构170的部分。在其他实施例中,金属-绝缘层-金属结构160不存在于多层钝化结构170中,下侧的介电层158与上侧的介电层167可结合为氮化物层156上的单一介电层(厚度介于约900nm至约1100nm之间)。
如图2N所示,方法10的步骤24(图1)形成一或多个开口(如开口171、172、与173)自上至下穿过介电层167、金属-绝缘层-金属结构160、介电层158、与氮化物层156。开口171、172、与173分别露出接点结构153、154、与155的上表面。在一些实施例中,进行干蚀刻制程以形成开口171、172、与173。每一开口的侧壁可露出金属-绝缘层-金属结构160的不同金属层,端视应用而定。如图2N所示,开口171与172均露出电容中间金属层166与电容顶金属层169,而开口173露出电容底金属层162与电容顶金属层169。
如图2O所示,方法10的步骤26(图1)分别形成一或多个上侧接点结构(如上侧的接点结构175、176、与177)于开口171、172、与173之中与之上。上侧的接点结构175、176、与177亦可称作金属接点、金属通孔、或金属线路。在一些实施例中,为形成一或多个接点结构(如接点结构175、176、与177),可先顺应性地沉积阻障层178于介电层167上及开口171、172、与173中,且沉积方法可采用合适的沉积技术如原子层沉积、物理气相沉积、或化学气相沉积。接着采用合适的沉积技术如化学气相沉积、物理气相沉积、或原子层沉积,以沉积金属填充层于阻障层178上。接着图案化沉积的阻障层178与金属填充层,以形成金属接点或金属线路(如接点结构175、176、与177),如图2O所示。在一些实施例中,在两阶段或多阶段蚀刻制程中图案化阻障层178与金属填充层。两阶段或多阶段的蚀刻制程,可包括至少一非等向蚀刻制程步骤与一等向蚀刻制程步骤,使接点结构175、176、与177的侧壁包括笔直的墙部W与锥形剖面T。在一些实施方式中,非等向蚀刻制程步骤比等向蚀刻制程步骤的蚀刻速率快,且需较多能量。在图2O所示的实施例中,墙部W与介电层167的上表面形成实质上90度的角度A1,而锥形剖面T与介电层167的上表面形成小于90度的角度A2。在一些例子中,角度A1介于约85°至约90°之间,而角度A2介于约70°至约85°之间。锥形剖面T可让接点结构175、176、与177包含锥形的基脚轮廓,使集中在接点结构角落的应力降低。此应力可增加向下穿过介电层167的裂缝,并威胁金属-绝缘层-金属结构160的整体性。
由于接点结构175、176、与177重布线上侧层与下侧层之间的接合连接,至少接点结构176、176、与177的上侧部分属于重布线层。上侧的接点结构175、176、与177由上至下各自穿过介电层167、金属-绝缘层-金属结构160、介电层158、与氮化物层156。上侧的接点结构175、176、与177可分别与下侧的接点结构153、154、与155电性接触。当上侧的接点结构175、176、与177重新布线接合连接时(比如连接接合垫190至下侧的接点结构153、154、与155),其可视作重布线层的接点。与下侧的接点结构153、154、与155类似,上侧的接点结构175、176、与177可各自包含阻障层与金属填充层,其形成方法可采用多重制程。在一些实施例中,上侧的接点结构175、176、与177的厚度各自介于约2500nm至约3100nm之间。每一上侧的接点结构侧壁可连接至金属-绝缘层-金属结构160的不同金属层,端视应用而定。如图2O所示,上侧的接点结构175与176均连接电容中间金属层166与电容顶金属层169,而上侧的接点结构177连接电容底金属层162与电容顶金属层169。由于金属-绝缘层-金属结构160可用于实施以多种图案配置的电容,接点结构175、176、与177可或可不电性连接至金属-绝缘层-金属结构160。以图2O的替代方案为例,金属-绝缘层-金属结构160可不具有任何构件直接位于接点结构153上,且此例的接点结构175不电性连接至金属-绝缘层-金属结构160。
如图2O所示,每一接点结构175、176、与177可具有高于介电层167的上侧部分。举例来说,接点结构176的上侧部分具有厚度Tc。接点结构175、176、与177之间亦可具有间隙距离。举例来说,接点结构176与177之间可具有间隙距离Pc。在一些实施例中,一或多个接点结构175、176、与177的厚隙比大于或等于约1:1(比如介于约1:1至约3:1之间)。由于采用多层钝化结构180如下述,因此可能具有上述比例范围。
在方法10的步骤28中(图1),形成多层钝化结构180于上侧的接点结构175、176、与177及介电层167上。如图2P至2R所示,形成多层钝化结构180的步骤关于多重制程。如图2P所示,形成氮化物层182于半导体装置100上。氮化物层182的形成方法可采用合适方法,比如化学气相沉积或物理气相沉积。在一实施例中,沉积的氮化物层182在半导体装置100的上表面上具有通常一致的厚度,比如在接点结构175、176、与177的上表面与侧壁表面上具有大致相同的厚度。在一些实施例中,氮化物层182的厚度介于约20nm至约250nm之间。
如图2Q所示,氧化物层184形成于氮化物层182上。氧化物层184的形成方法可采用合适方法,比如高密度等离子体的沉积法。在一些实施例中,氧化物层184的形成方法采用高密度等离子体的沉积法,其杨氏系数介于约62GPa至约76GPa之间,且其热膨胀系数介于约0.45ppm/℃至约0.55ppm/℃之间。在一实施例中,沉积的氧化物层184在半导体装置100的上表面上具有通常一致的厚度,比如在氮化物层182的上表面与侧壁表面上具有大致相同的厚度。在一些实施例中,氧化物层184包含未掺杂的氧化硅,且其厚度介于约1100nm至约1500nm之间。
如图2R所示,形成氮化物层186(如氮化硅)于氧化物层184上。氮化物层186的形成方法可采用合适方法如化学气相沉积或物理气相沉积。在一实施例中,沉积的氮化物层186在半导体装置100的上表面上具有通常一致的厚度,比如在氧化物层184的上表面与侧壁表面上具有大致相同的厚度。在一些实施例中,氮化物层186的厚度介于约600nm至约800nm之间。
在形成多层钝化结构180之后,其由下至上具有至少三层如氮化层182、氧化物层184、与氮化物层186。氮化物层182、氧化物层184、与氮化物层186所用的材料选择,使氧化物层184的杨氏系数低于(某些例子中为明显低于)氮化物层182或186的杨氏系数。杨氏系数较低意即氧化物层184较不硬脆,因此具有更高的应力抗性。在一实施例中,氮化物层182与186包括氮化硅(其杨氏系数为约310GPa),而氧化物层184包括未掺杂的氧化硅(其杨氏系数为约69GPa)。由于材料与制程条件造成多层的不同特性,多层钝化结构180具有多种优点如避免或减缓潜在裂缝的损伤,并增加多层钝化结构180的可能厚度。多层钝化结构180的优点将搭配图2U进一步说明如下。
如图2S所示,方法10的步骤30(图1)形成材料层188于多层钝化结构上。材料层188的组成可为聚酰亚胺或聚酰亚胺为主的材料,其杨氏系数可介于约3.0GPa至约5.5GPa之间,且其热膨胀系数可介于约20ppm/℃至约50ppm/℃之间。如图2S所示,材料层188良好地填入氮化物层186中的沟槽结构,而不具有任何瓶颈或空洞问题。
如图2T所示,方法10的步骤32(图1)形成接合垫190于材料层188中,以电性连接至上侧的接点结构176。接合垫190包括多层,且其形成方法关于多重制程。在一些实施例中,先产生开口于材料层188中。沉积凸块下金属层192至开口中,接着沉积凸块层194(组成可为铜)于凸块下金属层上。接着形成焊料层196于凸块层194上,作为连接至外部电路的连接点。
如上所述,位于重布线层上的一些钝化层只含硬脆材料,因此易于在应力下产生裂缝。此外,当重布线层包括接点结构时,重布线层上的单一钝化层厚度亦受限,因为过厚的钝化层在形成时可能造成瓶颈与空洞于相邻的接点结构之间的空间中。如此一来,相邻的金属接点之间的空间不能超过一定的深宽比。这会限制金属接点之间的最小间隙距离,并反过来限制重布线层的线路密度。此外,薄钝化层可诱发钝化层的裂缝并因此损伤金属-绝缘层-金属结构,其可作为重布线层下的电容。
本发明实施例提供多层钝化结构以解决前述问题并导致多种优点。在一些实施例中,多层钝化结构180具有至少三层而非单层,比如包含两个氮化物层182与186及夹设于氮化物层182与186之间的氧化物层184。由于氧化物层184的杨氏系数较低,其比氮化物层较不硬脆。因此氧化物层184对应力的抗性较高。与残留应力如-154MPa相较,氧化物层184的残留应力为-150MPa。在制作或使用时发生一或多个裂缝(如氮化物层186的角落中的裂缝198,见图2U)的状况中,由于氧化物层184可作为吸收应力的海棉,裂缝198顶多只穿过氮化物层186,因此可有效免于裂缝198扩散出或穿出氮化物层186。如此一来,裂缝较不会穿过钝化层的厚度并影响下方的电子构件。举例来说,氧化物层184可避免潜在的裂缝到达金属-绝缘层-金属结构160,而下方的氮化物层182可作为潜在的裂缝与金属-绝缘层-金属结构160之间的另一缓冲层。当金属-绝缘层-金属结构160为超高密度结构时,其可相对靠近多层钝化结构180的底部,并具有额外保护的价值。
此外,此处所述的多层钝化结构180比单一的氮化硅层钝化结构具有更大的整体厚度。在一实施例中,氮化物层182的厚度介于20nm至250nm之间,氧化物层184的厚度介于1100nm至1500nm之间,而氮化物层186的厚度介于600nm至800nm之间。在一些实施例中,多层钝化结构180的总厚度介于约1500nm至约3000nm之间。如上所述,由于采用多层钝化结构180,接点结构175、176、与177的厚隙比(厚度与间隙的比例)大于或等于约1:1,比如介于约1:1至约3:1之间。举例来说,由于制作多层钝化结构180可避免相邻接点结构之间的潜在空洞与瓶颈,因此可得上述比例范围。高厚隙比可让金属接点之间的间距缩小,进而增加接点结构175、176、与177分布其中的重布线层的线路密度。此外,多层钝化结构180中的每一层厚度设计为最佳化多层钝化结构180的效能,比如避免产生及/或扩散裂缝。在一例中,氧化物层为三层中最厚的层状物,以确保上方层(比如氮化物层186)中任何潜在的裂缝不会延伸至氧化物层184下的层状物中。
基于上述内容,可知本发明实施例比现有装置与其制作方法提供更多优点。然而应理解的是,其他实施例可提供额外优点,此处不必说明所有优点,且所有实施例不必具有特定优点。
本发明一实施例关于制作集成电路的方法。方法包括形成钝化层于第一接点结构上;形成第二接点结构于钝化层上并穿过该钝化层,且第二接点结构电性连接至第一接点结构;以及形成多层钝化结构于第二接点结构与钝化层上。钝化层包括介电层。形成多层钝化结构的步骤包括沉积第一氮化物层、沉积氧化物层于第一氮化物层上、以及沉积第二氮化物层于氧化物层上。
在一些实施例中,氧化物层的沉积方法采用高密度等离子体沉积法。在一些实施例中,第一氮化物层与第二氮化物层包括氮化硅,其沉积方法采用化学气相沉积或物理气相沉积。在一些实施例中,沉积的第一氮化物层、氧化物层、与第二氮化物层中,氧化物层的杨氏系数低于第一氮化物层或第二氮化物层的杨氏系数。在一些例子中,第一氮化物层与第二氮化物层包括氮化硅,氧化物层包括未掺杂的氧化硅,而第二接点结构包括铜。在一些实施例中,多层钝化结构的第一氮化物层的厚度介于约20nm至约250nm之间,氧化物层的厚度介于约1100nm至约1500nm之间,且第二氮化物层的厚度介于约600nm至约800nm之间。在一些实施例中,介电层为钝化层的上侧介电层。钝化层还包括金属-绝缘层-金属结构位于上侧介电层下,以及下侧介电层位于金属-绝缘层-金属结构下。在一些例子中,形成钝化层的步骤使其金属-绝缘层-金属结构包括多个层状物,且层状物包括电容底金属层、电容中间金属层、电容顶金属层、电容底金属层与电容中间金属层之间的第一高介电常数的介电材料层、以及电容中间金属层与电容顶金属层之间的第二高介电常数的介电材料层,其中电容底金属层、电容中间金属层、与电容顶金属层的至少一者经由第二接点结构电性连接至第一接点结构。在一些例子中,方法还包括形成接合垫,其电性连接至第二接点结构。在一些实施例中,形成接合垫的方法包括自下至上形成凸块下金属层、凸块层、与焊料层。
本发明一实施例关于半导体装置。半导体装置包括下侧接点结构,位于基板上;介电层,位于下侧接点结构上;上侧接点结构,位于介电层上并穿过介电层,且上侧接点结构电性连接至下侧接点结构;以及钝化结构,位于第二接点结构与介电层上。钝化结构包括第一氮化物层、第二氮化物层、与位于第一氮化物层与第二氮化物层之间的氧化物层。
在一些实施例中,下侧接点结构与上侧接点结构均包含铜。在一些实施例中,氧化物层的杨氏系数低于第一氮化物层或第二氮化物层的杨氏系数。在一些实施例中,第一氮化物层与第二氮化物层包括氮化硅,而氧化物层包括未掺杂的氧化硅。在一些例子中,第一氮化物层厚约20nm至约250nm,氧化层厚约1100nm至约1500nm,且第二氮化物层厚约600nm至约800nm。在一些实施例中,半导体装置还包括金属-绝缘层-金属结构位于下侧接点结构与介电层之间。金属-绝缘层-金属结构包括电容底金属层、电容中间金属层、电容顶金属层、电容底金属层与电容中间金属层之间的第一介电层、以及电容中间金属层与电容顶金属层之间的第二介电层。电容底金属层、电容中间金属层、与电容顶金属层的至少一者电性连接至上侧接点结构。在一些实施例中,介电层为上侧介电层,且半导体装置还包括下侧介电层于下侧接点结构与金属-绝缘层-金属结构之间。在一些实施例中,半导体装置还包括接合垫电性连接至上侧接点结构。接合垫自下至上包括凸块下金属层、凸块层、与焊料层。
本发明另一实施例关于方法。方法包括:形成顶金属接点于半导体基板上;沉积第一介电层于顶金属接点上;形成金属-绝缘层-金属结构于第一介电层上;沉积第二介电层于金属-绝缘层-金属结构上;形成金属通孔,其电性耦接至金属-绝缘层-金属结构及顶金属接点;形成钝化结构于金属通孔及第二介电层上;以及形成接合垫,其电性耦接至金属通孔。形成钝化结构的步骤包括:沉积第一氮化物层于金属通孔与第二介电层上;沉积氧化物层于第一氮化物层上;以及沉积第二氮化物层于氧化物层上。在一些实施例中,氧化物层的沉积法采用高密度等离子体沉积,且第一氮化物层与第二氮化物层包括氮化硅,其沉积法采用化学气相沉积或物理气相沉积。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础,设计并变化其他制程与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解,这些等效置换并未脱离本发明精神与范围,并可在未脱离本发明的精神与范围的前提下进行改变、替换、或变动。
Claims (1)
1.一种制作集成电路的方法,包括:
形成一钝化层于一第一接点结构上,且该钝化层包括一介电层;
形成一第二接点结构于该钝化层上并穿过该钝化层,且该第二接点结构电性连接至该第一接点结构;以及
形成一多层钝化结构于该第二接点结构与该钝化层上,其中形成该多层钝化结构的步骤包括沉积一第一氮化物层、沉积一氧化物层于该第一氮化物层上、以及沉积一第二氮化物层于该氧化物层上。
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