US20230021655A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
US20230021655A1
US20230021655A1 US17/587,605 US202217587605A US2023021655A1 US 20230021655 A1 US20230021655 A1 US 20230021655A1 US 202217587605 A US202217587605 A US 202217587605A US 2023021655 A1 US2023021655 A1 US 2023021655A1
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column
conductive patterns
patterns
columns
plan
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US17/587,605
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English (en)
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Ching-Hung Kao
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US17/587,605 priority Critical patent/US20230021655A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAO, CHING-HUNG
Priority to DE102022102730.9A priority patent/DE102022102730A1/de
Priority to TW111111331A priority patent/TWI843076B/zh
Priority to KR1020220039183A priority patent/KR20230015263A/ko
Priority to CN202210658260.2A priority patent/CN115346917A/zh
Publication of US20230021655A1 publication Critical patent/US20230021655A1/en
Pending legal-status Critical Current

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Definitions

  • FIG. 1 shows one of the stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 2 shows one of the stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 3 shows one of the stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 4 shows one of the stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 5 shows one of the stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure.
  • FIGS. 6 A and 6 B show one of the stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 7 shows one of the stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure.
  • FIGS. 8 A and 8 B show views of a semiconductor device according to an embodiment of the present disclosure.
  • FIGS. 9 A and 9 B show views of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 10 shows a view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 11 shows a view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 12 shows a view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 13 shows a view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 14 shows a view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 15 shows a view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 16 shows a view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 17 shows a view of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 18 shows a flow of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 19 shows a flow of a sequential manufacturing operation of a photomask according to an embodiment of the present disclosure.
  • FIG. 20 shows advantageous effects of the embodiments of the present disclosure.
  • first and second features are formed in direct contact
  • additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
  • Various features may be arbitrarily drawn in different scales for simplicity and clarity.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • a bump electrode is formed on the pad electrode, and in other embodiments, a bonding wire is directly attached to the pad electrode.
  • FIGS. 1 - 7 show various views of a sequential manufacturing operation of a bump structure over a semiconductor circuit according to an embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown by FIGS. 1 - 7 , and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.
  • a plurality of topmost wiring patterns 20 are formed in an interlayer dielectric (ILD) or intermetal dielectric (IMD) layers 18 formed over a semiconductor circuit 15 that is formed on a substrate 10 .
  • the topmost wiring patterns 20 are formed of a suitable conductive metal, including aluminum, copper, silver, gold, nickel, tungsten, titanium, alloys thereof, and/or multilayers thereof.
  • the topmost wiring patterns 20 are made of Cu or a Cu alloy in which a majority (more than 50%) is Cu.
  • the topmost wiring patterns 20 are formed by a suitable metal deposition operation, including electro or electroless plating, physical vapor deposition (PVD) including sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal evaporation, or electron beam evaporation.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • thermal evaporation thermal evaporation
  • electron beam evaporation electron beam evaporation.
  • the topmost wiring patterns 20 are formed by using a damascene technology.
  • the semiconductor circuit 15 includes transistors (e.g., field effect transistors (FETs)), capacitors, inductors, resistors, or the like in some embodiments.
  • the topmost wiring patterns 20 are electrically coupled to the semiconductor circuit 15 through underlying interconnection layers including wiring layers and vias formed in dielectric layers, such as ILD layers or IMD layers in some embodiments.
  • the wiring layers and vias of the interconnection layer may be formed of copper or copper alloys (e.g., AlCu), aluminum, tungsten, nickel, or any other suitable metal.
  • the wiring layers and vias may be formed using damascene processes.
  • the substrate 10 is formed of at least one selected from the group consisting of silicon, diamond, germanium, SiGe, SiGeSn, SiGeC, GeSn, SiSn, GaAs, InGaAs, InAs, InP, InSb, GaAsP, GaInP, and SiC.
  • the semiconductor substrate 10 is a silicon wafer or substrate.
  • the ILD or IMD layer 18 include one or more of silicon oxide, silicon nitride, SiOC, SiON, SiOCN, SiCN, low-k dielectric material or any other suitable dielectric materials.
  • the top dielectric layer 22 includes one or more layers of silicon oxide, silicon nitride, SiON, SiC, SiOCN, SiCN or any other suitable insulating layers. In some embodiments, a thickness of the top dielectric layer 22 is in a range from about 0.1 ⁇ m to about 2.0 ⁇ m, and is in a range from about 0.2 ⁇ m to about 1.0 ⁇ m.
  • the top dielectric layer 22 is formed by a suitable metal deposition operation, including PVD, CVD or ALD.
  • the top dielectric layer 22 is patterned using suitable photolithography and etching operations to form openings 24 .
  • a resist pattern 25 having openings is formed on the top dielectric layer 22 , and the top dielectric layer 22 is patterned by one or more etching operation.
  • part of the topmost wiring patterns 20 is exposed by the etching.
  • the opening 24 has a tapered shape as shown in FIG. 3 .
  • the blanket conductive layer 30 L is formed by a suitable metal deposition operation, including plating, PVD (including sputtering), CVD, ALD, thermal evaporation, and electron beam evaporation.
  • the blanket conductive layer 30 L includes a suitable conductive metal, including aluminum, copper, silver, gold, nickel, tungsten, titanium, alloys thereof, and/or multilayers thereof.
  • the blanket conductive layer 30 L is made of Al or an Al alloy in which a majority (more than 50%) is Al.
  • a thickness of the blanket conductive layer 30 L over the top dielectric layer 22 is in a range from about 0.5 ⁇ m to about 5.0 ⁇ m and is in a range from about 1.0 ⁇ m to about 3.0 ⁇ m in other embodiments.
  • a recess or a dimple 32 is formed above the opening 24 reflecting the shape of the top dielectric layer 22 .
  • the recess or dimple 32 has a V-shape, a U-shape or a reverse trapezoidal shape in some embodiments.
  • a depth of the recess or dimple 32 is in a range from about 0.05 ⁇ m to about 0.5 ⁇ m in some embodiments, and is in a range from about 0.1 ⁇ m to about 0.4 ⁇ m in other embodiments.
  • one or more barrier layer is formed before the blanket layer 30 L is formed.
  • the barrier layer includes Ti, TiN, Ta, TaN or TiW.
  • a resist pattern 35 is formed over the blanket conductive layer 30 L, and the blanket conductive layer 30 L is patterned into pad electrodes 30 by using one or more etching operations.
  • the pad electrode 30 has a tapered shape having a taper angle with respect to the normal direction towards an upper surface of the topmost wiring patterns 20 in a range from about 5 degrees to about 15 degrees.
  • the pad electrode 30 has a reverse tapered shape having a taper angle with respect to the normal direction in a range from about ⁇ 5 degrees to about ⁇ 15 degrees.
  • a passivation layer 40 is formed over the pad electrodes 30 and the top dielectric layer 22 .
  • the passivation layer 40 includes one or more layers of silicon oxide, silicon nitride, SiOC, SiON, SiOCN, SiCN or any other suitable dielectric materials.
  • silicon nitride is used as the passivation layer 40 .
  • a thickness of the passivation layer 40 is in a range from about 1.0 ⁇ m to about 10 ⁇ m, and is in a range from about 2.0 ⁇ m to about 5.0 ⁇ m, from the top of the pad electrodes 30 .
  • the passivation layer 40 is formed by a suitable deposition operation, including PVD, CVD or ALD. As shown in FIG. 7 , the passivation layer 40 has peaks above the pad electrodes 30 and valleys between the pad electrodes 30 .
  • the passivation layer 40 is patterned by one or more lithography and etching operation to form openings over the pad electrodes 30 for outside electrical connection (by wire or by bump).
  • the topmost wiring patterns 20 are arranged in a row-column (X-Y) arrangement in some embodiments as shown in FIG. 8 A .
  • the topmost wiring patterns 20 have a rectangular shape having first sides (width L 1 ) along the row (X) direction and second sides (width L 2 ) along the column (Y) direction in plan view.
  • L 1 and L 2 are in a range from about 2 ⁇ m to 10 ⁇ m, and are in a range from about 4 ⁇ m to 6 ⁇ m in other embodiments.
  • the rectangular or square shape of the topmost wiring patterns 20 have rounded corners in some embodiments in plan view.
  • the plurality of topmost wiring patterns 20 are arranged in a row-column arrangement having a pitch P 1 of about 2.5 ⁇ m to about 15 ⁇ m (a space between adjacent wiring patterns 20 is in a range from about 0.5 ⁇ m to about 5.0 ⁇ m).
  • the pitch along the row direction is the same as or different from the pitch along the column direction.
  • a thickness of the topmost wiring patterns 20 is in a range from about 1.0 ⁇ m to about 5.0 ⁇ m, and is in a range from about 3.0 ⁇ m to about 4.0 ⁇ m in other embodiments.
  • a 2 ⁇ 4 arrangement of the topmost wiring patterns 20 is illustrated in FIG. 8 A , but the disclosure is not limited to a 2 ⁇ 4 arrangement.
  • the arrangement is 2 ⁇ N arrangement, where N is 4 or more (up to, for example, 100).
  • Other arrangements, including a fewer or greater number of rows or columns of topmost wiring patterns 20 are included in the scope of this disclosure.
  • the arrangement may be an M ⁇ N arrangement, where M and N is a natural number, and at least one of M and N is 2 or more up to about 100.
  • the M ⁇ N arrangement has no other wiring patterns at the same wiring level within a distance L 0 from the M ⁇ N arrangement, where L 0 is twice to ten times the pitch of the M ⁇ N arrangement.
  • at least one of the row length or the column length of the matrix of the topmost wiring patterns 20 is in a range from about 200 ⁇ m to 2 mm.
  • the pad electrodes 30 are arranged in a row-column arrangement in some embodiments as shown in FIG. 8 A .
  • the arrangement or layout of the pad electrodes 30 is substantially the same as that of the topmost wiring patterns 20 .
  • the pad electrodes 30 have a rectangular shape having first sides (width L 3 ) along the row direction and second sides (width L 4 ) along the column direction in plan view. In some embodiments, 0.8 ⁇ L 3 /L 4 ⁇ 1.2, and in other embodiments, 0.95 ⁇ L 3 /L 4 ⁇ 1.05 (substantially square).
  • L 3 and L 4 are in a range from about 2 ⁇ m to 10 ⁇ m, and are in a range from about 4 ⁇ m to 6 ⁇ m in other embodiments. In some embodiments, L 3 and L 4 are smaller than L 1 and L 2 , respectively.
  • the passivation layer 40 has peaks above the pad electrodes 30 and valleys between the pad electrodes 30 .
  • the bottom of the valley is located at a level between the top of the topmost wiring patterns 20 and the top of the pad electrodes 30 .
  • the center line of the adjacent two rows of the pad electrodes 30 upper portion above the top dielectric layer
  • the center line of the adjacent two rows of the topmost wiring patterns 20 , on which the two rows of the pad electrodes 30 are formed are substantially aligned with each other (different is less than 0.1 ⁇ m)
  • the bottom of the valley is located above the space between the topmost wiring patterns 20 as shown in FIG. 8 B .
  • the center line of the adjacent two columns of the pad electrodes 30 is shifted, for example to + row direction, from the center line of the adjacent two columns of the topmost wiring patterns 20 .
  • the shift amount D 1 is more than 0.1 ⁇ m.
  • D 1 is equal to or more than S 1 / 2 (a half of S 1 ), where S 1 is a space between adjacent topmost wiring patterns 20 in the row direction (see, FIG. 10 ).
  • the shift amount D 1 is equal to or more than S 1 / 2
  • the center line of the adjacent two columns of the pad electrodes 30 overlaps one of the adjacent columns of the topmost wiring patterns as shown in FIGS. 9 A and 9 B .
  • the bottom of the valley of the passivation layer 40 is also located above one of the adjacent columns of the topmost wiring patterns as shown in FIG. 9 B .
  • the shift amount D 1 is S 1 / 2 + ⁇ , where ⁇ is in a range from about 0.1 ⁇ m to about 1.0 ⁇ m (e.g., 0.1, 0.2, 0.3, 0.4 or 0.5 ⁇ m).
  • a long valley is formed in the passivation layer 40 along the space between two columns in the column direction.
  • Such a long valley may cause a crack 45 in the passivation layer as shown in FIG. 10 .
  • the crack 45 since the bottom of the valley, which can be an origin of the crack, is located above the topmost wiring patterns 20 , the crack 45 , if formed, stops at the surface of the topmost wiring patterns 20 , and thus it is possible to prevent the crack from reaching the circuit region below the topmost wiring layers 20 .
  • the crack may penetrate into the top dielectric layer 22 and ILD/IMD layers at the spaces between adjacent topmost wiring patterns 20 , since the spaces between adjacent topmost wiring patterns 20 is sufficiently smaller than the size of the topmost wiring patterns 20 , the crack 45 does not penetrate deeply into the top dielectric layer 22 and/or the ILD/IMD layers.
  • the bottom of the crack 45 is located between the top surface and bottom surface of the topmost wiring patterns 20 in the space between the topmost wiring patterns in the column direction.
  • the width L 11 of the topmost wiring pattern 20 is in a range from about 2 ⁇ m to 10 ⁇ m, and is in a range from about 4 ⁇ m to 6 ⁇ m in other embodiments.
  • the width L 21 of the bottom of the pad electrode 30 is in a range from about 1.2 ⁇ m to 6 ⁇ m, and is in a range from about 2.4 ⁇ m to 3.6 ⁇ m in other embodiments.
  • the largest width L 22 of the pad electrode 30 is in a range from about 1.6 ⁇ m to 8 ⁇ m, and is in a range from about 3.2 ⁇ m to 4.8 ⁇ m in other embodiments.
  • the space S 1 is in a range from about 0.5 ⁇ m to 2.0 ⁇ m, and is in a range from about 0.8 ⁇ m to 1.2 ⁇ m in other embodiments.
  • the shift amount D 1 is set such that the outer edge of the opening 24 is within the topmost wiring pattern 20 .
  • D 1 corresponds to the difference between the center of the opening 24 (see, FIG. 3 ) and the center of the topmost wiring pattern 20 when a resist pattern 35 for the pad electrode 30 shown in FIG. 5 is aligned with the opening 24 .
  • the lower part (embedded in the top dielectric layer 22 ) of the pad electrode 30 and the upper part (above the upper surface of the top dielectric layer 22 ) of the pad electrode 30 are substantially aligned with each other (an overlay error is less than 0.1 ⁇ m in some embodiments).
  • D 1 is equal to or more than S 1 / 2 (a half of S 1 ) and equal to or less than (L 11 -L 21 )/2.
  • the upper part of the pad electrode 30 has a thickness greater than the lower part of the pad electrode 30 .
  • the lower part (embedded in the top dielectric layer 22 ) of the pad electrode 30 is substantially aligned with the topmost wiring layer 20 (an overlay error is less than 0.1 ⁇ m in some embodiments), and the upper part of the pad electrode 30 is shifted by the shift amount D 1 .
  • D 1 is equal to or more than S 1 / 2 (a half of S 1 ) and equal to or less than (L 22 -L 21 ′)/2, where the width L 21 ′ is a width of the top of the lower part of the pad electrode 30 .
  • D 1 is equal to or more than S 1 / 2 + ⁇ , where ⁇ is about 0.1 ⁇ m.
  • both the lower part and the upper part of the pad electrode 30 are shifted with respect to the topmost wiring pattern 20 so that the upper part of the pad electrode 30 is shifted from the topmost wiring layer 20 by the amount D 1 .
  • FIG. 12 shows another embodiment, where the pad electrodes 30 have a reverse tapered shape. Similar to the foregoing embodiments, the pad electrodes 30 are relatively shifted from the topmost wiring patterns 20 so that the center line of the adjacent two columns of the pad electrodes 30 overlaps one or two columns of the topmost wiring pattern 20 , on which the two columns of the pad electrodes 30 are formed. Accordingly, the valleys of the passivation layer 40 are located just above the topmost wiring patterns 20 .
  • the structures shown in FIGS. 9 A- 11 are obtained by shifting one or both resist patterns for the opening 24 and the pad electrode 30 with respect to the topmost wiring patterns 20 .
  • Such a pattern shift can be achieved by inputting an overlay adjustment value (other than or in addition to a machine errors (so called “overlay error”)) into a lithography apparatus using the original photo mask(s) which is designed to perfectly align the underlying pattern (e.g., the topmost wiring patterns).
  • overlay error other than or in addition to a machine errors
  • there is no need to manufacture additional photo masks for patterning the opening 24 and/or the pad electrodes 30 and all patterns formed by using the photo mask are shifted by the same amount.
  • new photo masks which have an intentional pattern shift are manufactured, and no overlay shift (other than minor adjustment) is input into a lithography apparatus when forming a resist pattern. In some embodiments, only certain necessary parts of the patterns are shifted.
  • FIGS. 13 and 14 show pattern layouts in accordance with embodiments of the present disclosure.
  • the topmost wiring patterns 20 and the pad electrodes 30 include not only a matrix pattern MX but also one or more island patterns IL as shown in FIGS. 13 and 14 .
  • the island pattern IL is separated from the matrix pattern or separated from the closest pattern by a distance L 0 , where L 0 is twice to ten times or more the pitch of the matrix arrangement.
  • L 0 is twice to ten times or more the pitch of the matrix arrangement.
  • both the pad electrodes 30 of the matrix pattern MX and the island pattern IL are shifted in the row direction with respect to the topmost wiring patterns 20 .
  • the center line CL of the adjacent two columns of the pad electrodes 30 of the matrix pattern overlaps one of two columns of the topmost wiring pattern 20 in plan view As set forth above, this can be achieved by inputting an overlay adjustment value into the lithography apparatus using the original photo mask, or using a specifically manufactured photo mask.
  • the topmost wiring patterns 20 include one or more patterns on which no pad electrode is formed.
  • the pad electrode 30 of the island pattern IL is substantially aligned (not shifted or shift amount less than 0.1 ⁇ m which may be caused by machine errors (so called “overlay error”)) with the corresponding topmost wiring pattern 20 .
  • overlay error machine errors
  • island patterns that do not require the pattern shift include a small matrix having row or column length less than 100 ⁇ m.
  • one or more island patterns IL as shown in FIG. 13 or 14 are a dummy pattern, a pattern for measurement (overlay or alignment), or a part of a test circuit, which are disposed on a scribe lane surrounding a semiconductor chip.
  • FIGS. 15 and 16 show pattern layouts in accordance with embodiments of the present disclosure.
  • the pattern matrix of the topmost wiring patterns 20 and the pad electrodes 30 is an M ⁇ N arrangement, where M and N are four or more, and/or the row and/or column length is more than 100 ⁇ m.
  • the entire matrix of the pad electrodes 30 is shifted only in one direction, e.g., row direction so that the center line CL of the adjacent two columns of the pad electrodes 30 overlaps one of two columns of the topmost wiring pattern 20 , on which the two columns of the pad electrodes 30 are formed.
  • the center (a geometric center or a center of gravity) of the matrix of the pad electrodes 30 (in particular upper portions) is shifted by the shift amount with respect to the center of the matrix of the topmost wiring patterns 20 in one direction.
  • the entire matrix of the pad electrodes 30 is shifted in both row and column directions so that the center line CL of the adjacent two columns of the pad electrodes 30 overlaps one of two columns of the topmost wiring pattern 20 , and the center line CL′ of the adjacent two rows of the pad electrodes 30 overlaps one of two rows of the topmost wiring pattern 20 .
  • the center of the matrix of the pad electrodes 30 (in particular upper portions) is shifted by the shift amount with respect to the center of the matrix of the topmost wiring patterns 20 in two directions.
  • FIG. 17 shows pattern layouts in accordance with embodiments of the present disclosure.
  • the pad electrodes 30 are arranged around the periphery of the semiconductor chip as shown in FIG. 17 .
  • the periphery or a peripheral area of the semiconductor chip is an area within 500 ⁇ m from a border between the chip area (circuit area) and scribe lines.
  • two columns of pad electrode are arranged at left and right sides of the semiconductor chip and two rows of pad electrodes are arranged at top and bottom sides of the semiconductor chip.
  • the columns of the pad electrodes 30 located at the left and the right of the semiconductor chip are shifted along the row direction (left to right) so that the center line of the adjacent two columns of the pad electrodes 30 overlaps one of two columns of the topmost wiring pattern 20 , on which the two columns of the pad electrodes 30 are formed.
  • the rows of the pad electrodes 30 located at the top and the bottom of the semiconductor chip are shifted along the column direction (top to bottom) so that the center line of the adjacent two rows of the pad electrodes 30 overlaps one of two rows of the topmost wiring pattern 20 , on which the two rows of the pad electrodes 30 are formed.
  • the shift direction of the columns of the pad electrodes 30 located at the left is the same as the shift direction of the columns of the pad electrodes 30 at the right of the semiconductor chip, for example, to the left with respect to the topmost wiring patterns, as shown in FIG. 7 .
  • the shift direction of the columns of the pad electrodes 30 located at the left is different from the shift direction of the columns of the pad electrodes 30 at the right of the semiconductor chip with respect to the topmost wiring patterns. Similar arrangements are applied to the rows of the pad electrodes located at the top and the bottom of the semiconductor chip.
  • the pad electrodes 30 are shifted toward the outside the semiconductor chip with respect to the topmost wiring patterns at four sides of the semiconductor chip, and in other embodiments, the pad electrodes are shifted toward the inside the semiconductor chip with respect to the topmost wiring patterns at four sides of the semiconductor chip.
  • the rows of the pad electrodes 30 and the columns of the pad electrodes 30 are shifted both in the row direction and the column direction with respect to the topmost wiring patterns similar to FIG. 16 .
  • FIG. 18 shows a flow chart of manufacturing a semiconductor device according to an embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown in FIG. 18 , and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.
  • the patterns 20 are a topmost wiring pattern, which is the closest wiring layer to the pad electrode in the vertical direction and connected to the pad electrode, and the patterns 30 are pad electrodes.
  • the configuration is not limited to this.
  • the pattern 30 is an under bump metallization (UBM) layer, on which a bump electrode is formed.
  • UBM under bump metallization
  • wiring patterns for example, the topmost wiring patterns 20 as set forth above, are formed in an ILD layer over a substrate.
  • a first dielectric layer for example, the top dielectric layer 22 as set forth above, is formed over the wiring pattern formed in the ILD layer.
  • a first resist pattern for forming openings/windows for example, openings 24 as set forth above, is formed over the first dielectric layer.
  • an overlay shift amount OL 1 in addition to an overlay compensation value caused by an imperfection of alignment process is implemented in the lithography process.
  • the overlay shift amount OL 1 of less than 0.1 ⁇ m is implemented in the lithography process.
  • OL 1 is set relative to the wiring patterns.
  • the first dielectric layer is patterned using the first resist pattern as an etching mask to form openings, for example openings 24 as set forth above, over the wiring patterns.
  • a blanket conductive layer for example conductive layer 30 L as set forth above, is formed in the openings and on the first dielectric layer.
  • a second resist pattern for forming electrodes for example, pad electrodes 30 as set forth above, is formed over the conductive layer.
  • an overlay shift amount OL 2 in addition to an overlay compensation value caused by imperfection of alignment process (about less than 0.1 ⁇ m) is implemented in the lithography process.
  • the blanket conductive layer is patterned using the second resist pattern as an etching mask to form an electrode, for example, a pad electrode 30 as set forth above.
  • a second dielectric layer for example, a passivation layer 40 as set forth above is formed over the first dielectric layer and the patterned electrodes.
  • one or both of the photomasks used in the process blocks S 804 and S 806 are designed such that the electrode or the electrode and openings are aligned with the corresponding wiring patterns.
  • the overlay shift amounts OL 2 with respect to the wiring patterns is set to more than 0.1 ⁇ m, or S 1 / 2 + ⁇ , where S 1 is a space between the wiring patterns, and ⁇ is in a range from about 0.1 ⁇ m to about 1.0 ⁇ m. In some embodiments, OL 1 is zero.
  • the sum of overlay shift amounts OL 1 +OL 2 with respect to the wiring patterns is set to more than 0.1 ⁇ m, or S 1 / 2 + ⁇ , where S 1 is a space between the wiring patterns, and ⁇ is in a range from about 0.1 ⁇ m to about 1.0 ⁇ m, when the OL 2 is set relative to the opening.
  • one or both of the photomasks used in the process blocks S 804 and S 806 are designed such that the electrodes are shifted with respect to the corresponding wiring patterns.
  • OL 1 and OL 2 are both zero and only an overlay compensation value caused by imperfection of alignment process, if necessary, is input to the lithography apparatus.
  • FIG. 19 shows a flow chart of manufacturing a photomask according to embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after the processes shown in FIG. 19 , and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.
  • an original layout for opening patterns for example, openings 24 (first resist pattern 25 ) and an original layout for electrode patterns, for example, pad electrodes 30 are prepared.
  • the opening patterns and the electrode patterns are designed to align with the underlying pattern, such as the wiring pattern on which the openings are formed (for example, topmost wiring patterns 20 ). Similar to the configuration shown in the embodiments of FIG. 8 A , the center line of the adjacent two rows of the electrode patterns is aligned with the center line of the adjacent two rows of the wiring patterns.
  • one or more groups of electrode patterns that would create a long valley (e.g., more than 200 ⁇ m) at an overlying insulating layer are searched for and detected.
  • the electrode patterns when the electrode patterns are arranged in at least two rows and/or columns, the space between adjacent rows/columns is within a predetermined range and the length of the rows/columns is more than a threshold length, it is determined that the groups of electrode patterns would create a long valley at an overlying insulating layer. This can be achieved by one or more resizing and/or Boolean operations of the patterns.
  • the predetermined range is from about 0.5 ⁇ m to 2.0 ⁇ m, and is from about 0.8 ⁇ m to 1.2 ⁇ m in other embodiments.
  • the threshold length is about 200 ⁇ m and is about 400 ⁇ m in other embodiments.
  • the group of electrode patterns are shifted in a direction crossing the valley, which would otherwise be appear, by a shift amount.
  • the shift amount is determined such that the centerline of the adjacent rows/columns of the electrode patterns overlaps the underlying wiring patterns as explained above.
  • the opening patterns corresponding to the critical group of electrode patterns are shifted at process block S 904 by the same or different shift amount as the shift amount of the electrode patterns.
  • modified layout is output as mask data, and one or more photomask is manufactured according to the mask data, and the manufactured photomask is used, for example, in the process shown in FIG. 18 .
  • the process shown in FIG. 19 is performed by a computer system including one or more processors and storage media (memories) that store a program.
  • the executed program can perform at least a part of the operations shown in FIG. 19 .
  • one or more of the process blocks S 901 -S 904 are performed by a computer system.
  • the computer system is provided with a computer including an optical disk read only memory (e.g., CD-ROM or DVD-ROM) drive and a magnetic disk drive, a keyboard, a mouse, and a monitor.
  • an optical disk read only memory e.g., CD-ROM or DVD-ROM
  • the computer is provided with, in addition to the optical disk drive and the magnetic disk drive, one or more processors, such as a micro processing unit (MPU), a ROM in which a program such as a boot up program is stored, a random access memory (RAM) that is connected to the MPU and in which a command of an application program is temporarily stored and a temporary storage area is provided, a hard disk in which an application program, a system program, and data are stored, and a bus that connects the MPU, the ROM, and the like.
  • processors such as a micro processing unit (MPU), a ROM in which a program such as a boot up program is stored, a random access memory (RAM) that is connected to the MPU and in which a command of an application program is temporarily stored and a temporary storage area is provided, a hard disk in which an application program, a system program, and data are stored, and a bus that connects the MPU, the ROM, and the like.
  • the computer system may include a network card (not
  • the program for causing the computer system to execute the functions of an apparatus for performing the aforementioned mask data generating operation may be stored in an optical disk or a magnetic disk, which are inserted into the optical disk drive or the magnetic disk drive, and transmitted to the hard disk. Alternatively, the program may be transmitted via a network (not shown) to the computer and stored in the hard disk. At the time of execution, the program is loaded into the RAM. The program may be loaded from the optical disk or the magnetic disk, or directly from a network.
  • the program does not necessarily have to include, for example, an operating system (OS) or a third party program to cause the computer to execute the functions of a photo mask data generation apparatus in the foregoing embodiments.
  • the program may only include a command portion to call an appropriate function (module) in a controlled mode and obtain desired results.
  • FIG. 20 shows an advantageous effect of the present embodiments.
  • Various samples having different row/column length (“PRL”) and different shift amounts were fabricated and a number of cases in which the crack in the passivation layer (silicon nitride of 200 nm) reaches below the topmost wiring patterns was counted.
  • Pattern space S 1 between adjacent ones of the topmost wiring layers was 0.75 ⁇ m.
  • a long valley portion in a passivation layer which may be an origin of a crack
  • a topography of rows and/or columns of pad electrode patterns since the rows/columns of the pad electrode patterns are shifted with respect to the underlying wiring patterns so that the valley is located above the underlying wiring patterns, it is possible to present the crack from penetrating below the wiring patterns.
  • such a pattern shift is achieved by introducing an overlay shift in an exposure apparatus and no new photomask is necessary.
  • lower conductive patterns are formed.
  • the lower conductive patterns include a first column of patterns in which a plurality of conductive patterns are arranged in a first direction and a second column of patterns in which a plurality of conductive patterns are arranged in the first direction, and the first column and the second column are adjacent to each other in a second direction crossing the first direction in plan view.
  • Upper conductive patterns are formed.
  • the upper conductive patterns include a third column of patterns in which a plurality of conductive patterns are arranged in the first direction and a fourth column of patterns in which a plurality of conductive patterns are arranged in the first direction, and the third column and the fourth column are adjacent to each other in the second direction in plan view.
  • the first column and the third column at least partially overlap with each other in plan view
  • the second column and the fourth column at least partially overlap with each other in plan view
  • the upper conductive patterns are formed such that a first center line extending in the first direction of the first and second columns is shifted in the second direction by a shift amount more than 0.1 ⁇ m from a second center line extending in the first direction of the third and fourth columns in plan view.
  • the second center line overlaps the second column in plan view.
  • the forming upper conductive patterns comprises forming a resist pattern corresponding to the upper conductive patterns by a lithography apparatus, and in the lithography operation, an overlay shift other than zero in the second direction is input to the lithography apparatus so that the first center line extending in the direction of the first and second columns is shifted in the second direction from the second center line extending in the direction of the third and fourth columns in plan view.
  • an insulating layer is further formed over the upper conductive lines.
  • the insulating layer comprises peaks over the third column and the fourth column, and a valley between the third column and the fourth column.
  • the valley overlaps the second column.
  • the insulating layer comprises a crack from the valley to at least one of the plurality of conductive patterns of the second column.
  • a space between the first column and the second column is smaller than a space between the third column and the fourth column.
  • the shift amount is greater than a half of the space between the first column and the second column.
  • the space between the first column and the second column is in a range from 0.8 ⁇ m to 1.2 ⁇ m
  • the space between the third column and the fourth column is in a range from 1.6 ⁇ m to 2.4 ⁇ m
  • the shift amount is in a range from 0.8 ⁇ m to 1.0 ⁇ m.
  • a total length of the first column is more than 200 ⁇ m.
  • each of the plurality of conductive patterns in the first and second columns has a square shape with rounded corners in plan view.
  • each of the plurality of conductive patterns in the third and fourth columns has a square shape with rounded corners in plan view.
  • a plurality of first conductive patterns arranged in a first direction and embedded in a first dielectric layer are formed.
  • a second dielectric layer is formed over the plurality of first conductive patterns and the first dielectric layer.
  • a plurality of openings in the second dielectric layer each over a corresponding one of the plurality of first conductive patterns are formed by a first patterning operation.
  • a blanket layer of a conductive material is formed over the second dielectric layer and in the plurality of opening. The blanket layer of the conductive material is patterned to form a plurality of second conductive patterns connected to a corresponding one of the plurality of first conductive patterns by a second patterning operation.
  • a third dielectric layer is formed over the plurality of second conductive patterns.
  • the plurality of openings as a whole are shifted in the first direction by a shift amount more than 0.1 ⁇ m from the plurality of first conductive pattern as a whole in plan view.
  • a center line of adjacent two of the plurality of first conductive patterns in the first direction is shifted in the first direction by the shift amount from a center line of adjacent two of the plurality of second conductive patterns in the first direction in plan view.
  • a thickness of the plurality of first conductive patterns is greater than a thickness of the plurality of second conductive pattern above the second dielectric layer.
  • the thickness of the plurality of first conductive patterns is in a range from 3 ⁇ m to 5 ⁇ m
  • the thickness of the plurality of second conductive pattern above the second dielectric layer is in a range from 1.0 ⁇ m to 3.0 ⁇ m.
  • a top size of each of the plurality of openings is smaller than a largest width of each of the plurality of second conductive patterns.
  • lower conductive patterns arranged in a column-row matrix are formed, wherein a first space between adjacent columns is in a range from 0.8 ⁇ m to 1.2 ⁇ m.
  • a first dielectric layer is formed over the lower conductive patterns.
  • Upper conductive patterns are formed over the lower conductive patterns and are arranged in a column-row matrix, and a second space between adjacent columns is greater than a first space.
  • a center line of adjacent columns of the lower conductive patterns is shifted in a row direction by a shift amount more than 0.1 ⁇ m from a center line of adjacent two columns of the plurality of upper conductive patterns in plan view.
  • a first island pattern is provided at a same level as the lower conductive patterns
  • a second island pattern is provided at a same level as the upper conductive patterns
  • a center of the first island pattern is aligned with a center of the second island pattern.
  • a semiconductor device includes a semiconductor circuit disposed over a substrate; lower conductive patterns disposed over and electrically coupled to the semiconductor circuit, wherein the lower conductive patterns include a first column of patterns in which a plurality of conductive patterns are arranged in a first direction and a second column of patterns in which a plurality of conductive patterns are arranged in the first direction, and the first column and the second column are adjacent to each other in a second direction crossing the first direction; a first dielectric layer disposed over the lower conductive patterns; upper conductive patterns disposed over the lower conductive patterns, wherein the upper conductive patterns include a third column of patterns in which a plurality of conductive patterns are arranged in the first direction and a fourth column of patterns in which a plurality of conductive patterns are arranged in the first direction, and the third column and the fourth column are adjacent to each other in the second direction; and a second dielectric layer disposed over the upper conductive patterns.
  • a first center line extending in the first direction between the first and second columns is shifted in the second direction by a shift amount more than 0.1 ⁇ m from a second center line extending in the first direction between the third and fourth columns in plan view.
  • the second center line overlaps one of the first column or the second column.
  • the shift amount is more than S/2 where S is a space between the first column and the second column.
  • the shift amount is more than S/2+0.1 ⁇ m.
  • S is in a range from 0.8 ⁇ m to 1.2 ⁇ m.
  • the second dielectric layer comprises peaks over the third column and the fourth column, and a valley between the third column and the fourth column. In one or more of the foregoing or following embodiments, the valley overlaps one of the first column or the second column in plan view. In one or more of the foregoing or following embodiments, the second dielectric layer comprises a crack from the valley to at least one of the plurality of conductive patterns of the second column. In one or more of the foregoing or following embodiments, the crack does not penetrate below bottoms of the lower conductive patterns.
  • the lower conductive patterns have a rectangular shape in plan view having first sides with a width L 1 along the first direction and second sides with a width L 2 along the second direction in plan view, and 0.95 ⁇ L 1 /L 2 ⁇ 1.05.
  • the upper conductive patterns have a rectangular shape in plan view having first sides with a width L 3 along the first direction and second sides with a width L 4 along the second direction in plan view, and 0.95 ⁇ L 3 /L 4 ⁇ 1.05.
  • the widths L 3 and L 4 are smaller than the widths L 1 and L 2 .
  • a semiconductor device includes a semiconductor circuit disposed over a substrate; wiring patterns embedded in a first interlayer dielectric (ILD) layer, and disposed over and electrically coupled to the semiconductor circuit; a second ILD layer disposed over the wiring patterns; pad electrodes disposed over and connected to the wiring patterns, respectively; and a passivation layer disposed over the pad electrodes.
  • ILD interlayer dielectric
  • Each of the pad electrodes includes a lower portion embedded in the second ILD layer and an upper portion above a surface of the second ILD layer.
  • the wiring patterns comprise a first matrix of patterns, and upper portions of the pad electrodes comprise a second matrix of patterns.
  • each of the first matrix and the second matrix is an M ⁇ N matrix, where M and N are natural number and at least one of M or N is 4 or more, and at least one of a column length and a column length of the M ⁇ N matrix is more than 100 ⁇ m.
  • M is 2 and N is 4 or more.
  • the shift amount is more than S/2+0.1 ⁇ m, where S is a space between adjacent wiring patterns.
  • the wiring patterns are made of Cu or a Cu alloy in which a majority is Cu, and the pad electrodes are made of Al or an Al alloy in which a majority is Al.
  • a semiconductor device includes a semiconductor circuit disposed over a substrate; wiring patterns disposed on a peripheral area, wherein the wiring patterns are embedded in a first interlayer dielectric (ILD) layer, and disposed over and electrically coupled to the semiconductor circuit; a second ILD layer disposed over the wiring patterns; pad electrodes disposed on the peripheral area and disposed over and connected to the wiring patterns, respectively; and a passivation layer disposed over the pad electrodes.
  • ILD interlayer dielectric
  • the wiring patterns comprise a 2 ⁇ N matrix
  • the pad electrodes comprises a 2 ⁇ N matrix, where N is a natural number of 4 or more, and a center of the second matrix is laterally shifted by a shift amount more than 0.1 ⁇ m with respect to a center of the first matrix toward outside the peripheral area or inside the peripheral area in plan view.
  • the peripheral area has a frame shape.
  • the shift amount is more than S/2+0.1 ⁇ m, where S is a space between adjacent wiring patterns.

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US17/587,605 2021-07-22 2022-01-28 Semiconductor device and method of manufacturing the same Pending US20230021655A1 (en)

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US17/587,605 US20230021655A1 (en) 2021-07-22 2022-01-28 Semiconductor device and method of manufacturing the same
DE102022102730.9A DE102022102730A1 (de) 2021-07-22 2022-02-07 Halbleitervorrichtung und verfahren zu ihrer herstellung
TW111111331A TWI843076B (zh) 2021-07-22 2022-03-25 半導體裝置及其製造方法
KR1020220039183A KR20230015263A (ko) 2021-07-22 2022-03-29 반도체 디바이스 및 그 제조 방법
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