CN115312477A - Chip packaging structure and chip module - Google Patents
Chip packaging structure and chip module Download PDFInfo
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- CN115312477A CN115312477A CN202210790543.2A CN202210790543A CN115312477A CN 115312477 A CN115312477 A CN 115312477A CN 202210790543 A CN202210790543 A CN 202210790543A CN 115312477 A CN115312477 A CN 115312477A
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- chip
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- package structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
Abstract
The invention relates to the technical field of chip packaging, and particularly provides a chip packaging structure and a chip module. The chip packaging structure comprises a substrate, a chip device, a bearing structure and a plastic packaging material, wherein a first step is formed on the chip device, the chip device is inversely arranged on the substrate, and the first step is matched with the bearing structure, so that a cavity is formed among the chip device, the bearing structure and the substrate.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip module.
Background
With the demand for miniaturization and cost reduction of electronic devices, flip chip mounting processes have come to be used. In flip-chip mounting, the chip is mounted on the substrate using bumps. Part of the chips with special functions are required to have a cavity structure between the chip and the substrate in the packaging process so as to meet the functions, performances or other special requirements of the chips, such as a Surface Acoustic Wave (SAW) filter chip, a Bulk Acoustic Wave (BAW) filter chip and the like.
In order to protect the chip from the external environment, the prior art generally covers the surface of the chip with a protective film so as to form a sealed cavity between the chip and the substrate. However, in practice, it is found that the film-coating method generally has the condition that the package structure is unstable, the air tightness is easily damaged under some severe environments, and a part of sealing material flows into the cavity through the gap between the chip and the substrate in the process treatment, so that the chip fails to function or the performance is reduced. Therefore, how to improve the reliability of such chip package structures has become an urgent problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a chip packaging structure and a chip module, which can prevent plastic packaging materials from flowing into a cavity in the plastic packaging process and improve the reliability of the packaging structure.
A first aspect of an embodiment of the present invention provides a chip packaging structure, including:
a substrate;
the chip device is formed with a first step, the first step comprises a first surface and a second surface, the chip device is inversely arranged on the substrate, and the distance between the first surface and the substrate is larger than the distance between the second surface and the substrate;
a carrier structure disposed on the substrate around the chip device, and at least a portion of the carrier structure extends between the first step and the substrate;
and the plastic packaging material covers the chip device and the bearing structure, so that a cavity is formed between the chip device and the bearing structure as well as between the chip device and the substrate.
Optionally, the second surface is a surface of the middle region of the chip device opposite to the substrate, and the first surface surrounds the second surface.
Optionally, at least a portion of the first surface is opposite to a side of the carrying structure away from the substrate.
Optionally, the bearing structure is formed with a second step matching with the first step.
Optionally, the second step includes a third surface and a fourth surface, and a distance between the third surface and the substrate is smaller than a distance between the fourth surface and the substrate;
the first surface is opposite the fourth surface, and a portion of the second surface is opposite the third surface; or, the first surface is opposite to the third surface, and the second surface is opposite to the substrate.
Optionally, a gap exists between the bearing structure and the first step.
Optionally, the bearing structure is attached to the first step.
Optionally, the molding compound includes a sealing resin containing particles.
Optionally, the chip package structure further includes a first sealing member, and the first sealing member is located in the gap.
Optionally, the chip package structure further includes a second sealing member, a portion of the second sealing member covers a surface of the chip device away from the substrate, and another portion of the second sealing member covers a surface of the carrier structure away from the substrate.
Optionally, the gap is less than or equal to the maximum particle size of the particulate matter.
Optionally, the gap is within a preset range.
Optionally, the sealing component is made of low-volatility material or non-volatility material.
Optionally, the chip device is a filtering chip device.
Optionally, the chip device is a non-filtering chip device.
A second aspect of the embodiments of the present invention provides a chip module including any one of the chip package structures described above.
In the embodiment of the invention, the chip packaging structure comprises a substrate, a chip device, a bearing structure and a plastic packaging material, wherein a first step is formed on the chip device, the chip device is inversely arranged on the substrate, and the first step and the bearing structure are mutually matched, so that a cavity is formed among the chip device, the bearing structure and the substrate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic diagram of a chip package structure according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a chip apparatus according to an embodiment of the present invention;
fig. 3 is a schematic diagram of another chip package structure provided in the embodiment of the present invention;
fig. 4 is a schematic diagram of a chip package structure provided in an embodiment of the invention;
FIG. 5 is a schematic diagram of another chip apparatus according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a chip package structure provided in an embodiment of the invention;
fig. 7 is a schematic diagram of a chip package structure provided in an embodiment of the invention;
fig. 8 is a schematic diagram of another chip package structure provided in an embodiment of the invention;
fig. 9 is a schematic diagram of another chip package structure provided in an embodiment of the invention;
fig. 10 is a schematic diagram of a chip package structure provided in an embodiment of the invention;
fig. 11 is a schematic diagram of another chip package structure according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to," "connected to" or "connected to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under 82303030," "under 823030; below," "under 823030; above," "over," etc. may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230, below" and "at 8230, below" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip module. In practice, it has been found that during the process of packaging the chip device, a part of the resin may flow into the cavity through the gap between the chip device and the substrate due to high temperature, so that the chip fails to function or the performance is reduced. In order to solve the above problems, the inventive concept of the present application will be specifically described by the following embodiments:
the chip device mentioned in the embodiment of the present invention may be a filtering function chip device such as a surface acoustic wave filter, a bulk acoustic wave filter, etc. that requires a cavity, or may be a non-filtering function chip device such as a power amplifier, etc. The substrate may include resin, ceramic, quartz, etc., and the support structure may be a structure formed on the substrate by a material with good formability and good solder mask performance, or a solder mask structure of the substrate, such as resin, solder mask green paint, dry film, etc., which is not limited in the embodiments of the present invention.
It should be noted that the embodiments of the present invention may be applied to a package structure of a single or multiple filter function chip devices that require a cavity, or may be applied to a package structure of a single or multiple non-filter function chip devices, or may be applied to a package structure of a chip module, where the module includes a filter function chip device and a non-filter function chip device.
In one embodiment, please refer to fig. 1 to 5. As shown in fig. 1, fig. 1 is a schematic view of a chip package structure provided in an embodiment of the present invention, and includes a substrate 1, a chip device 2, a carrier structure 3, and a molding compound 4.
The pad 11 is disposed on one surface of the substrate 1, and the pad 11 may be embedded in the substrate 1 or disposed on the surface of the substrate 1. The bonding pad 11 may be a metal or an alloy, the metal may be nickel, palladium, molybdenum, tungsten, ruthenium, gold, magnesium, aluminum, copper, chromium, titanium, osmium, iridium, or the like, and the bonding pad 11 is connected to an external circuit through a wiring (not shown) on the substrate 1.
In this embodiment, the chip device 2 is flip-chip mounted on the substrate 1. Specifically, the chip device 2 includes a bump structure 23, and the bump structure 23 may be tin, gold, or the like, or may be a metal bump, which is not limited in this embodiment. One end of the bump structure 23 is connected to a wiring (not shown) in the chip device 2, the chip device 2 is flip-chip mounted on the pad 11 through the bump structure 23, and the chip device 2 is connected to an external circuit through the bump structure 23 and the pad 11.
The chip arrangement 2 is formed with a first step 21, the first step 21 comprising a first surface 211 and a second surface 212, the chip arrangement 2 being flip-chip mounted on the substrate 1 such that the first surface 211 and the second surface 212 are opposite the substrate and the distance between the first surface 211 and the substrate 1 is larger than the distance between the second surface 212 and the substrate 1.
It will be appreciated that the above mentioned distance refers to the vertical distance between the two, i.e. the minimum distance, for example the vertical distance between the first surface 211 and the side of the substrate 1 facing the chip arrangement 2. The distance mentioned in the following description also refers to a vertical distance, and the description of this embodiment is omitted.
In one embodiment, the second surface 212 is a surface of the chip device 2 opposite to the substrate 1 in the middle region, and the first surface 211 surrounds the second surface 212, as shown in fig. 1 and 2. Fig. 2 is a schematic structural diagram of a chip apparatus provided in an embodiment of the present invention, that is, a top view of the chip apparatus 2 before being flipped. In fig. 2, the chip component 22 and the bump structure 23 are disposed on the second surface 212, the chip component 22 and the bump structure 23 are connected by a metal wire, not shown in the figure, and the first surface 211 is disposed around the second surface 212, so as to form the first step 21, i.e. the first step 21 is formed around the chip device 2.
In another embodiment, the first surface 211 may be a portion of an edge of the chip device 2, and the second surface 212 is a surface other than the first surface 211, as shown in fig. 3 to 5. Fig. 3 is a schematic diagram of another chip package structure provided in an embodiment of the present invention, fig. 4 is a schematic diagram of another chip package structure provided in an embodiment of the present invention, and fig. 5 is a schematic diagram of another chip device provided in an embodiment of the present invention. In fig. 3 to 5, the first step 21 is formed only on a part of the edge of the chip device 2, and fig. 5 shows that only two sides of the chip device 2 are formed with steps.
It should be noted that the first step 21 may have one step or multiple steps, and the embodiment only describes that the first step has one step.
It can be understood that the first step of the chip device 2 can be realized by step cutting, and the cutting manner can be laser cutting, plasma cutting, physical knife, and the like, and the embodiment is not limited.
In this embodiment, the supporting structure 3 is disposed on the substrate 1 around the chip device 2, and at least a portion of the supporting structure 3 extends between the first step 21 of the chip device 2 and the substrate 1. That is, an orthographic projection of the first step 21 in the substrate direction is at least partially on a surface of the carrying structure 3 remote from the substrate 1. Orthographic projection is understood to mean a projection perpendicular to the substrate.
In an embodiment, in the case that the chip apparatus 2 is configured as shown in fig. 1 and fig. 2, portions of the carrying structures 3 close to the chip apparatus 2 may both extend between the first step 21 and the substrate 1, or a portion thereof may extend between the first step 21 and the substrate 1, which is not limited in this embodiment.
In another embodiment, in the case that the chip arrangement 2 has the structure as shown in fig. 3 to 5, the portion of the carrying structure 3 close to the chip arrangement 2 may only extend between the first step 21 and the substrate 1, or may extend between the edge of the chip arrangement 2 where no step is formed and the substrate 1.
In this embodiment, at least a portion of the carrying structure 3 extends between the first step 21 and the substrate 1, which can be understood as that at least a portion of the first surface 211 of the first step 21 is opposite to a side of the carrying structure 3 away from the substrate 1, as shown in fig. 1 or 3; it is also understood that the first surface 211 of the first step 21 is entirely opposite to the side of the carrying structure 3 away from the substrate 1, and a portion of the second surface 212 is opposite to the side of the carrying structure 3 away from the substrate 1, as shown in fig. 4.
In the packaging process, the carrier structure 3 is disposed on the substrate 1, and a window is opened in a thickness direction (i.e., a direction perpendicular to a surface of the substrate) of the carrier structure 3, so that the pads 11 on the substrate 1 are exposed in the window, and then the chip device 2 is inverted in the window, so that the chip device 2 is connected to the pads 11 on the substrate 1 through the bump structures 23, thereby connecting external circuits.
In this embodiment, the molding compound 4 covers the chip device 2 and the supporting structure 3, and is specifically disposed on the surface away from the substrate 1, so that a cavity 5 is formed between the chip device 2, the supporting structure 3 and the substrate 1.
In this embodiment, set the edge of the face of the flip chip device 2 facing the substrate 1 to be the ladder structure, the bearing structure 3 extends to the edge between the chip device 2 and the substrate 1, so as to mutually match the ladder structure and the bearing structure 3, thereby avoiding the plastic package material 4 from flowing into the cavity 5 in the plastic package process, and improving the package reliability.
In another embodiment, please refer to fig. 6 to 9, fig. 6 is a schematic diagram of another chip package structure provided in the embodiment of the present invention, fig. 7 is a schematic diagram of another chip package structure provided in the embodiment of the present invention, fig. 8 is a schematic diagram of another chip package structure provided in the embodiment of the present invention, and fig. 9 is a schematic diagram of another chip package structure provided in the embodiment of the present invention. The structure shown in fig. 4 to fig. 7 is different from the structure of the previous embodiment in that the carrying structure 3 is different, and the rest of the structure is the same, and the description of this embodiment is omitted.
As shown in fig. 6, the carrying structure 3 is formed with a second step 31 cooperating with the first step 21.
Specifically, the second step 31 includes a third surface 311 and a fourth surface 312, where the third surface 311 and the fourth surface 312 are both sides of the supporting structure 3 away from the substrate 1, and a distance between the third surface 311 and the substrate 1 is smaller than a distance between the fourth surface 312 and the substrate 1.
In this embodiment, the carrying structure 3 is formed with the second step 31 matched with the first step 21, and it can be understood that the first step 21 and the second step 22 have the same number of steps, and the first step 21 and the second step 22 are used in cooperation, so that the edge of the chip device 2 is completely attached to the carrying structure 3, or a fine gap is formed, so that the plastic package material 4 is not easy to enter the cavity 5 in the plastic package process.
Specifically, after the chip arrangement 2 is flip-chip mounted on the substrate 1, the first surface 211 of the first step 21 is opposite to the fourth surface 312 of the second step 31, and a portion of the second surface 212 of the first step 21 is opposite to the third surface 311 of the second step 31, as shown in fig. 6. Alternatively, the first surface 211 of the first step 21 is opposite to the third surface 311 of the second step 31, and the second surface 212 of the first step 21 is opposite to the substrate, as shown in fig. 7.
It is understood that in the structure shown in fig. 6, the orthographic projection of the chip device 2 in the substrate direction is located such that the projection corresponding to the first surface 211 is located on the fourth surface 312 of the carrying structure 3 (all of the fourth surface 312 is possible, or a portion of the projection is located on the fourth surface 312 and another portion is located on the third surface 311), and the projection corresponding to the second surface 212 is located partially on the third surface 311 of the carrying structure 3 and another portion is located on the substrate 1. In the structure shown in fig. 7, an orthogonal projection of the chip device 2 in the substrate direction is located on the third surface 311 of the carrying structure 3 (all of the third surface 311 may be located, or a part of the third surface 311 may be located), and a corresponding projection of the second surface 212 is located on the substrate 1. In the above structure, the distance between the chip arrangement 2 (i.e. the second surface 212) and the substrate 1 is smaller than the thickness of the carrying structure 3.
Alternatively, there may be a gap or no gap between the carrying structure 3 and the first step 21, i.e. they fit each other, as shown in fig. 8. The first step 21 of the chip device 2 shown in fig. 8 may be in partial contact with the second step 32 of the carrier structure 3, or may be in full contact with the first step.
In one embodiment, a gap may exist between the bearing structure 3 and the first step 21 in a portion, and another portion may be attached.
In one embodiment, the second step 31 of the carrying structure 3 may be a step formed by processing the carrying structure 3 near the chip device 2, but not limited thereto, as shown in fig. 6 to 8; it is also possible to laminate a multilayer structure, forming a step close to the chip arrangement 2, as shown in fig. 9. In fig. 9, the carrier structure 3 is laminated by a two-layer structure and forms a second step.
Specifically, in the structure in which multiple layers are stacked to form a step, each layer may be implemented by liquid coating and/or dry film pressing, that is, each layer is implemented by the same method, or different layers are implemented by different methods, which is not limited in this embodiment.
In one embodiment, the distance between the surface of the chip arrangement 2 opposite the substrate 4 and the surface of the bonding pads 11 (i.e. the surface of the bonding pads 11 facing the chip arrangement 2) in the thickness direction of the bonding pads 11 is typically between 5um and 30 um. Preferably, the distance may be between 10um and 20 um. In one case, the distance can be between 45um-50 um.
In one embodiment, a molding compound 4 covers the chip device 2 and the supporting structure 3, and the molding compound 4 may be a sealing resin containing particles or other weak-flowing resinAn insulating material. Wherein the particulate matter may be silicon dioxide (SiO) 2 ) The particles may also be aluminum oxide (Al) 2 O 3 ) The particles may be a combination of a plurality of particles, and this embodiment is not limited thereto.
Through this embodiment, first step 21 of chip device 2 and second step 31 of bearing structure 3 mutually support for there is only tiny clearance or zero clearance between chip device 2 and the bearing structure 3, thereby makes in the plastic envelope in-process plastic envelope material 4 can not flow into the cavity through between bearing structure 3 and the chip device 2, improves chip package structure's reliability. Further, the plastic package material 4 is made of a material with low fluidity, such as a sealing resin containing particles, and the plastic package material 4 can be effectively blocked by the bearing structure 3 in the plastic package process, so that the plastic package material is further prevented from flowing into the cavity. Under general conditions, the material cost that the chip tectorial membrane adopted is higher, and this scheme of adoption makes and does not need the tectorial membrane in chip package, can also reduce manufacturing cost.
Further, in another embodiment, the gap between the carrier structure 3 and the chip device 2 is smaller than or equal to the maximum particle size of the particles included in the molding compound 4.
In this embodiment, the flowability of the sealing resin is reduced by mixing the particulate matter into the sealing resin, and the gap between the carrier structure 3 and the chip device 2 is smaller than or equal to the maximum particle size of the particulate matter, so that the particulate matter can be further prevented from flowing into the cavity through the gap between the carrier structure 3 and the chip device 2 in the plastic package process, and the reliability of the structure is further improved.
In another embodiment, the gap between the carrier structure 3 and the chip arrangement 2 is within a predetermined range. Specifically, the gap between the supporting structure 3 and the chip device 2 may be in the range of 0-15um, such as 0.2um, 0.5um, 1um, 3um, 7um or 10um; and may also be in the range of 0.1um to 5um. The gap between the carrier structure 3 and the chip arrangement 2 is sufficiently small to effectively prevent the molding compound from flowing into the cavity.
In still another embodiment, please refer to fig. 10 and fig. 11, where fig. 10 is a schematic diagram of another chip package structure provided by the embodiment of the present invention, fig. 11 is a schematic diagram of another chip package structure provided by the embodiment of the present invention, and specifically, fig. 10 and fig. 11 only show a portion enclosed by a dashed line in the chip package structure shown in fig. 6 and enlarge the portion.
As shown in fig. 10, the chip packaging structure further includes a first sealing member 6. The first sealing member 6 is located at the gap between the chip arrangement 2 and the carrier structure 3 to fill the gap and block the flow of molding compound 4 into the cavity 5.
In one embodiment, as shown in fig. 11, the chip package structure further includes a second sealing member 7, a portion of the second sealing member 7 covers a surface of the chip device 2 away from the substrate 1, and another portion covers a surface of the carrier structure 3 away from the substrate 1, as shown in fig. 11, so that an opposite or crossed region between the chip device 2 and the carrier structure 3 is isolated from the molding compound 4 during the molding process.
Further, a portion of the second sealing member 7 covers a surface of the chip arrangement 2 remote from the substrate 1, which may be understood as a portion of the second sealing member 7 completely covers a surface of the chip arrangement 2 remote from the substrate 1; it is also understood that a portion of the second sealing member 7 covers only an edge portion of the surface of the chip arrangement 2 remote from the substrate 1.
Further, another part of the second sealing member 7 covers the surface of the carrying structure 3 away from the substrate 1, which may be understood as that another part of the second sealing member 7 completely covers the surface of the carrying structure 3 away from the substrate 1, may be a surface other than the region opposite to or intersecting the chip arrangement 2, or may cover a part of the surface opposite to or intersecting the chip arrangement 2 while covering the above surface; it is also understood that another part of the second sealing member 7 only covers the surface of the area of the carrier structure 3 surrounding and adjacent to the chip arrangement 2.
Specifically, the first sealing member 6 and the second sealing member 7 may use a low-volatility material or a non-volatile material, the low-volatility material may include a low-volatility insulating material and a low-volatility resin material, and the low-volatility material may be understood as a material containing a low-volatility; non-volatile materials may include non-volatile insulating materials and non-volatile resin materials, which may be understood as materials that do not contain volatiles. The adhesive may be a nonconductive resin adhesive, an Ultraviolet light curing adhesive (UV) adhesive, an epoxy resin, a resin flux, or the like, which is not limited in the embodiment of the present invention. The first sealing component 6 can be realized by glue dispensing, printing, glue drawing and the like, and the second sealing component 7 can be realized by whole-surface spraying or partial-area spraying, so that the efficiency is improved.
The use of the low-volatility material for the first sealing member 6 and the second sealing member 7 means that the low-volatility material is included in the first sealing member 6 and the second sealing member 7, or the volatility of the entire first sealing member 6 and the second sealing member 7 is low, or the first sealing member 6 and the second sealing member 7 do not include the volatile material.
In one embodiment, low volatility may be understood as meaning that the entire sealing member does not volatilize during the packaging process (e.g., a reflow process), or there is a small proportion of volatilization that does not contaminate or cause less contamination of the cavity, does not affect the performance of the chip or cause the chip to fail.
In order to ensure the chip function, the first sealing part 6 and the second sealing part 7 are made of low-volatility materials or non-volatility materials, so that the situation that volatile matters are accumulated in the cavity 5 to pollute a chip functional area in the packaging or other processes can be avoided, and the reliability of a chip packaging structure is improved.
In this embodiment, the chip package structure is further provided with a sealing member, which can increase the reliability of the structure, so that the molding compound does not flow into the cavity.
In a further embodiment, not shown in the drawings, the surface of the chip arrangement 2 opposite the substrate 1 is provided with a first blocking member arranged around the chip element 22. The orthographic projection of the first barrier member in the substrate direction is located on the substrate 1 within the cavity 5. The first blocking component may be continuous or discontinuous, and this embodiment is not limited.
The height of the first blocking member may be the same as the height of the cavity 5, which may serve to support the chip device 2, and may serve as a secondary blocking for subsequent plastic encapsulation. The height of the first barrier means may also be less than the height of the cavity and may preferably be 5-15um.
In a further embodiment, not shown in the drawings, the substrate 1 is provided with a second barrier member, in particular on the side of the substrate 1 provided with the pads 11. The second stop member is located on the substrate 1 within the cavity 5, the orthographic projection of the second stop member in the direction of the chip arrangement being located outside the chip element 22.
It will be appreciated that the second barrier member is located outside the chip element 22 when the chip arrangement 2 is flip-chip mounted on the substrate 1. The second blocking component may be continuous or discontinuous, and this embodiment is not limited.
The height of the second blocking member may be the same as the height of the cavity 5, which may serve to support the chip device 2, and may serve as a secondary blocking for subsequent plastic encapsulation. The height of the second blocking means may also be smaller than the height of the cavity 2, preferably 5-15um.
Further, the first blocking part and the second blocking part may exist at the same time, and may be disposed in a staggered manner, or may be disposed opposite to each other in the thickness direction of the substrate 1, which is not shown in the figure, and the embodiment is not limited thereto.
It will be appreciated that on the basis of the above described embodiments, a first blocking member and/or a second blocking member may be provided.
In another embodiment, a chip module is disclosed, which includes the chip package structure described in the above embodiments, and details of this embodiment are not repeated.
The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (16)
1. A chip package structure, comprising:
a substrate;
the chip device is formed with a first step, the first step comprises a first surface and a second surface, the chip device is reversely arranged on the substrate, and the distance between the first surface and the substrate is larger than the distance between the second surface and the substrate;
a carrier structure disposed on the substrate around the chip device, and at least a portion of the carrier structure extends between the first step and the substrate;
and the plastic package material covers the chip device and the bearing structure, so that a cavity is formed between the chip device and the bearing structure as well as between the chip device and the substrate.
2. The chip package structure according to claim 1, wherein the second surface is a side of the middle region of the chip device opposite to the substrate, and the first surface surrounds the second surface.
3. The chip package structure according to claim 1 or 2, wherein at least a portion of the first surface is opposite to a side of the carrier structure away from the substrate.
4. The chip package structure according to claim 3, wherein the carrier structure is formed with a second step that mates with the first step.
5. The chip package structure according to claim 4, wherein the second step comprises a third surface and a fourth surface, and the distance between the third surface and the substrate is smaller than the distance between the fourth surface and the substrate;
the first surface is opposite to the fourth surface, and a part of the second surface is opposite to the third surface; or, the first surface is opposite to the third surface, and the second surface is opposite to the substrate.
6. The chip package structure according to claim 1, wherein a gap exists between the carrier structure and the first step.
7. The chip package structure according to claim 1, wherein the carrier structure is attached to the first step.
8. The chip package structure of claim 6, wherein the molding compound comprises a sealing resin containing particles.
9. The chip package structure according to claim 6, further comprising a first sealing member, the first sealing member being located at the gap.
10. The chip package structure according to claim 1, further comprising a second sealing member, a portion of the second sealing member covering a surface of the chip device away from the substrate, and another portion of the second sealing member covering a surface of the carrying structure away from the substrate.
11. The chip package structure according to claim 8, wherein the gap is less than or equal to a maximum particle size of the particulate matter.
12. The chip package structure according to claim 6, wherein the gap is within a predetermined range.
13. The chip package structure according to claim 9 or 10, wherein the sealing member is made of a low-volatility material or a non-volatility material.
14. The chip package structure according to claim 1, wherein the chip device is a filter function chip device.
15. The chip package structure according to claim 1, wherein the chip device is a non-filter function chip device.
16. A chip module comprising the chip package structure according to any one of claims 1 to 15.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210790543.2A CN115312477A (en) | 2022-07-06 | 2022-07-06 | Chip packaging structure and chip module |
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| CN202210790543.2A CN115312477A (en) | 2022-07-06 | 2022-07-06 | Chip packaging structure and chip module |
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