CN114530445A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN114530445A CN114530445A CN202210280601.7A CN202210280601A CN114530445A CN 114530445 A CN114530445 A CN 114530445A CN 202210280601 A CN202210280601 A CN 202210280601A CN 114530445 A CN114530445 A CN 114530445A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 192
- 239000010408 film Substances 0.000 claims description 91
- 239000010410 layer Substances 0.000 claims description 87
- 229910000679 solder Inorganic materials 0.000 claims description 82
- 239000011248 coating agent Substances 0.000 claims description 64
- 238000000576 coating method Methods 0.000 claims description 64
- 238000005520 cutting process Methods 0.000 claims description 28
- 239000013039 cover film Substances 0.000 claims description 25
- 230000017525 heat dissipation Effects 0.000 claims description 18
- 238000000465 moulding Methods 0.000 claims description 16
- 238000003466 welding Methods 0.000 claims description 9
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 239000003973 paint Substances 0.000 claims description 8
- 239000002245 particle Substances 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 2
- 238000000227 grinding Methods 0.000 description 11
- 210000002489 tectorial membrane Anatomy 0.000 description 11
- LIMFPAAAIVQRRD-BCGVJQADSA-N N-[2-[(3S,4R)-3-fluoro-4-methoxypiperidin-1-yl]pyrimidin-4-yl]-8-[(2R,3S)-2-methyl-3-(methylsulfonylmethyl)azetidin-1-yl]-5-propan-2-ylisoquinolin-3-amine Chemical compound F[C@H]1CN(CC[C@H]1OC)C1=NC=CC(=N1)NC=1N=CC2=C(C=CC(=C2C=1)C(C)C)N1[C@@H]([C@H](C1)CS(=O)(=O)C)C LIMFPAAAIVQRRD-BCGVJQADSA-N 0.000 description 10
- 238000011049 filling Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 5
- 239000003292 glue Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000000712 assembly Effects 0.000 description 3
- 238000000429 assembly Methods 0.000 description 3
- 230000032798 delamination Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 238000001914 filtration Methods 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010897 surface acoustic wave method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/64—Filters using surface acoustic waves
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Acoustics & Sound (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a chip packaging structure and a chip packaging method, and relates to the technical field of chip packaging. The chip packaging structure comprises a substrate, a first chip, a second chip, a covering film and a plastic package body, wherein the first chip and the second chip are arranged on the substrate at intervals; the periphery of the chip II is provided with a support column, the support column is connected with the substrate, the film covering covers the chip I, the chip II and the support column, and the plastic package body is arranged on one side of the film covering away from the chip I, so that a closed cavity is formed between the chip I and the substrate; the support columns support the covering films and are used for increasing the distance between the covering films and the substrate, so that the plastic package body breaks through the covering films on the outer sides of the second chips and is filled between the second chips and the substrate. The supporting columns are arranged, so that the plastic package body breaks through the film on the outer side of the chip II and is filled between the chip II and the substrate, meanwhile, the plastic package body can be prevented from breaking through the film corresponding to the chip I, the closed cavity at the bottom of the chip I is prevented from being polluted, the bottom of the chip II is completely filled, and the packaging quality is improved.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip packaging method.
Background
A surface acoustic wave filter (saw filter) is widely used in a receiver front end, a duplexer, a reception filter, and the like. The working principle of the surface acoustic wave filter is that sound waves are transmitted on the surface of a chip, the piezoelectric property of a piezoelectric material is adopted, an input signal of electric waves is converted into mechanical energy by an input Transducer and an output Transducer (Transducer), and the mechanical energy is converted into an electric signal after processing, so that unnecessary signals and noise are filtered, and the receiving quality is improved.
In order to ensure that the filter chip has a good filtering function, the functional area of the filter chip cannot contact any substance, and the filter chip is designed to be of a cavity structure. And other non-filter chips do not need to form a bottom cavity structure, and if the cavity structure is formed at the bottom of the non-filter chip, the reliability of the product is easily reduced. In the traditional packaging method, a diaphragm is mostly arranged on the back surface of the filter chip and used for isolating the plastic package body outside the filter chip so as to form a cavity structure at the bottom of the filter chip. Two packaging failure conditions easily occur in the packaging mode, firstly, the diaphragm is not broken by the plastic package fluid, so that cavity structures are formed at the bottoms of the filter chip and the non-filter chip, and the reliability of the product is reduced. Secondly, the diaphragm is easily broken by the plastic package fluid, which easily causes the cavity structure at the bottom of the filter chip to be polluted by the plastic package fluid and the filter function to be damaged.
Disclosure of Invention
The present invention provides a chip package structure and a chip package method, which can ensure that a sealed cavity at the bottom of a first chip is not contaminated, and can also ensure that a plastic package body between a second chip and a substrate is completely filled, thereby improving the package quality, and further improving the signal receiving quality and the product reliability of a product.
Embodiments of the invention may be implemented as follows:
in a first aspect, the invention provides a chip packaging structure, which comprises a substrate, a first chip, a second chip, a coating film and a plastic package body, wherein the first chip and the second chip are arranged on the substrate at intervals; a supporting column is arranged on the periphery of the second chip and connected with the substrate, the film covering covers are arranged on the first chip, the second chip and the supporting column, and the plastic package body is arranged on one side of the film covering far away from the first chip so as to form a closed cavity between the first chip and the substrate; the support columns support the covering films and are used for increasing the distance between the covering films and the substrate, so that the plastic package body breaks through the covering films on the outer sides of the second chip and is filled between the second chip and the substrate.
In an optional embodiment, a region of the cover film corresponding to the second chip is provided with a notch.
In an alternative embodiment, the size of the cut is at least two times larger than the particle size of the plastic package.
In an optional implementation manner, a first solder mask is arranged at a position on the substrate corresponding to the second chip, a first pad is arranged on the first solder mask, the first pad is electrically connected with the substrate, and the second chip is electrically connected with the first pad, so that a distance between one side surface of the second chip far away from the substrate and the substrate is greater than a distance between one side surface of the first chip far away from the substrate and the substrate.
In an optional implementation manner, a second solder mask is disposed at a position on the substrate corresponding to the first chip, a surface of the second solder mask corresponding to the first chip is flush with a surface of the first solder mask corresponding to the second chip, and the first solder mask and the second solder mask are continuously disposed.
In an alternative embodiment, a groove is provided on the first solder resist layer and/or the second solder resist layer to expose the substrate.
In an alternative embodiment, the first solder resist layer is provided with a recess at a position opposite to a position of the cut on the cover film. In an optional embodiment, a first supporting member is arranged on the substrate, the first supporting member is arranged on the periphery of the first chip, the coating is covered on the first supporting member, and a groove is arranged at one end, far away from the substrate, of the first supporting member.
In an alternative embodiment, the first support is serrated.
In an optional embodiment, a second pad is disposed on the substrate, the first chip is electrically connected to the second pad, and a second supporting member is disposed between the first chip and the substrate and disposed at a periphery of the second pad.
In an alternative embodiment, the distance between the side of the second chip close to the substrate and the substrate is greater than the distance between the surface of the side of the first chip close to the substrate and the substrate.
In an optional implementation manner, a heat dissipation layer is arranged on one side of the second chip far away from the substrate, and the covering film is laid on the heat dissipation layer.
In an optional embodiment, a glue layer is disposed on one side of the second chip away from the substrate, and the heat dissipation layer is disposed on one side of the glue layer away from the second chip.
In an alternative embodiment, the cover film is not disposed on a side of the second chip away from the substrate.
In an optional embodiment, the first chip, the second chip and the supporting columns are configured as component combinations, a plurality of the component combinations are arranged on the substrate at intervals, a cutting channel is arranged between two adjacent component combinations, a supporting column is arranged on the cutting channel, and the covering film is laid on the supporting column.
In an alternative embodiment, the width of the scribe line is greater than the width of the support post.
In a second aspect, the present invention provides a packaging method for fabricating a chip package structure as described in any one of the previous embodiments, the method comprising:
providing a substrate;
arranging a support column on the substrate;
mounting a first chip and a second chip on the substrate; the supporting column is arranged on the periphery of the second chip;
laying a covering film on the substrate, wherein the covering film covers the first chip, the supporting column and the second chip;
arranging a plastic package body outside the covering film, wherein the covering film is used for blocking the plastic package body at the outer side of the first chip so as to form a closed cavity between the first chip and the substrate; the plastic package body is used for breaking the covering film on the outer side of the second chip, and the supporting columns are used for increasing the distance between the covering film and the substrate in the corresponding areas of the second chip so that the plastic package body is filled between the second chip and the substrate.
In an alternative embodiment, the step of providing a substrate comprises:
providing a substrate, wherein a second bonding pad is arranged on the substrate and is used for being connected with the first chip;
coating a green paint layer on the substrate to form a first solder mask layer at a corresponding position for mounting the second chip and a second solder mask layer at a corresponding position for mounting the first chip; a first welding pad is arranged on the first solder mask layer and is electrically connected with the substrate, and the first welding pad is used for being electrically connected with the second chip, so that the plane where the first welding pad is located is higher than the plane where the second welding pad is located, and/or the distance between the surface of one side, away from the substrate, of the second chip and the substrate is larger than the distance between the surface of one side, away from the substrate, of the first chip and the substrate;
the step of providing support posts on the substrate includes:
the base plate is provided with a support column and a first support piece, and the first support piece is provided with a groove.
In an alternative embodiment, after the step of laying the coating film on the substrate, the method further includes:
and forming a cut on the covering film, wherein the cut is positioned in a corresponding area of the second chip, and the size of the cut is at least two times larger than the particle size of the plastic package body.
The beneficial effects of the embodiment of the invention include, for example:
according to the chip packaging structure provided by the embodiment of the invention, the supporting columns are arranged at the periphery of the second chip, and support the covering film around the second chip, so that the covering film is supported, the distance between the covering film and the substrate is increased, and the surface tension of the covering film is increased, so that the covering film on the outer side of the second chip can be conveniently broken by the plastic package mold flow and filled between the second chip and the substrate, the plastic package body at the bottom of the second chip is more completely filled, and the packaging reliability of the second chip is improved. Meanwhile, the coating film is arranged on the back surface of the first chip, a closed cavity can be formed between the first chip and the substrate, the functional area of the first chip is prevented from being polluted, the signal receiving quality is improved, the packaging quality is good, and the reliability is high.
The packaging method provided by the embodiment of the invention can ensure that the closed cavity at the bottom of the first chip is not polluted, can also ensure that the plastic package body between the second chip and the substrate is completely filled, and can improve the packaging quality, thereby improving the signal receiving quality and the product reliability of the product. The packaging method is simple, the operability is strong, and the packaging efficiency is high.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a first schematic diagram of a chip package structure according to an embodiment of the invention;
fig. 2 is a second schematic diagram of a chip package structure according to an embodiment of the invention;
fig. 3 is a third schematic view of a chip package structure according to an embodiment of the invention;
fig. 4 is a fourth schematic diagram of a chip package structure according to an embodiment of the invention;
fig. 5 is a fifth schematic view of a chip package structure according to an embodiment of the invention;
fig. 6 is a sixth schematic view of a chip package structure according to an embodiment of the invention;
fig. 7 is a seventh schematic view of a chip package structure according to an embodiment of the invention;
fig. 8 is a main flowchart of a packaging method according to an embodiment of the present invention.
Icon: 100-chip package structure; 110-a substrate; 111-a first solder mask layer; 113-a second solder mask layer; 115-first bonding pad; 117-second pad; 120-chip one; 121-closed cavity; 130-chip two; 140-coating a film; 141-incision; 150-plastic package body; 160-support column; 118-a groove; 170-a first support; 171-a trench; 180-a second support; 191-a heat dissipation layer; 193-glue layer; 195-cutting the tract.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1, the present embodiment provides a chip package structure 100, including a substrate 110, a first chip 120, a second chip 130, a film 140 and a plastic package body 150, wherein the first chip 120 and the second chip 130 are disposed on the substrate 110 at an interval; a supporting column 160 is arranged on the periphery of the second chip 130, the supporting column 160 is connected with the substrate 110, the first chip 120, the second chip 130 and the supporting column 160 are covered by the coating film 140, and the plastic package body 150 is arranged on one side of the coating film 140 far away from the first chip 120, so that a closed cavity 121 is formed between the first chip 120 and the substrate 110; the supporting pillars 160 support the cover film 140, and the supporting pillars 160 are used to increase the distance between the cover film 140 and the substrate 110, so that the molding compound 150 breaks the cover film 140 outside the second chip 130 and fills the space between the second chip 130 and the substrate 110. The packaging structure can ensure that the closed cavity 121 is formed at the bottom of the first chip 120, prevent the functional area of the first chip 120 from being polluted, improve the product quality, ensure that the plastic package body 150 filled between the bottom of the second chip 130 and the substrate 110 is more sufficient and complete, and improve the product reliability. The first chip 120 includes but is not limited to a surface acoustic wave filter chip, and a filtering function needs to be realized in a structure of the closed cavity 121; the second chip 130 is a non-filtering chip, including but not limited to an antenna switch, a low noise amplifier, a capacitor, an inductor, or other chips.
Referring to fig. 2, the supporting pillars 160 are disposed at the periphery of the second chip 130, and since the first chip 120 and the second chip 130 are disposed at an interval, the supporting pillars 160 are also located between the first chip 120 and the second chip 130. Optionally, the area of the cover film 140 corresponding to the second chip 130 is provided with a notch 141, that is, the notch 141 of the cover film 140 is located in the area corresponding to the second chip 130. It is understood that the area of the cover film 140 corresponding to the second chip 130 includes the area of the cover film 140 directly opposite to the second chip 130 and the area of the cover film 140 between the support posts 160 and the second chip 130. The strength of the coating film 140 at the position of the second chip 130 is weakened through the arrangement, so that the coating film 140 corresponding to the second chip 130 is more easily broken by mold flow of the plastic package body 150, the plastic package body 150 can conveniently enter the bottom of the second chip 130, a gap between the second chip 130 and the substrate 110 is filled, and the reliability of a product is improved. In this embodiment, the size of the notch 141 is at least two times larger than the particle size of the molding compound 150, which is favorable for the molding compound 150 to smoothly enter the bottom of the second chip 130.
The first solder mask layer 111 is arranged on the substrate 110 at a position corresponding to the second chip 130, the first solder mask layer 111 is provided with a first solder pad 115, the first solder pad 115 is electrically connected with the substrate 110, and the second chip 130 is electrically connected with the first solder pad 115, so that the distance from the surface of one side, away from the substrate 110, of the second chip 130 to the substrate 110 is greater than the distance from the surface of one side, away from the substrate 110, of the first chip 120 to the substrate 110. Optionally, a second bonding pad 117 is disposed on the substrate 110, and the first chip 120 is soldered to the second bonding pad 117. The distance from the surface of the first pad 115, which is far away from the substrate 110, to the substrate 110 is H1, the distance from the surface of the second pad 117, which is far away from the substrate 110, to the substrate 110 is H2, and due to the first solder mask layer 111, H1 is greater than H2, that is, the height of the first pad 115 is greater than the height of the second pad 117. In this way, when the first chip 120 and the second chip 130 have the same size, the coating film 140 is laid on the back surfaces of the first chip 120 and the second chip 130, the distance from the coating film 140 to the substrate 110 in the region of the second chip 130 is H3, and the first solder resist layer 111 is provided, so that H3 is the distance from the coating film 140 to the first solder resist layer 111. The provision of the first solder resist layer 111 increases H1 and further increases the surface tension of the coating film 140, so that the mold flow of the mold package body 150 more easily breaks through the coating film 140 in the second chip 130 region during molding. It can be understood that, during plastic packaging, the mold flow of the plastic package body 150 impacts the gap between the bottom of the second chip 130 and the substrate 110, and due to the arrangement of the first solder resist layer 111, the gap distance between the bottom of the second chip 130 and the substrate 110 is increased, so that the mold flow impact area is larger, the coating film 140 at the second chip 130 is more easily broken, and the bottom of the second chip 130 is better filled with the plastic package body 150.
Optionally, a second solder mask layer 113 is disposed on the substrate 110 at a position corresponding to the first chip 120, a surface of the second solder mask layer 113 corresponding to the first chip 120 is flush with a surface of the first solder mask layer 111 corresponding to the second chip 130, and the first solder mask layer 111 and the second solder mask layer 113 are disposed continuously. The arrangement is convenient for the arrangement of the solder mask layer, the step structure formed by the solder mask layer arranged on one part of the substrate 110 and the solder mask layer not arranged on the other part of the substrate 110 is avoided, if the step structure is arranged on the surface of the substrate 110, the flowability of the plastic package body 150 is reduced, the problem of filling and back-packaging is easily caused, and the packaging quality is reduced. In this embodiment, the first solder mask layer 111 and the second solder mask layer 113 are continuously disposed and have flush surfaces, so that the flowability of the plastic-sealed body 150 can be improved, and the problem of filling and recoiling can be avoided. It can be understood that, since the first solder mask layer 111 and the second solder mask layer 113 are continuously disposed and the surfaces are flush, i.e., the region between the first chip 120 and the second chip 130 is also disposed with a solder mask layer, the flatness and the continuity of the structure surface can be maintained, and the filling back can be avoided.
Referring to fig. 3, the first solder resist layer 111 and/or the second solder resist layer 113 are provided with a groove 118 to expose the substrate 110. It is understood that the position and number of the grooves 118 may be determined according to practical situations, and the pads or the copper layer on the substrate 110 may be exposed by forming the grooves 118, and the base material layer of the substrate 110, i.e. the underlying BT resin layer, may also be exposed, and is not limited specifically herein. In this embodiment, set up recess 118 on first solder mask 111, when filling plastic-sealed body 150, plastic-sealed body 150 fills to in the recess 118, can promote the cohesion of plastic-sealed body 150 and first solder mask 111, also can promote the cohesion of the substrate layer of first solder mask 111 and base plate 110 and promote the cohesion of tectorial membrane 140 and base plate 110 substrate layer, improve structural reliability, prevent the structural stratification phenomenon, thereby promote the cohesion between tectorial membrane 140 and the base plate 110, and the cohesion between tectorial membrane 140 and the first solder mask 111. Further, the position of the groove 118 on the first solder resist layer 111 corresponds to the position of the notch 141 on the second chip 130 area coating film 140, that is, after the notch 141 is formed on the coating film 140, for example, the notch 141 is formed by laser cutting, and the groove 118 on the first solder resist layer 111 can be exposed from the notch 141, so that more mold flows of the mold package body 150 can be ensured to enter the groove 118, the bonding force between the mold package body 150 and the substrate 110, and between the mold package body 150 and the first solder resist layer 111 can be improved, and the structural reliability can be improved.
Referring to fig. 4, optionally, a first supporting element 170 is disposed on the substrate 110, the first supporting element 170 is disposed on the periphery of the first chip 120, the coating 140 is covered on the first supporting element 170, and a groove 171 is disposed at an end of the first supporting element 170 away from the substrate 110. In this embodiment, the first support member 170 is similarly serrated. Through setting up the slot 171, be favorable to improving the cohesion between tectorial membrane 140 and the second solder mask 113 to promote the cohesion of first chip 120 edge and tectorial membrane 140, prevent that the tectorial membrane 140 at first chip 120 edge from being broken by the punching when the plastic envelope. The first support 170 can block mold flow during plastic packaging, reduce the mold flow of the plastic package body 150 from impacting the coating film 140 at the edge, and prevent the coating film 140 from being broken. Optionally, the first support 170 is disposed near the edge of the first chip 120, which is more effective in blocking the mold flow.
In this embodiment, the second supporting member 180 is disposed between the first chip 120 and the substrate 110, and the second supporting member 180 is disposed at the periphery of the second bonding pad 117 to further block mold flow and buffer mold flow impact, so as to protect the cover film 140 from being flushed into the bottom of the sidewall of the first chip 120 by the mold flow of the molding compound 150, and to ensure that the structure of the closed cavity 121 at the bottom of the first chip 120 is not contaminated. Optionally, the second supporting member 180 is disposed at the bottom of the first chip 120 and is flush with the sidewall of the first chip 120, which has better blocking and buffering effects, and can further block the mold flow from breaking the cover film 140 and prevent the cover film 140 or the mold flow from entering the closed cavity 121 at the bottom of the first chip 120.
With reference to fig. 5, optionally, the height of the second chip 130 may be higher than the height of the first chip 120, so that the distance from the covering film 140 on the back surface of the second chip 130 to the substrate 110 is larger, that is, the height difference between the surface of the second chip 130, which is away from the substrate 110, and the substrate 110 is larger, which is beneficial to increasing the tension of the covering film 140, so that the molding compound 150 easily breaks through the covering film 140 on the edge of the second chip 130 during the molding process, so that the molding compound can be better filled to the bottom of the second chip 130. It is understood that the greater distance from the bottom surface of the second chip 130 to the substrate 110 or the first solder mask layer 111 is also beneficial for the mold flow to break through the cover film 140, so that the mold flow can better fill the bottom of the second chip 130. Optionally, in a chip grinding step before chip mounting, the heights of the first chip 120 and the second chip 130 are controlled by a grinding process, and the grinding thickness of the first chip 120 is controlled to be greater than the grinding thickness of the second chip 130, so that the height of the second chip 130 after grinding is greater than the height of the first chip 120 after grinding, for example, the thickness of the first chip 120 after grinding is 200 micrometers, and the height of the second chip 130 after grinding is 400 micrometers, so that after chip mounting, the surface of the side, away from the substrate 110, of the second chip 130 is higher than the surface of the side, away from the substrate 110, of the first chip 120, and the distance between the coating 140 around the second chip 130 and the substrate 110 is increased, so as to increase the surface tension of the coating 140, so that mold flow of the plastic package body 150 more easily breaks the coating 140 around the second chip 130 and enters the bottom of the second chip 130.
With reference to fig. 6, in an alternative embodiment, a heat dissipation layer 191 may be further disposed on a side of the second chip 130 away from the substrate 110, and the coating film 140 may be laid on the heat dissipation layer 191. The heat dissipation layer 191 can be made of materials such as metal or ceramic, and the heat dissipation layer 191 not only can play a role in heat dissipation, but also can increase the distance between the coating film 140 and the substrate 110, so that the surface tension of the coating film 140 is improved, and the coating film 140 at the edge of the second chip 130 can be easily broken by the mold flow of the plastic package body 150 during plastic package. Furthermore, an adhesive layer 193 is disposed on a side of the second chip 130 away from the substrate 110, and the heat dissipation layer 191 is disposed on a side of the adhesive layer 193 away from the second chip 130. The heat dissipation layer 191 can be adhered and fixed on the back surface of the second chip 130 through the adhesive layer 193, the adhesive layer 193 can also play a role in heat dissipation, the distance between the coating film 140 and the substrate 110 is increased, and the surface tension of the coating film 140 is improved, so that the coating film 140 on the edge of the second chip 130 can be easily broken by the mold flow of the plastic package body 150 during plastic package.
It is easy to understand that if the distance from the side of the second chip 130 close to the substrate 110 is increased, the mold flow is favorable to break through the coating 140 at the edge of the second chip 130 and enter the bottom of the second chip 130. That is, the larger the gap between the bottom of the second chip 130 and the substrate 110, the easier it is to break the cover film 140, so that the molding compound 150 can smoothly enter the bottom of the second chip 130, and the filling is more complete. In this embodiment, the distance between the side of the second chip 130 close to the substrate 110 and the substrate 110 is greater than the distance between the surface of the first chip 120 close to the substrate 110 and the substrate 110. It should be noted that, the lifting of the bottom gap of the second chip 130 (the distance between the side of the second chip 130 close to the substrate 110 and the substrate 110), or the lifting of the height of the back side of the second chip 130, can ensure that the coating film 140 on the periphery of the second chip 130 is broken by the mold flow of the plastic package body 150, which is beneficial to more complete and sufficient filling of the plastic package body 150 at the bottom of the second chip 130, and improves the structural reliability.
With reference to fig. 7, it is understood that in other alternative embodiments, the coating film 140 may not be disposed on the side of the second chip 130 away from the substrate 110. That is, the coating film 140 is selectively disposed on the substrate 110, and the coating film 140 is only laid around the chip one 120, so as to ensure that the closed cavity 121 is formed at the bottom of the chip one 120. This can also ensure the plastic package body 150 at the bottom of the second chip 130 is filled more completely.
It is understood that the first chip 120, the second chip 130 and the supporting pillars 160 are configured as component assemblies, a plurality of component assemblies are arranged on the substrate 110 at intervals, a cutting channel 195 (see fig. 8) is arranged between two adjacent component assemblies, the supporting pillars 160 are arranged on the cutting channel 195, and the covering film 140 is laid on the supporting pillars 160. The support posts 160 are disposed on the cutting street 195, and in a subsequent cutting process, the components are separated into individual products by cutting along the cutting street 195, and the support posts 160 in the structure can be removed to reduce the weight, volume and size of the individual products. Alternatively, the width of the cutting channel 195 is greater than the width of the support post 160, and the support post 160 may be removed entirely. If the number of the supporting pillars 160 on the cutting street 195 is multiple, the width of the cutting street 195 should be larger than the distance between the supporting pillars 160, so that all the supporting pillars 160 on the cutting street 195 are removed along with the cutting street 195.
The chip package structure 100 provided by the embodiment of the invention mainly aims to ensure that the closed cavity 121 at the bottom of the first chip 120 is not affected, and simultaneously ensure that the mold flow of the plastic package body 150 fully enters the bottom of the second chip 130 to completely fill the bottom of the second chip 130. The surface tension of the coating 140 around the second chip 130 is increased by arranging the supporting columns 160; the height of the first welding pad 115 is raised by arranging the first solder mask layer 111, so that the gap at the bottom of the second chip 130 is increased, the distance between the back of the second chip 130 and the substrate 110 is increased, and the plastic package body 150 is ensured to flow to break through the coating film 140 and enter the bottom of the second chip 130; the adhesive layer 193 and the heat dissipation layer 191 are arranged on the back surface of the second chip 130, so that the distance between the back surface of the second chip 130 and the substrate 110 is increased, and the surface tension of the covering film 140 is increased; the notch 141 is arranged on the coating 140, so that the plastic package body 150 is ensured to break the coating 140 and enter the bottom of the second chip 130; grinding the second chip 130 to increase the gap at the bottom of the second chip 130; the bottom filling of the second chip 130 is ensured to be complete, and the structural reliability is improved. By providing the first support member 170 and the second support member 180 around the chip one 120, the first support member 170 is provided with grooves 171 and the like, which function to protect the closed cavity 121 at the bottom of the chip one 120. In addition, first solder mask 111 and second solder mask 113 set up and the surface flushes in succession, and the preparation of being convenient for improves encapsulation efficiency, prevents to fill the repackage etc. simultaneously. The grooves 118 are formed in the first solder mask layer 111 and the second solder mask layer 113, so that the bonding force among the coating film 140, the substrate 110 and the solder mask layers is improved, the structural delamination is prevented, and the structural reliability is improved.
It should be noted that the above technical solutions can be combined arbitrarily to form various embodiments without conflict or contradiction, so as to improve the reliability of the structure, ensure that the cavity structure at the bottom of the first chip 120 is not contaminated, and ensure that the bottom of the second chip 130 can be fully filled with the plastic package body 150.
Second embodiment
With reference to fig. 8, the present invention provides a packaging method for manufacturing the chip package structure 100 according to any of the foregoing embodiments, and the main processes include manufacturing the substrate 110, mounting the chip, vacuum coating the film 140, cutting the film 140, performing plastic encapsulation, and cutting to form a single product. The packaging method mainly comprises the following steps:
providing a substrate 110; disposing the supporting pillars 160 on the substrate 110; mounting a first chip 120 and a second chip 130 on a substrate 110; the supporting column 160 is arranged at the periphery of the second chip 130; laying a film 140 on the substrate 110, wherein the film 140 covers the first chip 120, the supporting pillar 160 and the second chip 130; arranging a plastic package body 150 outside the covering film 140, wherein the covering film 140 is used for blocking the plastic package body 150 at the outer side of the first chip 120 so as to form a closed cavity 121 between the first chip 120 and the substrate 110; the plastic package body 150 is used for breaking the coating film 140 on the outer side of the second chip 130 to fill the space between the second chip 130 and the substrate 110. So as to ensure that the cavity structure at the bottom of the first chip 120 is not contaminated and to ensure that the bottom of the second chip 130 can be sufficiently filled with the molding compound 150. The supporting posts 160 may be copper posts or a laminated resin material.
Optionally, the step of providing a substrate 110 includes:
providing a substrate 110, coating a green paint layer on the substrate 110 to form a first solder mask layer 111 at a position corresponding to the second mounted chip 130, and forming a second solder mask layer 113 at a position corresponding to the first mounted chip 120; the first solder mask layer 111 is provided with a first pad 115, the first pad 115 is electrically connected with the substrate 110, and the first pad 115 is used for electrically connecting the second chip 130, so that the distance from the surface of one side, away from the substrate 110, of the second chip 130 to the substrate 110 is greater than the distance from the surface of one side, away from the substrate 110, of the first chip 120 to the substrate 110. This configuration is advantageous for increasing the distance between the coating film 140 on the back surface (the surface away from the substrate 110) of the second chip 130 and the substrate 110, and for increasing the surface tension of the coating film 140. First solder mask 111 and second solder mask 113 set up in succession, and both surfaces flush, avoid appearing the uneven stair structure of height, fill the problem of repackage when preventing the plastic envelope.
Alternatively, the support pillars 160 may be disposed on the substrate 110, and then a layer of green paint may be applied to surround the second pads 117, so as to buffer and block the flow. The first bonding pad 115 is disposed on the green paint layer, and the first bonding pad 115 is electrically connected to a bonding pad on the substrate 110 to raise the mounting position of the second chip 130.
Alternatively, after applying the green paint layer, the first support 170 may be disposed on the substrate 110, and the first support 170 may be disposed on the green paint layer. In this embodiment, the first support member 170 is disposed on the periphery of the first chip 120, that is, the first support member 170 is disposed on the second solder mask layer 113. The grooves 171 are formed in the first support 170, and then the vacuum coating 140 process is used to lay the coating 140 on the substrate 110, so that the grooves 171 can increase the bonding force between the coating 140 and the first support 170, and prevent the coating 140 around the first chip 120 from being broken.
Optionally, a groove 118 may be formed in the green paint layer, that is, the groove 118 is formed in the first solder resist layer 111 and the second solder resist layer 113, so as to improve the bonding force with the plastic package body 150, improve the structural reliability, and prevent the structural delamination.
After the step of laying the cover film 140 on the substrate 110, a notch 141 is further formed on the cover film 140, the notch 141 is located in a corresponding area of the second chip 130, and the size of the notch 141 is at least two times larger than the particle size of the plastic package body 150, so that the mold flow of the plastic package body 150 in the plastic package process can smoothly pass through the cover film 140 to enter the bottom of the second chip 130, and the bottom of the second chip 130 is completely filled with the plastic package body 150. It will be readily appreciated that if the filled plastic body 150 has a particle diameter of about 25 microns, the width dimension of the cut 141 should be greater than 50 microns. The molding body 150 fills the cavity at the bottom of the second chip 130 through the notch 141, a non-cavity structure is formed at the bottom of the second chip 130, and the supporting column 160 plays a supporting role to increase the surface tension of the coating film 140. Meanwhile, the bonding force between the coating film 140 and the substrate 110 can be improved, the coating film 140 around the first chip 120 is prevented from being pulled and broken during plastic packaging, and the effect of protecting the closed cavity 121 at the bottom of the first chip 120 is achieved. Of course, the cut 141 on the coating film 140 may be provided in advance before being applied to the substrate 110, and is not particularly limited here.
It is understood that the number of the supporting columns 160 can be flexibly set according to practical situations, and is not particularly limited herein. In the cross-sectional view shown in fig. 1, the number of the supporting columns 160 in the cross-sectional view is two, but in other embodiments, it may be one, three, or five, etc. The cutting is performed along the cutting channel 195, and the width of the cutting channel 195 is greater than the distance between the two supporting pillars 160, that is, after the cutting, the supporting pillars 160 are removed along with the cutting channel 195, and a product without the supporting pillars 160 is formed, which is beneficial to reducing the weight of the product and reducing the size and volume of the product. In fig. 8, the dashed lines indicate the cutting street 195, and the distance between the two dashed lines indicates the width of the cutting street 195. And finally, packaging, testing and discharging the cut product to finish the manufacturing process.
It can be understood that, no matter the supporting posts 160 on the scribe line 195 or the supporting posts 160 at the periphery of the second chip 130, the supporting posts 160 are located between the first chip 120 and the second chip 130, the number of the supporting posts 160 may be one or more, if there are a plurality of supporting posts 160, since the supporting posts 160 are protruded on the surface of the substrate 110, a structural groove is formed between two adjacent supporting posts 160, when the plastic package body 150 is filled, the plastic package body 150 enters the structural groove, which can increase the bonding force between the coating film 140 and the substrate 110, and further improve the reliability of the structure.
Optionally, according to the actual process conditions, before the first die 120 is mounted, a grinding step for the first die 120 may be added; before mounting the second chip 130, adding a grinding step to the second chip 130; the steps of forming the grooves 118 in the first solder resist layer 111 and the second solder resist layer 113 and the steps of attaching the adhesive layer 193 to the back surface of the second chip 130 and the heat dissipation layer 191 are added, or the second chip 130 may be selectively covered with the film 140, and the film 140 is not disposed in the region corresponding to the second chip 130, which is not particularly limited herein, and the above processes may be added or combined according to actual situations.
In this embodiment, the content of the other parts not mentioned is similar to that described in the first embodiment, and is not repeated here.
In summary, the chip package structure 100 and the package method provided in the embodiments of the present invention have the following advantages:
in the chip package structure 100 provided by the embodiment of the invention, the supporting columns 160 are arranged at the periphery of the second chip 130, and the supporting columns 160 support the coating 140 around the second chip 130, so as to support the coating 140, increase the distance between the coating 140 and the substrate 110, and increase the surface tension of the coating 140, so that the molding flow of the molding compound 150 breaks through the coating 140 at the outer side of the second chip 130 and fills the coating 140 between the second chip 130 and the substrate 110, so that the molding compound 150 at the bottom of the second chip 130 is filled more completely, and the package reliability of the second chip 130 is improved. Meanwhile, the coating film 140 is disposed on the back surface of the first chip 120, so as to form a closed cavity 121 between the first chip 120 and the substrate 110, thereby ensuring that the functional area of the first chip 120 is not polluted, improving the quality of reception, and having good packaging quality and high reliability. In addition, the mounting position of the second chip 130 is raised, so that the distance between the top surface and/or the bottom surface of the second chip 130 and the substrate 110 is increased, the glue layer 193 and the heat dissipation layer 191 are added to increase the distance between the top surface of the second chip 130 and the substrate 110, and the notch 141 is formed in the coating film 140 in the area corresponding to the second chip 130 to ensure that the molding compound 150 mold flow breaks through the coating film 140 in the area corresponding to the second chip 130. And a cutting channel 195 is arranged among the plurality of component combinations arranged at intervals, and one or more supporting columns 160 are arranged on the cutting channel 195, so that a structure of a closed cavity 121 can be formed at the bottom of the first chip 120, a structure of a non-cavity can be formed at the bottom of the second chip 130, and the supporting columns 160 can be removed in a subsequent cutting process.
The packaging method provided by the embodiment of the invention can ensure that the closed cavity 121 at the bottom of the first chip 120 is not polluted, and can also ensure that the plastic package body 150 between the second chip 130 and the substrate 110 is completely filled, thereby improving the packaging quality and further improving the signal receiving quality and the product reliability of the product. The packaging method is simple, the operability is strong, and the packaging efficiency is high.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (19)
1. A chip packaging structure is characterized by comprising a substrate, a first chip, a second chip, a covering film and a plastic package body, wherein the first chip and the second chip are arranged on the substrate at intervals; supporting columns are arranged on the periphery of the chip and connected with the substrate, the film covering covers are arranged on the first chip, the second chip and the supporting columns, and the plastic package body is arranged on one side, far away from the first chip, of the film covering body, so that a closed cavity is formed between the first chip and the substrate; the support columns support the covering films, and the support columns are used for increasing the distance between the covering films and the base plate, so that the plastic package body breaks through the covering films on the outer sides of the second chips and is filled between the second chips and the base plate.
2. The chip package structure according to claim 1, wherein a region of the cover film corresponding to the second chip is provided with a notch.
3. The chip package structure according to claim 2, wherein the size of the cut is at least two times larger than the particle size of the molding compound.
4. The chip packaging structure according to claim 2, wherein a first solder mask is disposed on the substrate at a position corresponding to the second chip, a first pad is disposed on the first solder mask, the first pad is electrically connected to the substrate, and the second chip is electrically connected to the first pad, so that a distance between a side surface of the second chip away from the substrate and the substrate is greater than a distance between a side surface of the first chip away from the substrate and the substrate.
5. The chip packaging structure according to claim 4, wherein a second solder mask is disposed on the substrate at a position corresponding to the first chip, a surface of the second solder mask corresponding to the first chip is flush with a surface of the first solder mask corresponding to the second chip, and the first solder mask and the second solder mask are disposed in series.
6. The chip packaging structure according to claim 5, wherein a groove is provided on the first solder resist layer and/or the second solder resist layer to expose the substrate.
7. The chip packaging structure according to claim 5, wherein the first solder resist layer is provided with a groove, and the position of the groove is opposite to the position of the cut on the cover film.
8. The chip package structure according to claim 1, wherein a first supporting member is disposed on the substrate, the first supporting member is disposed on a periphery of the first chip, the cover film is disposed on the first supporting member, and a groove is disposed at an end of the first supporting member away from the substrate.
9. The chip package structure according to claim 8, wherein the first supporting member is zigzag.
10. The chip package structure according to claim 8, wherein a second pad is disposed on the substrate, the first chip is electrically connected to the second pad, and a second supporting member is disposed between the first chip and the substrate, the second supporting member being disposed at a periphery of the second pad.
11. The chip package structure according to claim 1, wherein a distance between a side of the second chip close to the substrate and the substrate is greater than a distance between a surface of the first chip close to the substrate and the substrate.
12. The chip package structure according to claim 1, wherein a heat dissipation layer is disposed on a side of the second chip away from the substrate, and the cover film is disposed on the heat dissipation layer.
13. The chip package structure according to claim 12, wherein a side of the second chip away from the substrate is provided with an adhesive layer, and the heat dissipation layer is disposed on a side of the adhesive layer away from the second chip.
14. The chip package structure according to claim 1, wherein the cover film is not disposed on a side of the second chip away from the substrate.
15. The chip package structure according to any one of claims 1 to 14, wherein the first chip, the second chip and the supporting pillars are configured as a combination of components, a plurality of the combination of components are disposed on the substrate at intervals, a cutting channel is disposed between two adjacent combination of components, a supporting pillar is disposed on the cutting channel, and the covering film is laid on the supporting pillar.
16. The chip package structure according to claim 15, wherein the scribe line has a width greater than a width of the support pillar.
17. A packaging method for making a chip package structure according to any one of claims 1 to 16, the method comprising:
providing a substrate;
arranging a support column on the substrate;
mounting a first chip and a second chip on the substrate; the supporting columns are arranged on the periphery of the second chip;
laying a covering film on the substrate, wherein the covering film covers the first chip, the supporting column and the second chip;
arranging a plastic package body outside the covering film, wherein the covering film is used for blocking the plastic package body at the outer side of the first chip so as to form a closed cavity between the first chip and the substrate; the support columns support the covering films, and the support columns are used for increasing the distance between the covering films and the base plates in the corresponding areas of the second chip, so that the plastic package body is used for breaking the covering films on the outer sides of the second chip to fill the space between the second chip and the base plates.
18. The method of claim 17, wherein the step of providing a substrate comprises:
providing a substrate, wherein a second bonding pad is arranged on the substrate and is used for being connected with the first chip;
coating a green paint layer on the substrate to form a first solder mask layer at a corresponding position for mounting the second chip and a second solder mask layer at a corresponding position for mounting the first chip; a first welding pad is arranged on the first solder mask layer and is electrically connected with the substrate, and the first welding pad is used for being electrically connected with the second chip, so that the plane where the first welding pad is located is higher than the plane where the second welding pad is located, and/or the distance between the surface of one side, away from the substrate, of the second chip and the substrate is larger than the distance between the surface of one side, away from the substrate, of the first chip and the substrate;
the step of providing support posts on the substrate includes:
the base plate is provided with a support column and a first support piece, and the first support piece is provided with a groove.
19. The packaging method according to claim 17, wherein the step of laying a cover film on the substrate further comprises:
and forming a cut on the covering film, wherein the cut is positioned in a corresponding area of the second chip, and the size of the cut is at least two times larger than the particle size of the plastic package body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202210280601.7A CN114530445A (en) | 2022-03-21 | 2022-03-21 | Chip packaging structure and packaging method |
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| CN202210280601.7A CN114530445A (en) | 2022-03-21 | 2022-03-21 | Chip packaging structure and packaging method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115312477A (en) * | 2022-07-06 | 2022-11-08 | 锐石创芯(重庆)科技有限公司 | Chip packaging structure and chip module |
| CN115377015A (en) * | 2022-08-29 | 2022-11-22 | 北京超材信息科技有限公司 | Packaging structure of electronic device and manufacturing method |
| CN117792321A (en) * | 2024-02-26 | 2024-03-29 | 甬矽电子(宁波)股份有限公司 | Chip packaging technology and chip packaging structure |
| CN117792321B (en) * | 2024-02-26 | 2024-07-05 | 甬矽电子(宁波)股份有限公司 | Chip packaging technology and chip packaging structure |
-
2022
- 2022-03-21 CN CN202210280601.7A patent/CN114530445A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115312477A (en) * | 2022-07-06 | 2022-11-08 | 锐石创芯(重庆)科技有限公司 | Chip packaging structure and chip module |
| CN115377015A (en) * | 2022-08-29 | 2022-11-22 | 北京超材信息科技有限公司 | Packaging structure of electronic device and manufacturing method |
| CN117792321A (en) * | 2024-02-26 | 2024-03-29 | 甬矽电子(宁波)股份有限公司 | Chip packaging technology and chip packaging structure |
| CN117792321B (en) * | 2024-02-26 | 2024-07-05 | 甬矽电子(宁波)股份有限公司 | Chip packaging technology and chip packaging structure |
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