CN221282097U

CN221282097U - Multi-chip packaging structure and radio frequency front end module

Info

Publication number: CN221282097U
Application number: CN202322658137.3U
Authority: CN
Inventors: 黄浈; 史海涛; 倪建兴; 陈建; 徐杰; 周佳炜
Original assignee: Ruishi Chuangxin Chongqing Technology Co ltd
Current assignee: Ruishi Chuangxin Chongqing Technology Co ltd
Filing date: 2023-09-28
Publication date: 2024-07-05
Anticipated expiration: 2033-09-28

Abstract

The application relates to the technical field of chip scale packaging, in particular to a multi-chip packaging structure and a radio frequency front end module. The multi-chip package structure specifically comprises: a first surface of the substrate is provided with a first bonding pad and a second bonding pad; the filter chip is flip-chip mounted on the first surface and connected with the first bonding pad; a non-filter chip arranged on the first surface and connected with the second bonding pad through bonding wires; the first adhesive part is arranged on the first surface at least around the filter chip, and a cavity is formed among the filter chip, the first adhesive part and the substrate; and the filler is filled on the first surface and covers the filter chip, the non-filter chip and the adhesive part. According to the application, the filter chip and the non-filter chip with bonding wires can be arranged on the same side of the substrate, and the requirement of the cavity of the filter chip is met by arranging the glue part, so that the package miniaturization is realized, and meanwhile, the reliability requirement of the package is met.

Description

Multi-chip packaging structure and radio frequency front end module

Technical Field

The present application relates to the field of chip scale packaging technologies, and in particular, to a multi-chip package structure and a radio frequency front end module.

Background

In the chip scale package, a multi-chip is mounted on the surface of a package substrate, and the chip is filled with a thermosetting resin or other material in a plastic package manner so as to protect the chip from being corroded by moisture. Some special function chips require a cavity structure between the chip and the substrate during packaging to meet the function, performance or other special requirements, such as a surface acoustic wave (Surface Acoustic Wave, SAW) filter chip, a bulk acoustic wave (Bulk Acoustic Wave, BAW) filter chip, and the like.

In order to form a closed cavity, the chip element is prevented from being influenced by external environment, and a protective film is covered on the surface of the chip to form the closed cavity between the chip and the substrate, and then plastic packaging materials are filled. However, in practice, it is found that a part of chips are not suitable for the packaging mode, and therefore, the packaging process of the film coating cannot meet the packaging requirement in the multi-chip scenario.

Disclosure of utility model

The embodiment of the application provides a multi-chip packaging structure and a radio frequency front end module, which can reduce the packaging size and meet the packaging requirement under a multi-chip scene.

A first aspect of an embodiment of the present application provides a multi-chip package structure, including:

The substrate comprises a first surface, wherein the first surface is provided with a first bonding pad and a second bonding pad;

The filter chip is flip-chip mounted on the first surface and connected with the first bonding pad;

The non-filter chip comprises a bonding wire, the non-filter chip is arranged on the first surface, and the bonding wire is connected to the second bonding pad;

The adhesive part comprises a first adhesive part, the first adhesive part is arranged on the first surface at least around the filter chip, and a cavity is formed among the filter chip, the first adhesive part and the substrate;

And the filler is filled on the first surface and covers the filter chip, the non-filter chip and the adhesive part.

Optionally, a spacing between the filter chip and the non-filter chip is less than a first threshold.

Optionally, the first threshold is 100 μm or 50 μm.

Optionally, the thickness of the portion of the first adhesive portion near the side surface of the filter chip is greater than the minimum distance from the lower surface of the filter chip to the first surface.

Optionally, the substrate includes a solder mask layer, the solder mask layer has at least a first opening and a second opening, the first bonding pad and the second bonding pad are respectively located in the first opening and the second opening, and a first adhesive portion disposed around the filter chip is at least partially located on the solder mask layer.

Optionally, the thickness of the solder mask layer is greater than the thickness of the first bonding pad or the second bonding pad exposed out of the first surface.

Optionally, the adhesive part further includes a second adhesive part, the non-filter chip further includes a first solder joint and a second solder joint, and the second adhesive part covers at least one of the first solder joint and the second solder joint;

The first welding point is a welding point for connecting the bonding lead and the upper surface of the non-filter chip, and the second welding point is a welding point for connecting the bonding lead and the second welding point.

Optionally, the second glue portion also covers at least one of at least part of a side surface of the non-filter chip and an upper surface of the non-filter chip.

Optionally, the thickness difference between any two positions of the glue portion is smaller than a second threshold.

Optionally, the second threshold is 25 μm, 20 μm or 15 μm.

Optionally, a gap is formed between at least a portion of the first adhesive portion adjacent to the filter chip and a side surface of the filter chip; or at least part of the first adhesive part close to the filter chip is attached to the side surface of the filter chip.

Optionally, the first glue portion covers at least part of the upper surface of the filter chip.

Optionally, the multi-chip package structure further includes a first chip, the substrate includes a second surface opposite to the first surface, and the first chip is disposed on the first surface and/or the second surface.

Optionally, the first chip is a filter chip, a non-filter chip or a passive element.

A second aspect of the embodiment of the present application provides a multi-chip package structure, which is characterized by including:

The non-filter chip comprises a bonding wire, the non-filter chip is arranged on the first surface and connected with the second bonding pad, and a first distance is reserved between the non-filter chip and the filter chip;

The first chip is arranged on the first surface, a second distance is arranged between the first chip and the filter chip or the non-filter chip, and the first distance is smaller than the second distance;

And the filler is filled on the first surface and covers the filter chip, the non-filter chip, the first chip and the adhesive part.

A third aspect of an embodiment of the present application provides a multi-chip package structure, including:

The substrate comprises a first surface, wherein the first surface is provided with a solder mask layer, a first bonding pad and a second bonding pad, the solder mask layer is at least provided with a first opening and a second opening, and the first bonding pad and the second bonding pad are respectively positioned in the first opening and the second opening;

The filter chip is inversely installed in the first opening and connected with the first bonding pad;

A non-filter chip including a bonding wire, the non-filter chip being disposed in the second opening and the bonding wire being connected to the second bonding pad;

The glue material part comprises a third glue material part which is arranged on the first surface so as to cover the solder mask layer, the filter chip and the non-filter chip, and a cavity is formed among the filter chip, the third glue material part and the substrate;

And the filling material is filled on the first surface and covers the glue material part.

Optionally, the non-filter chip further includes a first solder joint and a second solder joint, the glue portion further includes a fourth glue portion, and the fourth glue portion is disposed on a surface of the third glue portion facing away from the substrate through a dispensing process, so as to cover at least one of the first solder joint and the second solder joint;

An embodiment of the present application provides a radio frequency front end module, including the multi-chip package structure provided in any one of the above aspects.

According to the multi-chip packaging structure provided by the application, the filter chip and the non-filter chip with the bonding lead can be arranged on the same side of the substrate, and the requirement of the cavity of the filter chip is met by arranging the glue part, so that the packaging miniaturization is realized, and meanwhile, the reliability requirement of packaging is met.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a multi-chip package structure according to at least one embodiment of the present disclosure;

FIG. 2 is a schematic diagram II of a multi-filter package structure according to at least one embodiment of the present disclosure;

FIG. 3 is a schematic diagram III of a multi-filter package structure according to at least one embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a multi-filter package structure according to at least one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a multi-filter package structure according to at least one embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a multi-filter package structure according to at least one embodiment of the present disclosure;

Fig. 7 is a schematic diagram of a multi-filter package structure according to at least one embodiment of the application.

Reference numerals:

10. A substrate; 11. a first surface; 12. a second surface; 13. routing; 14. a first bonding pad; 15. a second bonding pad; 16. a solder mask layer;

20. A filter chip; 21. an upper surface of the filter chip; 22. a lower surface of the filter chip; 23. connection bumps of the first filter chip; 24. chip elements of the filter chip; 25. a cavity of the filter chip;

30. A non-filter chip; 31. an upper surface of the non-filter chip; 32. an adhesive layer; 33. bonding wires;

41. A glue material part; 41. a first adhesive part; 42. a second adhesive part; 43. a third adhesive part; 44. a fourth adhesive portion;

50. A filler;

60. A first chip.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for the same elements throughout for clarity.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to," "connected to" … another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Spatially relative terms, such as "under …," "under …," "below," "under …," "over …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In the following description, for the purpose of providing a thorough understanding of the present application, detailed structures and steps are presented in order to illustrate the technical solution presented by the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other embodiments in addition to these detailed descriptions.

In the chip-scale packaging technology, in order to meet the requirement of a filter chip on a cavity, a protective film is generally covered on the outer surface of the chip, in the process, the protective film is generally laid on the upper surface of the chip, then pressure facing to a substrate is applied to the protective film, so that the protective film is attached to the upper surface, the side surface and the substrate of the chip, and a sealed cavity is formed among the chip, the protective film and the substrate, so that the functional requirement of the chip is met, and finally, the chip is subjected to plastic packaging by adopting filling materials such as sealing resin. In the film coating process, a protective film is laid on the surface of the structure to be packaged and pressure is applied towards the substrate, so that in a multi-chip scene, if a film coating mode is adopted to package the filter chip, the film coating process can affect the chip with a special structure, for example, the bonding wires in the wire bonding structure chip can be broken, and in order to avoid the situation, the filter chip and the wire bonding structure chip are generally arranged on different sides of the substrate in the related art, but the package size is increased, and the miniaturization requirement is not met.

In order to solve the above-mentioned problems, the present application provides a multi-chip package structure, which specifically includes: the substrate comprises a first surface, wherein the first surface is provided with a first bonding pad and a second bonding pad; the filter chip is flip-chip mounted on the first surface and connected with the first bonding pad; the non-filter chip comprises a bonding wire, the non-filter chip is arranged on the first surface, and the bonding wire is connected with the second bonding pad; the first glue material part is arranged on the first surface at least around the filter chip, and a cavity is formed among the filter chip, the first glue material part and the substrate; and the filler is filled on the first surface and covers the filter chip, the non-filter chip and the first adhesive part. That is, the filter chip and the non-filter chip (wire bonding structure chip) with bonding wires can be arranged on the same side of the substrate, and the requirement of the cavity of the filter chip is met by arranging the adhesive, so that the package miniaturization is realized, and meanwhile, the reliability requirement of the package is met. The application will be illustrated in detail by the following examples:

The filter chip in the embodiment of the application refers to a chip with a filtering function, and may be a surface acoustic wave filter chip or a bulk acoustic wave filter chip; the non-filter chip is other chips than the chip with the filtering function, and may be a power amplifier chip, a low noise amplifier chip, a switch, a coupler, a matching circuit, etc., and the implementation of the present application is not limited.

In an embodiment, referring to fig. 1, fig. 1 is a schematic diagram of a multi-chip package structure according to at least one embodiment of the application. In the multi-chip structure shown in fig. 1, the multi-chip structure includes a substrate 10, a filter chip 20, a non-filter chip 30, a glue portion 40, and a filler 50, wherein the glue portion 40 includes a first glue portion 41 disposed around at least the periphery of the filter chip 20, and the filler 50 is filled in the substrate 10 and covers the filter chip 20, the non-filter chip 30, and the first glue portion 41.

The substrate 10 may be a resin, ceramic, quartz, or the like, or the substrate 10 may be a single-layer substrate or a multi-layer substrate, which is not limited by the present application, and in this embodiment, the substrate 10 is a multi-layer substrate. The material of the filler 50 may be an insulating material such as a sealing resin, or may be another insulating material having a low fluidity such as a sealing resin containing particles. Specifically, the material of the filler 50 may be a thermosetting resin, or a thermosetting resin containing particulate matter. The particulate matter may be silica (SiO 2) particles or alumina (Al 2O 3) particles, and the present application is not limited thereto. Alternatively, the filler 50 may be an insulating resin material or other conventional molding materials. It should be understood that other materials for the packing material 50 may be used to perform the sealing function, and the present application will not be described herein. The filler 50 may be provided to provide physical support protection and also to block moisture, salt, mist, etc. from the external environment, thereby protecting the packaged chip. The glue portion 40 may be a fast curing glue, in one embodiment, the glue portion 40 may be an ultraviolet curing glue, in other embodiments, the glue portion 40 may be a glue having a lower fluidity than the filler, and the application is not limited herein.

Specifically, the substrate 10 includes a first surface 11, a second surface 12, a plurality of traces 13, a first pad 14 and a second pad 15, where the first surface 11 and the second surface 12 are disposed opposite to each other; the first pads 14 and the second pads 15 are provided on the first surface 11. In one manner, the first bonding pad 14 and the second bonding pad 15 may be embedded in the substrate 10, and the upper surfaces of the first bonding pad 14 and the second bonding pad 15 may be flush with the first surface 11 or slightly higher than the first surface 11, which is not limited by the present application; the traces 13 may be disposed on the first surface 11, the second surface 12, and in the substrate 10, for connection of an internal circuit and connection of the multi-chip module with an external circuit, and the first pads 14 and the second pads 15 and the traces 13 may be metals or alloys doped with various metals, specifically, nickel, palladium, molybdenum, tungsten, ruthenium, gold, magnesium, aluminum, copper, chromium, titanium, osmium, iridium, and the like.

In the embodiment shown in fig. 1, the heights of the first pads 14 and the second pads 15 disposed on the first surface 11 and the traces 13 are substantially the same, and may be made in the same process.

Specifically, the filter chip 20 includes a connection bump 23 and a chip element 24, which is flip-chip disposed on the first surface 11, and specifically is connected to the first pad 14 through the connection bump 23, where the connection bump 23 may be tin, gold, copper, or the like, and the application is not limited thereto. The flip-chip arranged filter chip 20 has an upper surface 21 and a lower surface 22 opposite to the upper surface 21, wherein the lower surface 22 is closer to the substrate 10 than the upper surface 21. The connection bumps 23, the chip elements 24, and the like of the filter chip 20 are provided on the lower surface 22, specifically, the connection bumps 23, the chip elements 24, and the like are generally provided in the middle region of the lower surface 22, and the edge of the lower surface 22 is a region around the peripheral side of the middle region, generally not provided with elements related to the filter operation performance.

Specifically, the non-filter chip 30 includes an upper surface 31 facing away from the substrate 10 and a lower surface that is adhered to the first surface 11 by an adhesive layer 32. The non-filter chip 30 includes bonding wires 33, one ends of the bonding wires 33 are connected to the upper surface 31 of the non-filter chip 30, and the other ends are connected to the second pads 15, thereby achieving electrical connection with the traces 13 of the substrate 10, and electrical connection with the filter chip 20 and external circuits is achieved through the traces 13.

Further, the non-filter chip 30 further includes a first solder joint and a second solder joint, wherein the first solder joint is a solder joint where the bonding wire 33 is connected to the upper surface 31 of the non-filter chip 30, and the second solder joint is a solder joint where the bonding wire 33 is connected to the second solder pad 15. The bonding wires 33 are connected to pads on the upper surface 31 of the non-filter chip 30 by first pads and to the second pads 15 by second pads, which are not shown in the drawings of the present application.

Illustratively, in the embodiment shown in fig. 1, the glue portion 40 includes a first glue portion 41 disposed on the first surface 11 around the periphery of the filter chip 20, a portion of the first glue portion 41 being disposed below the filter chip 20 opposite to the edge region of the lower surface 22, and another portion being disposed outside the filter chip 20 such that a cavity 25 of the filter chip 20 is enclosed between the lower surface 22 of the filter chip 20, the first surface 11 of the substrate 10, and the first glue portion 41.

In one embodiment, a portion of the first adhesive portion 41 located below the filter chip 20 may abut against the lower surface 22 of the filter chip 20, and may have a certain gap.

In another embodiment, the thickness of the portion of the first adhesive portion 41 located outside the filter chip 20 may be slightly lower than the height of the space between the lower surface 22 and the first surface 11 of the filter chip 20, or may be higher than the height of the space. In the case where the thickness of the portion of the first adhesive portion 41 located outside the filter chip 20 is higher than the height of the pitch, the portion may abut against the side surface of the filter chip 20 or may have a certain gap, and the present application is not particularly limited.

In the embodiment of the present application, the shape of the first adhesive part 41 is not limited. Illustratively, the surface of the first adhesive portion 41 facing away from the substrate 10 may have a plurality of peaks or top surfaces, and a "concave" shape may be formed between adjacent peaks and the peaks or top surfaces, or may be a substantially flat surface.

It is to be understood that the first adhesive portion 41 may be partially in contact with the first pad 14 to protect the first pad 14, or may be spaced apart, which is not particularly limited by the present application.

According to the embodiment of the application, the filter chip 20 and the non-filter chip 30 of the wire bonding structure can be packaged on the same side of the substrate, so that the connecting line between the filter chip and the non-filter chip is shortened, the negative influence on the working performance caused by overlong connecting line is reduced, the requirement on the working performance is met, the packaging size is reduced, and the packaging cost is saved. Further, by the arrangement of the first adhesive portion 41, the requirement of the filter chip 20 for a closed cavity is achieved, thereby improving the packaging reliability.

In some embodiments, the spacing between the filter chips 20 and the non-filter chips 30 is less than a first threshold.

It is to be understood that the spacing between the filter chip 20 and the non-filter chip 30 may be the minimum spacing between the two chips in the arrangement direction of the two chips, or may be the average spacing or the maximum spacing, which is not limited in the present application.

It will be appreciated that the filter chips 20 and the non-filter chips 30 may be arranged in a line along a particular direction, with the two chips substantially overlapping in that direction; the chips can also be staggered along the direction, and the two chips are partially overlapped along the direction; the chips may be arranged diagonally, and the two chips are hardly overlapped in the direction, which is not particularly limited in the present application.

In this embodiment, when the first adhesive portion 41 is disposed around the filter chip 20, the distance between the two chips may be set smaller than the first threshold, and compared with the filter chip 20 and the non-filter chip of the non-wire bonding structure, the distance between the two chips may be further reduced, thereby greatly reducing the package size and saving the package cost.

In some embodiments, the first threshold is 150 μm, 100 μm, or 50 μm. In particular, the spacing between the filter chip 20 and the non-filter chip 30 may be less than 150 μm, or less than 100 μm, or less than 80 μm, or less than 50 μm.

For example, the spacing between the filter chip 20 and the non-filter chip 30 may be 30 μm, 40 μm, 50 μm, 75 μm, 80 μm, 90 μm, 99 μm, 130 μm, etc., and the present application is not limited thereto.

In the present embodiment, the first adhesive portion 41 is provided around the filter chip 20, so that the distance between the filter chip 20 and the non-filter chip 30 can be reduced to 150 μm or less than 100 μm, even to 50 μm or less, and the distance between the two chips can be greatly reduced while ensuring the package reliability.

In some embodiments, the thickness of the portion of the first adhesive portion 41 near the side of the filter chip 20 is greater than the minimum distance from the lower surface 22 of the filter chip 20 to the first surface 11.

Specifically, with continued reference to fig. 1, a portion of the first adhesive portion 41 adjacent to the side surface of the filter chip 20 may be understood as a portion of the first adhesive portion located outside the filter chip 20 facing the side surface of the filter chip 20 in a top view direction (a direction from the filter chip 20 to the substrate 10). The minimum distance from the lower surface 22 of the filter chip 20 to the first surface 11 can be understood as the distance from the lower surface 22 to the first surface 11 in the top view.

In this embodiment, by defining the thickness of the portion of the first adhesive portion 41 near the side surface of the filter chip 20, a certain stress buffering effect can be achieved on the side surface of the filter chip 20, and the cavity of the filter chip 20 is also formed, so that the filler 50 is effectively prevented from entering the cavity 25 of the filter chip 20 through the gap between the lower surface 22 and the first surface 11 of the filter chip 20, and packaging reliability is improved.

In some embodiments, a gap is provided between at least a portion of the first adhesive portion 41 adjacent to the filter chip 20 and a side surface of the filter chip 20; or at least a portion of the first adhesive portion 41 adjacent to the filter chip 20 is attached to the side surface of the filter chip 20. In this way, external stresses to which the sides of the filter chip 20 are subjected can be buffered.

Specifically, the first adhesive portion 41 near the filter chip 20 may have a gap between a portion and a side surface of the filter chip 20, and a portion is attached to the side surface of the filter chip 20; or a gap is formed between the first glue part 41 close to the filter chip 20 and the side surface of the filter chip 20; or the first adhesive portions 41 near the filter chip 20 are adhered to the side surfaces of the filter chip 20, and the present application is not limited thereto.

In a specific embodiment, the gap between the first adhesive part 41 disposed on the solder resist layer 16 and the side of the filter chip 20 at a position close to the side of the filter chip 20 is not more than 15 μm, 10 μm or 5 μm to prevent the filler 50 from entering the cavity 25 of the filter chip 20 from the gap between the first adhesive part 41 and the filter chip 20 and the gap between the solder resist layer 16 and the filter chip 20. That is, the first adhesive portion 41 does not cover the side surface of the filter chip 20.

In a specific embodiment, the first adhesive portion 41 disposed on the solder resist layer 16 is disposed in a position close to the side surface of the filter chip 20 and attached to the side surface of the filter chip 20, so that a small portion of the side surface of the filter chip 20 close to the solder resist layer 16 is covered by the first adhesive portion 41, which can buffer stress of the side surface of the filter chip 20 to some extent. That is, most of the side surface (i.e., the upper half) of the filter chip 20 is not covered by the first adhesive portion 41.

In some embodiments, the first glue portion 41 may also be located on the upper surface 21 of the filter chip 20 to at least partially cover the upper surface 21 of the filter chip 20. Specifically, the first adhesive portion 41 located on the upper surface 21 of the filter chip 20 may cover only the edge area of the upper surface 21, may cover only the middle area of the upper surface 21, may be intermittently disposed on the upper surface 21, and may also cover the upper surface 21 completely to buffer the stress borne by the upper surface 21 of the filter chip 20.

In some embodiments, the first glue portion 41 may be formed by a dispensing process. In a specific embodiment, the first adhesive portion 41 surrounding the periphery of the filter chip 20 as shown in fig. 1 may be formed by multiple dispensing-curing. For example, after the first layer of the adhesive is printed, the first layer of the adhesive is cured by ultraviolet irradiation, and then the second layer of the adhesive is printed and cured, and the first adhesive portion 41 shown in fig. 1 is finally formed by printing and curing a plurality of times.

In at least one embodiment, the substrate 10 includes a solder mask 16, the solder mask 16 has at least a first opening 161 and a second opening 162, the first bonding pad 14 is located in the first opening 161, the second bonding pad 15 is located in the second opening 162, and the first adhesive portion 41 disposed around the filter chip 20 is at least partially located on the solder mask 16.

Specifically, in the case of the solder resist layer 16, the solder resist layer 16 located at the edge of the first opening 161 is at least opposite to the edge of the lower surface 22 of the filter chip 20.

In one embodiment, referring to fig. 2, fig. 2 is a schematic diagram of a multi-chip package structure according to at least one embodiment of the application. The structure shown in fig. 2 is different from that of fig. 1 in that: the substrate 10 includes a solder mask 16, the solder mask 16 has at least a first opening 161 and a second opening 162, the first bonding pad 14 is located in the first opening 161, the second bonding pad 15 is located in the second opening 162, and the first adhesive portion 41 disposed around the filter chip 20 is located on the solder mask 16. In the embodiment shown in fig. 1, the substrate 10 does not include the solder mask layer 16, and the first adhesive portion 41 disposed around the filter chip 20 is directly disposed on the first surface 11.

Specifically, the number of the first openings 161 may be plural or one. In the case where the number of the first openings 161 is plural, one or more first pads 14 are provided in each of the first openings 161, that is, a portion of the solder resist layer 16 (not shown) is present in the cavity formed by the filter chip 20; in the case where the number of first openings 161 is one, all the first pads 14 connected to the connection bumps 23 of the filter chip 20 are located within the first openings 161, as shown in fig. 2. Further, a portion of the trace 13 may be further disposed on the first surface 11 of the substrate 10 in the first opening 161, so as to meet the requirements of the filter chip 20 in terms of operation or performance.

Specifically, the number of the second openings 162 may be plural or one. In the case that the number of the second openings 162 is plural, one or more second pads 15 are disposed in each second opening 162, and the non-filter chip 30 may be located on the solder mask layer 16 or may be located in the second opening 162, as shown in fig. 2; in the case where the number of the second openings 162 is one, all the second pads 15 connected to the bonding wires 33 of the non-filter chip 30 and the non-filter chip 30 are located in the second openings 161 (not shown in the drawing).

In another embodiment, referring to fig. 3, fig. 3 is a schematic diagram of a multi-chip package structure according to at least one embodiment of the application. One of the differences between the structure shown in fig. 3 and that shown in fig. 2 is that: the first adhesive portion 41 disposed around the filter chip 20 is partially disposed on the solder resist layer 16, and partially disposed in the first opening 161.

In some embodiments, the thickness of the solder mask layer 16 is greater than the thickness of the first pad 14 or the second pad 15 exposed on the first surface 11.

It is understood that the first pads 14, the second pads 15 and the traces 13 may be manufactured in the same process, and the heights thereof are substantially the same, and the thickness of the first pads 14 or the second pads 15 exposed on the first surface 11 may be understood as the thickness of the traces 13 exposed on the first surface 11. If the three are fabricated in different processes or the three are different in height, the thickness of the solder mask layer 16 may be greater than the maximum thickness of the three exposed to the first surface 11.

In the structures shown in fig. 2 and 3, the first pads 14, the second pads 15 and the traces 13 are disposed on the first surface 11 of the substrate 10, and then the thickness of the first pads 14 or the second pads 15 exposed on the first surface 11 can be understood as the height of the first pads 14 or the second pads 15. In other embodiments, if the first pads 14 or the second pads 15 are all embedded in the substrate 10, and the upper surfaces of the first pads 14 or the second pads 15 are substantially flush with the first surface 11, the thickness of the first pads 14 or the second pads 15 exposed to the first surface 11 is almost negligible. In another embodiment, if the first pad 14 or the second pad 15 is partially embedded in the substrate 10, and the upper surface of the first pad 14 or the second pad 15 is slightly higher than the first surface 11, the thickness of the first pad 14 or the second pad 15 exposed to the first surface 11 may be understood as the minimum distance from the upper surface of the first pad 14 or the second pad 15 to the first surface 11.

In the present embodiment, the thickness of the solder mask 16 is greater than or slightly greater than the thickness of the first pad 14 or the second pad 15 exposed on the first surface 11, so as to protect the wires and the pads in the opening, and the arrangement of the solder mask 16 can reduce the distance between the filter chip 20 and the substrate 10, and in combination with the arrangement of the first adhesive portion 41, the filler 50 is more beneficial to blocking the filler 50 from entering the cavity 25 of the filter chip 20.

In some embodiments, where the substrate 10 includes the solder resist layer 16, the thickness of the portion of the first adhesive portion 41 adjacent to the side of the filter chip 20 is greater than the minimum distance from the lower surface 22 of the filter chip 20 to the first surface 11, and it is understood that the thickness of the portion of the first adhesive portion 41 adjacent to the side of the filter chip 20 is greater than the minimum distance from the lower surface 22 of the filter chip 20 to the solder resist layer 16.

In the structure shown in fig. 2 and 3, the first adhesive portion 41 surrounding the periphery of the filter chip 20 may be formed by a dispensing process.

In at least one embodiment, the glue portion 40 may further include a second glue portion 42, where the second glue portion 42 covers at least one of the first and second welding spots.

Illustratively, in one embodiment, the second glue portion 42 covers only the second weld spot; in another embodiment, the second glue portion 42 covers only the first welding spot; in yet another embodiment, referring to fig. 3, in fig. 3, the second adhesive portion 42 covers the first and second welding points.

In some embodiments, the second adhesive portion 42 may cover only the second solder joint, or may cover the second pad 15 simultaneously with the second solder joint, which is not limited by the present application.

In this embodiment, the second adhesive portion 42 may be formed at the first welding point and/or the second welding point through a dispensing process. At least one of the first welding spot and the second welding spot is covered, so that the welding spot of the non-filter chip can be protected, and the non-filter chip is prevented from being broken due to the falling of the welding spot.

In some embodiments, the second glue portion 42 also covers at least one of at least a portion of the side surfaces of the non-filter chip 30 and the upper surface of the non-filter chip 30.

In the present embodiment, the second adhesive portion 42 may cover the first solder joint on the upper surface 31 of the non-filter chip 30, and may cover other portions of the upper surface 31 of the non-filter chip 30, specifically, the entire upper surface 31, or a portion of the upper surface 31, specifically, an edge region and/or a middle region of the upper surface 31 of the non-filter chip 30, or may be provided intermittently or continuously. The second adhesive portion 42 covers at least part of the side surface of the non-filter chip 30, which is understood to cover only the side surface of the non-filter chip 30 near the second pads, or covers all the side surfaces of the non-filter chip 30. Specifically, only a portion of the side surface near the substrate may be covered, or the entire side surface may be covered, and the present application is not limited thereto.

In the present embodiment, the second dispensing portion 42 covers the side surface and/or the upper surface 31 of the non-filter chip 30, so that the external stress can be buffered to some extent, and the multi-non-filter chip 30 plays a role in protection.

In one embodiment, the second dispensing portion 42 may be formed by a dispensing process to cover at least one of at least a portion of the side surface of the non-filter chip 30 and the upper surface of the non-filter chip 30.

In at least one embodiment, referring to fig. 4, fig. 4 is a schematic diagram of a multi-chip package structure according to at least one embodiment of the present application. In fig. 4, the solder resist layer 16, the upper surface 21 of the filter chip 20, the second pad 15, and the upper surface 31 of the non-filter chip 30 are all covered by the adhesive portion 40 on the surfaces. The adhesive portion 40 on the solder resist layer 16 between the filter chip 20 and the non-filter chip 30 may be regarded as a first adhesive portion 41 or a second adhesive portion 42.

In some embodiments, the thickness difference of the glue portion 40 (including the first glue portion 41 and/or the second glue portion 42) at any two locations on the surface facing away from the substrate 10 is less than the second threshold.

Illustratively, the glue portions 40 (including the first glue portion 41 and/or the second glue portion 42) may be formed by a full spray process.

In some embodiments, the second threshold is 25 μm, 20 μm, or 15 μm.

In some embodiments, the fourth threshold is 10 μm or 5 μm.

In this embodiment, the difference in thickness between any two positions of the glue portion 40 is smaller than the second threshold, which can be understood as that the thickness of the glue portion 40 finally formed by, for example, a full spray process is substantially uniform. Specifically, the thickness difference between any two positions of the glue portion 40 is within the range, so that the thickness of the glue portion 40 is relatively uniform, and the packaging efficiency is improved.

It will be appreciated that the thickness theory of the glue portion formed by the full spray process is that a glue portion of uniform thickness is formed, but there is an error in the actual process, so that the thickness difference between the thickest and thinnest portions of the glue portion 40 is about 20 μm, and may be in the range of 25 μm, or in the range of 20 μm, or in the range of 15 μm.

Illustratively, since there are various structures on the surface of the substrate 10, the heights of the respective structures are different, and the spraying time or direction for each position is also different when the full spraying process is performed, the thickness of the adhesive part 40 finally formed on the surface of each structure is also different. Specifically, for example, the thickness of the paste formed on the solder resist layer 15 is substantially uniform and the thickness difference is small, and the thickness of the paste formed on the upper surfaces of the two chips (the filter chip 20 and/or the non-filter chip 30) is substantially uniform and the thickness difference is small, but the thickness of the paste portion 40 on the solder resist layer 16 may be large in a gap from the thickness of the paste portion 40 on the upper surfaces of the two chips (the filter chip 20 and/or the non-filter chip 30).

Illustratively, because the solder resist layer 16 is thicker in the vicinity of the two chips (the filter chip 20 and/or the non-filter chip 30) due to the package reliability, or because a thicker adhesive is required on the upper surface or the side of one of the two chips to cover due to the stress relief requirement, the spraying time may be prolonged or the spraying direction may be adjusted at the corresponding position when the full spraying process is performed, so that the thickness of the adhesive portion 40 formed at the position may be greater than that of the adhesive portion 40 formed at other positions, and thus there may be a thickness difference in the range of 15 μm, 20 μm, or even 25 μm even if the adhesive portion 40 is formed through the full spraying process.

Further, the thickness theory of the glue portion formed by the full spray process is that a glue portion having a uniform thickness is formed, but there is an error in the actual process, and thus, the thickness difference between any two positions of the glue portion 40 may be in the range of 10 μm or even in the range of 5 μm.

In some embodiments, the glue sections 40 (including the first glue section 41 and/or the second glue section 42) may be formed by a dispensing process, as shown in fig. 1-3.

In the present embodiment, the glue portion 40 is formed by the dispensing process, so that the glue can be precisely disposed at a desired position, the amount of glue used can be reduced, and the influence of volatile gas and the like of the glue on the packaged chip can be reduced to a certain extent by reducing the amount of glue used.

In the packaging scene of the filter chip 20 and the non-filter chip 30 with the wire bonding structure on the same side of the substrate 10, in one embodiment, the first glue material part 41 with relatively uniform thickness is formed in a full spraying process mode, so that the requirement of a closed cavity of the filter chip 20 can be met, the stress buffering is carried out on the upper surface of the filter chip 20, and the packaging efficiency can be improved; the second glue part is formed only at the required position through a glue dispensing process, so that the use of glue can be reduced, and the process cost is saved.

In another embodiment, the second glue portion 42 with a relatively uniform thickness is formed by a full spray process, so that the welding can be protected, the stress buffering can be performed on the upper surface of the non-filter chip 300, and the process efficiency can be improved; the first adhesive portion 41 is formed only at a desired position by the dispensing process, so that the requirement of sealing the cavity of the filter chip 20 can be satisfied.

In still another embodiment, the glue portion 40 (the first glue portion 41 and the second glue portion 42 may be regarded as a whole) with a relatively uniform thickness is formed by a full spray process, for example, fig. 4, so that the process flow can be reduced, the packaging efficiency can be greatly improved, the process cost can be reduced, and the stress borne by the filter chip 20 and the non-filter chip 30 can be buffered, so that the packaging reliability can be improved.

It will be appreciated that the thickness of the glue portion 40 formed by the full spray process is the minimum distance of the glue portion 40 from this location in the upper surface of the substrate 10 to near the lower surface of the substrate 10. The thickness is at least greater than the distance of the lower surface 22 of the filter chip 20 to the gap of the solder mask layer 16 to relieve stress at the gap and the sides of the filter chip near the gap and to block the filler material 50 at the gap.

In at least one embodiment, please refer to fig. 5 and fig. 6, fig. 5 is a schematic diagram of a multi-chip package structure provided by at least one embodiment of the present application, and fig. 6 is a schematic diagram of a multi-chip package structure provided by at least one embodiment of the present application. In the structure shown in fig. 5 and 6, the multi-chip package structure further includes a first chip 60, the substrate 10 includes a second surface 12 opposite to the first surface 11, and the first chip 60 is disposed on the first surface 11 and/or the second surface 12.

Specifically, the first chip 60 may be one or more. In the case where there are a plurality of first chips 60, they may be provided on the first surface 11, may be provided on the second surface 12, or may be provided on the first surface 11 in part and the second surface 12 in part. The plurality of first chips 60 may be flip-chip mounted on the substrate 10, or may be wire-bonded on the substrate 10, or may be partially flip-chip mounted, or partially wire-bonded, and the present application is not particularly limited.

Illustratively, fig. 5 shows only one first chip 60, the first chip 60 is flip-chip mounted on the second surface 12, and the filler 50 encapsulates the first chip 60 and fills the space between the first chip 60 and the second surface 12.

Illustratively, fig. 6 shows that only one first chip 60 is provided, the first chip 60 is flip-chip mounted on the first surface 11, specifically, on a side close to the filter chip 20, and the upper surfaces of the first chip 60, the filter chip 20, and the non-filter chip 30 are sprayed with the adhesive portion 40. In contrast, there is a large gap between the glue portion 40 and the first chip 60, from where the filler 50 can enter the space between the first chip 60 and the first surface 11.

In some embodiments, the first chip 60 may also be disposed on a side proximate to the non-filter chip 30.

In some embodiments, the spacing between the first chip and the adjacent chip may be greater than or less than a first threshold. Preferably, the distance between the first chip and the adjacent chip is smaller than the first threshold, so that the package size of the multi-chip package structure is further reduced by at least arranging the adhesive around the filter chip 20.

In some embodiments, the first chip 30 is a filter chip, a non-filter chip, or a passive element.

It is understood that in the case where the number of the first chips 30 is one, the first chips 30 may be filter chips, non-filter chips, or passive elements. In the case where the number of the first chips 30 is plural, each of the first chips 30 may be a filter chip, a non-filter chip, or a passive element, and the same type of chip may be present or different types of chips may be present in the plural first chips 30, which is not limited in the present application. The non-filter chip may be a low noise amplifier chip, a power amplifier chip, a switch, a coupler, a matching circuit, or the like. The passive element may be a capacitor or an inductor. Fig. 5 shows only the first chip 30 as a non-filter chip structure.

In at least one embodiment, a multi-chip package structure includes: a substrate 10, a filter chip 20, a non-filter chip 30, a first chip 60, a glue portion 40 (including a first glue portion 41), and a filler 50, wherein:

The substrate 10 comprises a first surface 11, the first surface 11 being provided with first pads 14 and second pads 15. The filter chip 20 is flip-chip mounted on the first surface 11 and connected to the first pads 14. The non-filter chip 30 includes bonding wires 33, the non-filter chip 30 is disposed on the first surface 11, and the bonding wires 33 are connected to the second pads 15, and a first distance D1 is provided between the non-filter chip 30 and the filter chip 20. The first chip 60 is disposed on the first surface 11, and a second distance D2 is provided between the first chip 60 and the filter chip 20 or the non-filter chip 30, and the first distance D1 is smaller than the second distance D2. The first adhesive portion 41 is disposed at least around the filter chip 20 on the first surface 11, and a cavity 25 is formed between the filter chip 20, the first adhesive portion 41 and the substrate 10. The filler 50 is filled in the first surface 11 and covers the filter chip 20, the non-filter chip 30, the first chip 60 and the adhesive portion 40.

With continued reference to fig. 6, in the structure shown in fig. 6, the first chip 60 is disposed on the first surface 11, and the description of the first chip 60 can refer to the related description of the above embodiment, which is not repeated herein.

It should be understood that the first distance D1 between the filter chip 20 and the non-filter chip 30 may be the minimum distance between the two chips, specifically, the minimum distance between the sides of the two chips, the minimum distance between the sides of the filter chip 20 and the bonding wires 33 of the non-filter chip 30, and the minimum distance between the second pads 15 connected to the bonding wires 33 as shown in fig. 6, which is not limited by the present application.

In this embodiment, under the multicore piece scene, can realize the demand of filter chip to airtight cavity through setting up gluey material portion, set up gluey material portion and can encapsulate filter chip and the non-filter chip of routing structure in the same side of base plate, shortened the connecting wire between filter chip and the non-filter chip, reduce the negative influence to working property because of connecting wire overlength produces, not only satisfied the demand in the aspect of the working property, can also reduce the encapsulation size, save encapsulation cost. Further, the glue parts are arranged around the filter chip, and the first distance between the filter chip and the non-filter chip of the wire bonding structure can be shortened, so that the first distance is smaller than the second distance between the first chip and the filter chip or the non-filter chip of the wire bonding structure, and compared with the filter chip 20 and the non-filter chip of the non-wire bonding structure, the packaging size can be further reduced, and the packaging cost is saved.

It should be noted that, other structures and corresponding effects of the present embodiment may refer to the related descriptions in the above embodiments, and the disclosure is not repeated herein.

In at least one embodiment, a multi-chip package structure includes: a substrate 10, a filter chip 20, a non-filter chip 30, a glue portion 40 (including a third glue portion 43), and a filler 50, wherein:

The substrate 10 comprises a first surface 11, the first surface 11 being provided with a solder mask 16, a first pad 14 and a second pad 15, the solder mask 16 having at least a first opening and a second opening, the first pad 14 and the second pad 15 being located in the first opening and the second opening, respectively.

The filter chip 20 is flip-chip mounted in the first opening and connected to the first pad 14. The non-filter chip 30 includes bonding wires 33, the non-filter chip 20 is disposed in the second opening, and the bonding wires 33 are connected to the second pads 15.

The adhesive part 40 includes a third adhesive part 43, and the third adhesive part 43 is disposed on the first surface 11 to cover the solder mask layer 16, the filter chip 20, and the non-filter chip 30, and a cavity is formed between the filter chip 20, the third adhesive part 43, and the substrate 10. The filler 50 is filled in the first surface 11 and covers the adhesive portion 40.

In the embodiment, the third adhesive portion 43 may be formed on the solder mask layer 16, the upper surface 21 of the filter chip 20, and the upper surface 31 of the non-filter chip 30 by a full spray process or a dispensing process, etc., and the description and effects thereof will be referred to the description of the above embodiments, and the disclosure is not repeated.

In some embodiments, the thickness of the third glue portion 43 is relatively uniform, with a thickness difference in any two locations in the range of 25 μm, or in the range of 20 μm, or in the range of 15 μm.

In some embodiments, the thickness of the third glue portion 43 is relatively uniform, and the difference in thickness between any two locations thereof is in the range of 10 μm, or in the range of 5 μm. The related description may refer to the corresponding content of the above embodiments, and the embodiments of the present application are not described herein again.

In some embodiments, the non-filter chip 30 further includes a first solder joint and a second solder joint, the glue portion 40 further includes a fourth glue portion 44, and the fourth glue portion 44 is disposed on a surface of the third glue portion 43 facing away from the substrate 10 by a dispensing process, so as to cover at least one of the first solder joint and the second solder joint; the first solder joint is a solder joint where the bonding wire 33 is connected to the upper surface 31 of the non-filter chip 30, and the second solder joint is a solder joint where the bonding wire 33 is connected to the second solder joint 15.

In the embodiment of the application, on the basis of the third adhesive part 43, the fourth adhesive part 44 is additionally arranged on at least one of the first welding spot and the second welding spot through the dispensing process, so that the first welding spot and the second welding spot can be better protected, each welding spot of the non-filter chip 30 can be effectively prevented from falling off, and the reliability of the multi-chip packaging structure is further improved.

In at least one embodiment, after the fourth adhesive portion 44 is disposed on at least one of the first solder joint and the second solder joint, the third adhesive portion 43 may be disposed to cover the fourth adhesive portion 44, the solder mask layer 16, the filter chip 20 and the non-filter chip 30.

In an embodiment, a radio frequency front end module is provided, and the package structure of the radio frequency front end module includes the multi-chip package structure provided by the application, for example, the multi-chip package structure provided by the above embodiment. In addition, the rf front-end module further includes devices such as an antenna, an amplifier, an inductor, and a capacitor, which are not limited in this embodiment.

The radio frequency front end module provided by the application comprises the multi-chip packaging structure, so that the overall packaging size of the module can be reduced to a certain extent, and the packaging reliability of the module is improved.

The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. A multi-chip package structure, comprising:

2. The multi-chip package structure of claim 1, wherein a spacing between the filter chip and the non-filter chip is less than a first threshold.

3. The multi-chip package structure of claim 2, wherein the first threshold is 100 μιη or 50 μιη.

4. The multi-chip package structure of claim 1, wherein a thickness of a portion of the first adhesive portion adjacent to the side of the filter chip is greater than a minimum distance from the lower surface of the filter chip to the first surface.

5. The multi-chip package structure of claim 1, wherein the substrate comprises a solder mask having at least a first opening and a second opening, the first and second pads being located within the first and second openings, respectively, and a first glue portion disposed around the filter chip being located at least partially on the solder mask.

6. The multi-chip package structure of claim 5, wherein the thickness of the solder mask layer is greater than the thickness of the first pad or the second pad exposed from the first surface.

7. The multi-chip package structure of claim 1, wherein the glue portion further comprises a second glue portion, the non-filter chip further comprises a first solder joint and a second solder joint, the second glue portion covers at least one of the first solder joint and the second solder joint;

8. The multi-chip package structure of claim 7, wherein the second adhesive portion further covers at least one of at least a portion of a side surface of the non-filter chip and an upper surface of the non-filter chip.

9. The multi-chip package structure of claim 1, wherein a thickness difference between any two positions of the glue portion is less than a second threshold, the second threshold being 25 μιη, 20 μιη, or 15 μιη.

10. The multi-chip package structure of claim 1, wherein at least a portion of the first glue portion proximate to the filter chip has a gap with the side of the filter chip; or at least part of the first adhesive part close to the filter chip is attached to the side surface of the filter chip.

11. The multi-chip package structure of claim 1 or 10, wherein the first adhesive portion covers at least a portion of the upper surface of the filter chip.

12. The multi-chip package structure of claim 1, further comprising a first chip, wherein the substrate comprises a second surface opposite the first surface, and wherein the first chip is disposed on the first surface and/or the second surface.

13. The multi-chip package structure of claim 12, wherein the first chip is a filter chip, a non-filter chip, or a passive component.

14. A multi-chip package structure, comprising:

15. A multi-chip package structure, comprising:

16. The multi-chip package structure of claim 15, wherein the non-filter chip further comprises a first solder joint and a second solder joint, the glue part further comprises a fourth glue part, and the fourth glue part is arranged on the surface of the third glue part facing away from the substrate through a dispensing process so as to cover at least one of the first solder joint and the second solder joint;

17. A radio frequency front end module comprising the multi-chip package structure of any of claims 1-16.