CN218414581U - Chip packaging structure and chip module - Google Patents

Chip packaging structure and chip module Download PDF

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Publication number
CN218414581U
CN218414581U CN202221986267.9U CN202221986267U CN218414581U CN 218414581 U CN218414581 U CN 218414581U CN 202221986267 U CN202221986267 U CN 202221986267U CN 218414581 U CN218414581 U CN 218414581U
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China
Prior art keywords
chip
substrate
chip device
package structure
protective layer
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CN202221986267.9U
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Chinese (zh)
Inventor
倪建兴
王华磊
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Ruishi Chuangxin Chongqing Technology Co ltd
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Ruishi Chuangxin Chongqing Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model relates to a chip package technical field specifically provides a chip package structure and chip module. The utility model discloses a chip package structure includes the base plate, first chip device, the second chip device, protective layer and stopping, wherein first chip device all falls to adorn on the base plate with the second chip device, the first chip device surface of protective layer laminating is laid to the base plate on, the stopping encapsulates two chip devices, make all have the cavity between first chip device and second chip device and the base plate, thereby keep the homogeneity of cavity distribution in the chip package structure, prevent that the unbalance of stress from causing inside fault or life-span to reduce, thereby can improve package structure's reliability.

Description

Chip packaging structure and chip module
Technical Field
The utility model relates to a chip package technical field especially relates to a chip package structure and chip module.
Background
With the miniaturization of electronic devices, the market demands higher and higher integration of chips, and chips with different functions are usually integrated together and flip-chip mounted on a substrate. For example, a chip with a filtering function, such as a Surface Acoustic Wave (SAW) filter chip and a Bulk Acoustic Wave (BAW) filter chip, requires a cavity structure between the chip and a substrate in a packaging process to meet the function, performance or other special requirements. In practice, it is found that chips with different functions are integrated, and because the packaging requirements are different, the problem of unbalanced stress may exist, and the reliability of the packaging structure is reduced.
SUMMERY OF THE UTILITY MODEL
An embodiment of the utility model provides a chip package structure and chip module can improve chip package structure's reliability.
The embodiment of the utility model provides a first aspect provides a chip packaging structure, include:
a substrate;
a first chip device including a first chip and a plurality of first bumps, the first chip device being connected with the substrate through the plurality of first bumps;
a second chip device including a second chip and a plurality of second bumps, the second chip device being connected to the substrate through the plurality of second bumps;
a protective layer attached to an outer surface of the first chip device and laid on the substrate;
and the filling material covers the protective layer to encapsulate the first chip device and the second chip device, so that a first cavity is formed between the first chip device and the substrate, and a second cavity is formed between the second chip device and the substrate.
Optionally, the substrate is provided with a bearing structure, and the bearing structure is provided with at least two windows;
the first chip device is connected to the substrate within a first one of the at least two windows via the first plurality of bumps, and the second chip device is connected to the substrate within a second one of the at least two windows via the second plurality of bumps;
a first cavity is formed between the first chip device and the substrate in the first window;
a second cavity is formed between the second chip device and the substrate in the second window.
Optionally, the protective layer is applied to a surface of the supporting structure away from the substrate.
Optionally, the carrying structure has a step structure, the step structure includes a first surface and a second surface, and a distance between the first surface and the substrate is smaller than a distance between the second surface and the substrate;
the first chip device and/or the second chip device are located on the first surface at an edge of an orthographic projection towards the substrate.
Optionally, a gap exists between the first chip device and/or the second chip device and the carrying structure.
Optionally, the first chip device and/or the second chip device is attached to the carrier structure.
Optionally, the first chip is a filtering function chip, and the second chip is a non-filtering function chip.
Optionally, the outer surface of the first chip device includes a first front surface of the first chip device, which is away from the substrate, and the protective layer attached to the first front surface has a first opening.
Optionally, the area of the first front surface exposed to the first opening is in contact with the filling material.
Optionally, the protective layer further conforms to an outer surface of the second chip device.
Optionally, the outer surface of the second chip device includes a second front surface of the second chip device, the second front surface being away from the substrate, and the protective layer attached to the second front surface has a second opening.
Optionally, the area of the second front surface exposed to the second opening is in contact with the filling material.
Optionally, the protective layer is an epoxy film.
Optionally, the height of the first cavity is equal to the height of the second cavity.
The embodiment of the utility model provides a second aspect provides a chip module, including any chip package structure of the aforesaid.
The embodiment of the utility model provides an in, chip package structure includes the base plate, first chip device, the second chip device, protective layer and stopping, wherein first chip device all adorns on the base plate with the second chip device, protective layer laminating first chip device's surface is laid to the base plate on, the stopping encapsulates two chip devices, make all have the cavity between first chip device and second chip device and the base plate, thereby keep the homogeneity of cavity distribution in the chip package structure, prevent that the unbalance of stress from causing inside fault or life-span to reduce, thereby can improve package structure's reliability.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic diagram of a chip package structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another chip package structure provided in an embodiment of the present invention;
fig. 3 is a schematic diagram of another chip package structure provided in an embodiment of the present invention;
fig. 4 is a schematic diagram of another chip package structure provided in an embodiment of the present invention;
fig. 5 is a schematic diagram of another chip package structure provided in an embodiment of the present invention;
fig. 6 is a schematic diagram of another chip package structure provided in an embodiment of the present invention;
fig. 7 is a schematic diagram of another chip package structure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on," adjacent to, "" connected to, "or" coupled to, "" connected to, "" and "823030," other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under 82303030," "under 823030; below," "under 823030; above," "over," etc. may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230, below" and "at 8230, below" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed structures and steps will be provided in the following description so as to explain the technical solution provided by the present invention. The preferred embodiments of the present invention are described in detail below, however, other embodiments of the present invention are possible in addition to these detailed descriptions.
The utility model relates to a chip package technical field, concretely relates to chip package structure and chip module. When a plurality of chip devices exist in the conventional chip packaging structure, if some chip devices (such as the chip devices with the filtering function) need cavities during packaging, and other chip devices do not need cavities during packaging, the cavities in the chip packaging structure may have the condition of uneven distribution, so that the stress imbalance of the packaging structure causes internal faults or reduces the reliability of the packaging structure. In order to solve the above problems, the present invention has been conceived and will be explained in detail by the following embodiments:
it should be noted that the embodiment of the present invention can be applied to the packaging structure of a plurality of filtering function chip devices, and also can be applied to the packaging structure of a plurality of non-filtering function chip devices, and also can be applied to the packaging structure of a chip module, where the module includes a filtering function chip device and a non-filtering function chip device.
In an embodiment, please refer to fig. 1 and fig. 2, fig. 1 is a schematic diagram of a chip package structure according to an embodiment of the present invention, and fig. 2 is a schematic diagram of another chip package structure according to an embodiment of the present invention. The chip package structure shown in the figure comprises a substrate 1, a first chip device 2, a second chip device 3, a protective layer 4 and a filling material 5.
The substrate 1 may be a resin, ceramic, quartz, or other type of substrate, and this embodiment is not limited thereto. One surface of the substrate 1 is provided with a plurality of pads 12, and the pads 12 may be embedded in the substrate 1 or disposed on the surface of the substrate 1, which is not limited in this embodiment. The bonding pad 12 may be a metal or an alloy, the metal may be nickel, palladium, molybdenum, tungsten, ruthenium, gold, magnesium, aluminum, copper, chromium, titanium, osmium, iridium, or the like, and the bonding pad 12 is connected to an external or internal circuit through a wiring (not shown) on the substrate 1.
In this embodiment, the first chip device 2 includes a first chip and a plurality of first bumps 21, and the first chip device 2 is flip-chip mounted on the substrate 1. Specifically, the first bump 21 may be tin, gold, or the like, or may be a commonly used bump type such as a metal bump, and the embodiment is not limited thereto. One end of the plurality of first bumps 21 is connected to a wiring (not shown) of the first chip, and the first chip device 2 is connected to the pad 12 on the substrate 1 through the plurality of first bumps 21, thereby achieving connection to an external circuit or an internal circuit.
In this embodiment, the second chip device 3 includes a second chip and a plurality of second bumps 31, and the second chip device 3 is flip-chip mounted on the substrate 1. Specifically, the second bump 31 may be tin, gold, or the like, or may be a commonly used bump type such as a metal bump, and the embodiment is not limited thereto. One end of the plurality of second bumps 31 is connected to the wiring of the second chip, and the second chip device 3 is connected to the pad 12 on the substrate 1 through the plurality of second bumps 31, so as to be connected to an external circuit.
In this embodiment, the protective layer 4 is attached to the outer surface of the first chip device 2 and is disposed on the substrate 1. The first chip means 2 comprises an inner surface, which is the side opposite to the substrate 1, and an outer surface, which is the other surface than the inner surface, such as the side, the front side facing away from the substrate 1. The protective layer 4 is applied to the substrate 1, which means that the protective layer 4 is applied to the surface of the substrate 1 provided with the pads 12 except for the overlapping portions with the first chip arrangement 2 and the second chip arrangement 3.
Further, as shown in fig. 2, the outer surface of the first chip device 2 includes a first front surface 23 and a side surface 24 of the first chip device 2 away from the substrate 1, and the protective layer 4 attached to the first front surface 23 has a first opening 41.
It is understood that the first opening 41 may penetrate through the protective layer 4, such that the area of the first front surface 23 exposed to the first opening 41 is in contact with the filling material 5; the first opening 41 may not penetrate through the protection layer 4, i.e. the bottom of the first opening 41 is on the protection layer 4, and thus the first front surface 23 is not exposed to contact with the filling material 5.
The shape of the first opening 41 may be square, circular, or trapezoidal, or may be regular or irregular shapes such as a circular ring, a square ring, or a cross opening, the number of the first openings 41 may be one or multiple, and the shape, number, size, and the like of the first opening 41 are not limited in this embodiment, and it is only necessary to attach the protective layer 4 to the side surface 24. The first opening 41 is not beyond the edge of the first front surface 23, and the first opening 41 may be near the middle region of the first front surface 23, or may be located at the edge region of the first front surface 23, which is not limited in this embodiment.
Optionally, the protective layer 4 further adheres to an outer surface of the second chip assembly 3, and the second chip assembly 3 includes an inner surface and an outer surface, the inner surface is a surface opposite to the substrate 1, and the outer surface is another surface except the inner surface, such as a side surface and a front surface far away from the substrate 1.
Further, the outer surface of the second chip device 3 includes a second front surface 32 and a side surface 33 of the second chip device 3 away from the substrate 1, and the protective layer 4 attached to the second front surface 32 has a second opening 42.
It is understood that the second opening 42 may penetrate through the protective layer 4, such that the area of the second front surface 32 exposed to the second opening 42 contacts the filling material 5; the second opening 42 may not penetrate through the protection layer 4, i.e. the bottom of the second opening 42 is on the protection layer 4, and thus the second front surface 32 is not exposed to contact with the filling material 5.
The shape of the second opening 42 may be square, circular, or trapezoidal, or may be regular or irregular shapes such as a circular ring, a square ring, or a cross opening, the number of the second openings 42 may be one or multiple, and the shape, number, size, and the like of the second openings 42 are not limited in this embodiment, and only the protective layer 4 needs to be attached to the side surface of the second chip device 3. The second opening 42 does not exceed the edge of the second front surface 32, and the second opening 42 may be near the middle region of the second front surface 32, or may be located at the edge region of the second front surface 32, which is not limited in this embodiment.
It is understood that the protective layer 4 may be applied only to the outer surface of the first chip arrangement 2 and applied to the substrate 1 around the first chip arrangement 2, as shown in fig. 2; or may be bonded to the outer surface of the first chip device 2 and the outer surface of the second chip device 3, and laid on the substrate 1, as shown in fig. 1, which is not limited in this embodiment.
In the process, the protective layer is generally laid on one surface of the chip device away from the substrate, then pressure facing the substrate is applied to the protective layer between the chip devices or the protective layer outside the chip devices, so that the protective layer is attached to the outer surface of the chip device and the substrate, a closed cavity is formed between the chip device and the substrate, and then the filler covers the protective layer. Since the protective layer is limited by its ductility, the above process is liable to cause the protective layer to break, and the filler may enter the cavity from the broken part, causing the chip in the cavity to fail or affecting the working performance of the chip. In this embodiment, the protection layer 4 has an opening on the first front surface 23 and/or the second front surface 32, so that the limitation of ductility of the protection layer 4 is reduced to a certain extent, and thus the protection layer 4 can be prevented from being broken, thereby improving the reliability of chip packaging.
Further, the protective layer 4 has an opening on the front surface of the first chip device 2 and/or the second chip device 3, so that the filling material 5 contacts the chip device at the opening, the bonding force between the chip device and the protective layer 4 and between the chip device and the filling material 5 can be increased, and the reliability of the package structure can be improved.
In one embodiment, the protective layer 4 may be attached to the outer surface of the first chip arrangement 2 and/or the entire outer surface of the second chip arrangement 3 and applied to the substrate 1.
Specifically, the protective layer 4 is used for isolating the filling material 5 from the first cavity 6 and/or the second cavity 7, or for blocking the filling material 5 from entering the first cavity 6 and/or the second cavity 7 to pollute the cavity environment. The protective layer 4 may be specifically an epoxy resin film, or may be another polymer film such as a dry film or another resin material. The protective layer 4 may be a material that has a certain ductility at high temperature, but has a poor fluidity and does not exhibit a liquid state at high temperature, so that the protective layer 4 can better cover surfaces of various shapes and can perform a better blocking function.
In an embodiment, the thickness of the protection layer 4 may be greater than 20um, for example, the thickness of the protection layer 4 may be 40um, 70um, 80um, 100um, or the like, or may be less than or equal to 20um, for example, the thickness of the protection layer 4 may be 18um, 15um, 10um, or the like, which is not limited in this embodiment.
In this embodiment, the filling material 5 covers the protective layer 4 to encapsulate the first chip device 2 and the second chip device 3, so that a first cavity 6 is formed between the first chip device 2 and the substrate 1, and a second cavity 7 is formed between the second chip device 3 and the substrate 1.
In this embodiment, the filler 5 is used to isolate the chip device from the external environment, so as to prevent the chip device from being affected by humidity, temperature, particles, and the like of the external environment, so as to protect the chip device, and the filler 5 may be a molding compound, specifically, a sealing resin, or may contain particles (such as SiO) 2 、Al 2 O 3 Etc.) and may be other insulating materials having good fluidity at high temperatures or in a liquid state.
In this embodiment, the distance between the surface of the first chip arrangement 2 provided with the first bump 21 and the surface of the pad 12 (i.e. the side of the pad 12 facing the first chip arrangement 2) is typically between 5um and 30 um. Preferably, the distance may be between 10um and 20 um. In one case, the distance can be between 45um-50 um. Wherein the distance can be understood as the distance in the thickness direction of the pad 12.
In this embodiment, the distance between the surface of the second chip device 3 provided with the second bump 31 and the surface of the pad 12 (i.e. the surface of the pad 12 facing the second chip device 3) is generally between 5um and 30 um. Preferably, the distance may be between 10um and 20 um. In one case, the distance can be between 45um-50 um. Wherein the distance can be understood as the distance in the thickness direction of the pad 12.
In the present embodiment, the height of the first cavity 6 is equal to the height of the second cavity 7, and it can be understood that the distance between the surface of the first chip device 2 provided with the first bump 21 and the substrate 1 is equal to the distance between the surface of the second chip device 3 provided with the second bump 31 and the substrate 1. This distance can be understood as the distance perpendicular to the substrate 1.
It will be appreciated that the protective layer 4 separates at least the first cavity 6 from the filling material 5, so that the filling material 5 cannot enter the first cavity 6 during the process. As shown in fig. 2, the protective layer 4 only separates the first cavity 6 from the filling material 5, the filling material 5 does not flow into the first cavity 6 during the process, but there is a portion of the filling material 5 flowing into the second cavity 7 between the second chip arrangement 3 and the substrate 1, wherein the protective layer 4 has a first opening 41 on the first front side 23 of the first chip arrangement 2, such that the area of the first front side 23 at the first opening 41 is in contact with the filling material 5. As shown in fig. 1, the protective layer 4 also isolates the second cavity 7 from the filler 5, so as to prevent local filling in the second cavity 7 from causing tin channeling in the upper board filling and non-filling areas, thereby increasing the risk of bridging, and the structure can prepare the protective layer 4 only by one process, thereby reducing the process cost, wherein the protective layer 4 is completely attached to the outer surface of the first chip device 2 and the outer surface of the second chip device 3, and no opening exists.
The embodiment of the utility model provides an in, first chip device 2 and second chip device 3 are all installed upside down on base plate 1, the surface of protective layer 4 laminating first chip device 2 and/or second chip device 3, and lay to base plate 1 on, stopping 5 encapsulates two chip devices, make all have the cavity between first chip device 2 and second chip device 3 and the base plate 1, thereby keep the homogeneity of cavity distribution in the chip package structure, prevent that the unbalance of stress from causing inside fault or life-span to reduce, thereby can improve packaging structure's reliability.
In one embodiment, the first chip is a filter function chip, such as a saw filter, a bulk acoustic wave filter, etc., and includes a function region 22, and a plurality of first bumps 21 are disposed around a periphery of the function region 22; the second chip is a non-filter function chip, such as a power amplifier, a low noise amplifier, a radio frequency switch, and the like. In this embodiment, the protective layer 4 is at least attached to the outer surface of the first chip device 2 and is disposed on the substrate 1, so that the filler 5 does not flow into the first cavity 6 during the process, thereby preventing the filter function chip from being contaminated, and improving the reliability of the chip device.
In another embodiment, please refer to fig. 3-6, and fig. 3-6 are schematic views of another chip package structure according to an embodiment of the present invention. The structure of the substrate 1, the first chip device 2, the second chip device 3, the passivation layer 4 and the filling material 5 is the same as that of the previous embodiment, except that:
the side of the substrate 1 provided with the bonding pad 12 is further provided with a bearing structure 11, and the bearing structure 11 has at least two windows, the bonding pad 12 is located in the at least two windows, the opening direction of the windows may be perpendicular to the substrate 1, or may have a certain included angle with the substrate 1, which is not limited in this embodiment.
Specifically, bearing structure 11 can be that formability is better, hinders the structure that the better material of welding performance formed on base plate 1, also can be base plate 1's solder mask layer structure, for example resin, hinder and weld green paint, dry film etc. the embodiment of the utility model provides a do not restrict.
In the present embodiment, the first chip device 2 is connected to the substrate 1 through a plurality of first bumps 21 in a first window 111 (the area outlined by the dashed line on the left side in the figure) of the at least two windows, and the second chip device 3 is connected to the substrate 1 through a plurality of second bumps 31 in a second window 112 (the area outlined by the dashed line on the left side in the figure) of the at least two windows; a first cavity 6 is formed between the first chip arrangement 2 and the substrate 1, in particular in the first window 111; a second cavity 7 is formed between the second chip arrangement 3 and the substrate 1 in the second window 112.
It is understood that the first chip arrangement 2 and the second chip arrangement 3 are located on the substrate 1 in the middle area of their orthographic projection towards the substrate 1, in particular on the substrate 1 exposed in the window, while their edge areas are located on the carrying structure 11 at the edge of the window. That is, the chip arrangement is flip-chip mounted on the substrate 1, with the central area of the side provided with the bumps facing the substrate 1 in the fenestration, and the edge area facing the surface of the carrier structure 11 facing away from the substrate 1.
Correspondingly, the protective layer 4 is attached to the surface of the carrying structure 11 away from the substrate 1, specifically, the protective layer 4 is attached to the surface of the carrying structure 11 away from the substrate and not opposite to the chip device, and the protective layer 4 is attached to at least the outer surface of the first chip device 2.
In this embodiment, the supporting structure 11 can shorten the distance between the edge of the chip device and the substrate 1, and prevent the protective layer 4 from being broken due to a large distance when the chip device and the substrate 1 are attached to each other, so as to prevent the filler 5 from flowing into the cavity in the process, and this structure enables a relatively airtight cavity to be formed between the substrate 1 and the chip device.
In fig. 3, the first chip arrangement 2 is mounted upside down in the first window 111, the second chip arrangement 3 is mounted upside down in the second window 112, the protective layer 4 adjoins the first front side 23 and the side 24 of the first chip arrangement 2 and the second front side 32 and the side 33 of the second chip arrangement 3 and has a first opening 41 on the first front side 23 and a second opening 42 on the second front side 32, so that the filling compound 5 does not enter the first cavity 6 and the second cavity 7 during the process.
In fig. 4, the protective layer 4 is only attached to the first front side 23 and the side 24 of the first chip arrangement 2, and the first front side 23 has a first opening 41, so that the filling material 5 does not enter the first cavity 6 during the process, and the protective layer 4 is not attached to the outer surface of the second chip arrangement 3.
In fig. 5, the protective layer 4 is applied over the entire outer surface of the first chip arrangement 2 and over the entire outer surface of the second chip arrangement 3, so that the filling material 5 does not enter the first cavity 6 and the second cavity 7 during the process.
In fig. 6, the protective layer 4 is only attached to the entire outer surface of the first chip arrangement 2, so that the filling material 5 does not enter the first cavity 6 during the process, and the protective layer 4 is not attached to the outer surface of the second chip arrangement 3.
Optionally, a gap may be present between the first chip arrangement 2 and/or the second chip arrangement 3 and the carrier structure 11.
Optionally, the first chip device 2 and/or the second chip device 3 is bonded to the carrier structure 11.
Specifically, gaps exist between the edge of the first chip device 2 and the edge of the second chip device 3 and the carrying structure 11; a gap exists between the edge of the first chip device 2 and the bearing structure 11, and the edge of the second chip device 3 is attached to the bearing structure 11; the edge of the first chip device 2 is attached to the bearing structure 11, and a gap exists between the edge of the second chip device 3 and the bearing structure 11; the edge of the first chip arrangement 2 and the edge of the second chip arrangement 3 are attached to the carrier structure 11.
It is understood that the gap between the carrier structure 11 and the first chip arrangement 2 and/or the second chip arrangement 3 may be in the range of 0-15um, such as 0.2um, 0.5um, 1um, 3um, 7um or 10um; or in the range of 0.1um to 5um, which is not limited in this embodiment.
It is understood that the gap between the supporting structure 11 and the first chip apparatus 2 and/or the second chip apparatus 3 may be smaller than or larger than the thickness of the protection layer, and the thickness of the protection layer may be uniform or non-uniform, which is not limited in this embodiment.
In this embodiment, the substrate 1 has a bearing structure 11, the bearing structure 11 is provided with a window, and the first chip device 2 and the second chip device 3 are both inversely mounted on the substrate in the window, so as to reduce the distance between the edge of the chip device and the substrate, and avoid the protective layer 4 from being broken due to an excessively large distance when being attached to the chip device, thereby further avoiding the filler 5 from flowing into the cavity, and improving the reliability of the package structure.
In another embodiment, please refer to fig. 7, fig. 7 is a schematic diagram of another chip package structure according to an embodiment of the present invention. In fig. 7, the carrier structure 11 has a step structure 113, and the step structure 113 includes a first surface 1131 and a second surface 1132, wherein a distance between the first surface 1131 and the substrate 1 is smaller than a distance between the second surface 1132 and the substrate 1, specifically, a distance in a thickness direction of the carrier structure 11.
Further, the first chip arrangement 2 and/or the second chip arrangement 3 are located at the first surface 1131 at the edge of the orthographic projection towards the substrate. The orthographic projection of the first chip arrangement 2 and/or the second chip arrangement 3 towards the substrate may be understood as the projection of the first chip arrangement 2 and/or the second chip arrangement 3 perpendicular to the substrate.
It can be understood that the bearing structure 11 may form the step structure 113 at the first window 111, may form the step structure 113 at the second window 112, and may form the step structure 113 at both the first window 111 and the second window 112, which is not limited in this embodiment.
It is understood that the first chip arrangement 2 is located in the first window 111 in a middle region of the orthographic projection towards the substrate 1, while the edge region is located on the first surface 1131 of the carrier structure 113; and/or the second chip arrangement 3 is located in the second window 112 in a middle region of the orthographic projection towards the substrate 1, while the edge region is located on the first surface 1131 of the carrier structure 113.
It is understood that the bearing structure 11 may be a two-layer structure stacked to form a step structure at the opening, or a one-layer structure processed to form a step structure at the opening, and this embodiment is not limited thereto.
In this embodiment, the bearing structure at the edge of the window is set as a step, and can be used in cooperation with a chip device, so that the distance between the chip device and the bearing structure is further reduced, the risk of breakage of a protective layer is reduced, and the packaging reliability is improved.
In an embodiment, the edge of the first chip arrangement 2 and/or the second chip arrangement 3 may also be provided as a step structure, so as to cooperate with the step structure 113 of the carrier structure 11.
The embodiment of the utility model provides a still provide a chip module, it contains the utility model discloses the chip package structure who mentions. The chip module can comprise a plurality of non-filtering function chip devices, and also can comprise a plurality of filtering function chip devices and a plurality of non-filtering function chip devices.
The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims (15)

1. A chip package structure, comprising:
a substrate;
a first chip device including a plurality of first bumps, the first chip device being connected with the substrate through the plurality of first bumps;
a second chip device including a plurality of second bumps, the second chip device being connected to the substrate through the plurality of second bumps;
a protective layer attached to an outer surface of the first chip device and laid on the substrate;
and the filling material covers the protective layer to encapsulate the first chip device and the second chip device, so that a first cavity is formed between the first chip device and the substrate, and a second cavity is formed between the second chip device and the substrate.
2. The chip package structure according to claim 1, wherein the substrate is provided with a carrier structure having at least two windows;
the first chip device is connected to the substrate within a first one of the at least two windows via the first plurality of bumps, and the second chip device is connected to the substrate within a second one of the at least two windows via the second plurality of bumps;
a first cavity is formed between the first chip device and the substrate in the first window;
a second cavity is formed between the second chip device and the substrate in the second window.
3. The chip package structure according to claim 2, wherein the protection layer is applied to a surface of the supporting structure away from the substrate.
4. The chip package structure according to claim 2, wherein the carrier structure has a step structure, the step structure includes a first surface and a second surface, and a distance between the first surface and the substrate is smaller than a distance between the second surface and the substrate;
the first chip device and/or the second chip device are/is located on the first surface at an edge of a forward projection towards the substrate.
5. The chip packaging structure according to any one of claims 2 to 4, wherein a gap exists between the first chip arrangement and/or the second chip arrangement and the carrier structure.
6. The chip package structure according to any one of claims 2 to 4, wherein the first chip device and/or the second chip device is bonded to the carrier structure.
7. The chip package structure according to claim 1, wherein the first chip is a filter function chip, and the second chip is a non-filter function chip.
8. The chip package structure according to claim 1, wherein the outer surface of the first chip device includes a first front surface of the first chip device away from the substrate, and the protection layer attached to the first front surface has a first opening.
9. The chip package structure according to claim 8, wherein a region of the first front surface exposed to the first opening is in contact with the filling material.
10. The chip package structure according to claim 1, wherein the protective layer further conforms to an outer surface of the second chip device.
11. The chip package structure according to claim 10, wherein the outer surface of the second chip device includes a second front surface of the second chip device away from the substrate, and the protection layer attached to the second front surface has a second opening.
12. The chip package structure according to claim 11, wherein a region of the second front surface exposed to the second opening is in contact with the filling material.
13. The chip package structure according to claim 1, wherein the protective layer is an epoxy film.
14. The chip package structure according to claim 1, wherein a height of the first cavity is equal to a height of the second cavity.
15. A chip module comprising the chip package structure according to any one of claims 1 to 14.
CN202221986267.9U 2022-07-29 2022-07-29 Chip packaging structure and chip module Active CN218414581U (en)

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Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202221986267.9U CN218414581U (en) 2022-07-29 2022-07-29 Chip packaging structure and chip module

Publications (1)

Publication Number Publication Date
CN218414581U true CN218414581U (en) 2023-01-31

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