JPH0993077A - Compound element mounting circuit board - Google Patents
Compound element mounting circuit boardInfo
- Publication number
- JPH0993077A JPH0993077A JP7273679A JP27367995A JPH0993077A JP H0993077 A JPH0993077 A JP H0993077A JP 7273679 A JP7273679 A JP 7273679A JP 27367995 A JP27367995 A JP 27367995A JP H0993077 A JPH0993077 A JP H0993077A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- acoustic wave
- surface acoustic
- pattern
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 150000001875 compounds Chemical class 0.000 title 1
- 238000010897 surface acoustic wave method Methods 0.000 claims abstract description 45
- 239000010409 thin film Substances 0.000 claims abstract description 44
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 14
- 229920005989 resin Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 29
- 239000002131 composite material Substances 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 abstract description 5
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- 239000010408 film Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Electrodes Of Semiconductors (AREA)
- Oscillators With Electromechanical Resonators (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数種類の素子を
搭載した回路基板に関し、特に、弾性表面波素子と他の
素子を複合搭載した高周波回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board on which a plurality of types of elements are mounted, and more particularly to a high frequency circuit board on which a surface acoustic wave element and other elements are mounted in combination.
【０００２】[0002]
【従来の技術】従来、表面を直接樹脂で覆うことのでき
ない弾性表面波素子は、カンパッケージや表面実装形の
セラミックパッケージを用いて気密封止され、プリント
基板に実装されるのが一般的である。図３は従来の弾性
表面波装置を実装した回路基板の部分拡大断面図であ
る。図３に示した弾性表面波装置は、セラミックパッケ
ージ３２の内側底面に接着剤１２でダイボンディングさ
れた弾性表面波素子７のボンディングパッド７ｂと外部
引出し電極３２ｂが金線などのワイヤ１１で接続され、
弾性表面波素子７のくし形電極７ａの弾性表面波が励振
される表面上に中空部９を保ち、くし形電極７ａとボン
ディングパッド７ｂの腐食を防止するため、中空部９の
空気が不活性ガスに置換され、キャップ３２ａにより気
密封止されている。このような弾性表面波装置が他のチ
ップ部品３３とともにプリント基板３１の配線パターン
３１ａ上にはんだ３４で接続搭載されて回路基板が構成
されている。2. Description of the Related Art Conventionally, a surface acoustic wave element whose surface cannot be directly covered with resin is generally hermetically sealed using a can package or a surface mount type ceramic package and mounted on a printed circuit board. is there. FIG. 3 is a partially enlarged sectional view of a circuit board on which a conventional surface acoustic wave device is mounted. In the surface acoustic wave device shown in FIG. 3, the bonding pad 7b of the surface acoustic wave element 7 die-bonded to the inner bottom surface of the ceramic package 32 with the adhesive 12 and the external extraction electrode 32b are connected by a wire 11 such as a gold wire. ,
In order to keep the hollow portion 9 on the surface of the comb-shaped electrode 7a of the surface acoustic wave element 7 where the surface acoustic wave is excited and prevent the comb-shaped electrode 7a and the bonding pad 7b from being corroded, the air in the hollow portion 9 is inactive. It is replaced with gas and is hermetically sealed by the cap 32a. Such a surface acoustic wave device is connected and mounted on the wiring pattern 31a of the printed circuit board 31 with the other chip parts 33 by the solder 34 to form a circuit board.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記の従来構
成では、移動通信機器の軽薄短小化，低コスト化に対応
するための回路基板の配線パターンの微細化，高密度実
装化に限界がある。However, in the above-mentioned conventional structure, there is a limit to the miniaturization of the wiring pattern of the circuit board and the high-density mounting in order to cope with the light, thin, short and small size of the mobile communication device and the cost reduction. .
【０００４】本発明の目的は、従来技術の問題点を解消
し、回路基板の配線パターンの微細化を図ることがで
き、弾性表面波素子を高密度に実装した素子複合搭載回
路基板を提供することにある。An object of the present invention is to solve the problems of the prior art and to miniaturize the wiring pattern of the circuit board, and to provide an element composite mounted circuit board on which surface acoustic wave elements are mounted at high density. Especially.
【０００５】[0005]
【課題を解決するための手段】本発明の請求項１に記載
した素子複合搭載回路基板は、基板と、該基板上に形成
された薄膜抵抗パターンと薄膜コンデンサパターン及び
薄膜インダクタパターンのうち少なくとも１つの薄膜回
路素子と、圧電基板上にくし形電極とボンディングパッ
ドと前記くし形電極の表面波励振面上に中空部を形成す
る薄膜カバーとが設けられた主面を上にして前記基板の
上に載置接合されたチップ状弾性表面波素子と、該チッ
プ状弾性表面波素子の前記ボンディングパッドと前記薄
膜回路素子の回路電極とを接続したワイヤと、前記薄膜
回路素子とチップ状弾性表面波素子とワイヤとを覆った
樹脂とが備えたことを特徴とする。According to a first aspect of the present invention, there is provided an element composite mounted circuit board, and at least one of a substrate, a thin film resistance pattern, a thin film capacitor pattern, and a thin film inductor pattern formed on the substrate. A thin film circuit element, a comb-shaped electrode on the piezoelectric substrate, a bonding pad, and a thin-film cover forming a hollow portion on the surface wave excitation surface of the comb-shaped electrode, with the main surface facing upwards A chip-shaped surface acoustic wave element mounted and bonded to a wire, a wire connecting the bonding pad of the chip-shaped surface acoustic wave element and a circuit electrode of the thin-film circuit element, the thin-film circuit element and the chip-shaped surface acoustic wave. It is characterized in that it is provided with a resin covering the element and the wire.
【０００６】さらに、本発明の請求項２に記載した素子
複合搭載回路基板は、前記チップ状弾性表面波素子は、
前記薄膜コンデンサパターンの上部電極の上に載置接合
されたことを特徴とするものである。Further, in the element composite mounted circuit board according to claim 2 of the present invention, the chip-shaped surface acoustic wave element is
The thin film capacitor pattern is placed and bonded on the upper electrode.
【０００７】[0007]
【発明の実施の形態】本発明の素子複合搭載回路基板
は、例えば、シリコン下基板の上に生成されたシリコン
酸化膜上に薄膜コンデンサパターンや薄膜抵抗パターン
または薄膜インダクタパターンを形成して薄膜による回
路を設け、基板上または薄膜コンデンサパターンの上に
弾性表面波素子を配置し、前記基板の配線パターン回路
電極と弾性表面波素子のボンディングパッドとをワイヤ
で接続し、くし形電極の表面波励振部表面を薄膜カバー
により中空に確保して樹脂により基板上の薄膜回路と弾
性表面波素子を同時に封止したことを要旨とする。BEST MODE FOR CARRYING OUT THE INVENTION The element composite mounted circuit board of the present invention is formed of a thin film by forming a thin film capacitor pattern, a thin film resistance pattern or a thin film inductor pattern on a silicon oxide film formed on a silicon lower substrate, for example. A circuit is provided, a surface acoustic wave element is arranged on the substrate or on the thin film capacitor pattern, and the wiring pattern circuit electrode of the substrate and the bonding pad of the surface acoustic wave element are connected by a wire to excite the surface wave of the comb-shaped electrode. The gist is that the surface of the part is kept hollow by a thin film cover, and the thin film circuit on the substrate and the surface acoustic wave element are simultaneously sealed with resin.
【０００８】以下図面により本発明を詳細に説明する。
図１は本発明の第１の実施例を示す部分断面図である。
この実施例は、弾性表面波素子７の主面を上にして基板
１の上に載置した例である。図１において、１は基板、
２は絶縁層、３は回路電極、４は抵抗パターン、５はコ
ンデンサパターン、６はインダクタパターン、７は弾性
表面波素子、８は樹脂、９は中空部、１０は薄膜カバ
ー、１１はワイヤ、１２は接着剤である。The present invention will be described in detail below with reference to the drawings.
FIG. 1 is a partial sectional view showing a first embodiment of the present invention.
In this embodiment, the surface acoustic wave element 7 is mounted on the substrate 1 with the main surface thereof facing upward. In FIG. 1, 1 is a substrate,
2 is an insulating layer, 3 is a circuit electrode, 4 is a resistance pattern, 5 is a capacitor pattern, 6 is an inductor pattern, 7 is a surface acoustic wave element, 8 is a resin, 9 is a hollow portion, 10 is a thin film cover, 11 is a wire, 12 is an adhesive.
【０００９】例えば、シリコン基板などの基板１の表面
に酸化膜またはポリイミド膜等の絶縁層２を設け、その
上に蒸着法またはスパッタリング法等で薄膜導体を成膜
し、さらにスパッタリング法やホトエッチング法等の手
段を用いてコンデンサ用の誘電体５ａを形成する。その
後、抵抗用と電極用の薄膜を成膜し、ホトエッチング法
等で回路電極３，抵抗パターン４，上部電極５ｂ，下部
電極５ｃ，コンデンサパターン５等が形成される。さら
にインダクタパターン６は予めパターン形成していた部
分にめっき等により導体を厚膜化し形成することにより
薄膜の受動素子回路が基板１上に形成される。For example, an insulating layer 2 such as an oxide film or a polyimide film is provided on the surface of a substrate 1 such as a silicon substrate, a thin film conductor is formed thereon by a vapor deposition method or a sputtering method, and further, a sputtering method or photo etching. The dielectric 5a for the capacitor is formed by using a method such as a method. After that, thin films for resistors and electrodes are formed, and the circuit electrodes 3, the resistance pattern 4, the upper electrode 5b, the lower electrode 5c, the capacitor pattern 5 and the like are formed by photoetching or the like. Further, in the inductor pattern 6, a thin film passive element circuit is formed on the substrate 1 by forming a thick film of a conductor on a portion where a pattern is formed in advance by plating or the like.
【００１０】上記の薄膜の受動素子の周辺部に載置固定
される弾性表面波素子７のくし形電極７ａの上には、薄
膜カバー１０により中空部９が確保されている。ここで
図面の中空部９の前後の空洞出入口の部分は樹脂等によ
りすでに封止されており、受動素子および弾性表面波素
子７とワイヤ１１等を確保する樹脂８の流れ込みは起こ
らないようになっている。A hollow portion 9 is secured by a thin film cover 10 on the comb-shaped electrode 7a of the surface acoustic wave element 7 mounted and fixed on the peripheral portion of the thin film passive element. Here, the cavity inlet and outlet portions before and after the hollow portion 9 in the drawing are already sealed with resin or the like, so that the passive element and the surface acoustic wave element 7 and the resin 8 for securing the wire 11 and the like do not flow in. ing.
【００１１】弾性表面波素子７は、くし形電極７ａとボ
ンディングパッド７ｂが形成されている主面を上にし
て、上述の受動素子回路が形成されている面の受動素子
周辺部に接着剤１２等で載置固定され、弾性表面波素子
７のボンディングパッド７ｂと基板１上の回路電極３と
金等のワイヤ１１により電気的に接続されている。ワイ
ヤ１１による弾性表面波素子７と基板１上の受動素子の
回路電極３との接続部と、ワイヤ１１と弾性表面波素子
７は、エポキシ等の樹脂８でモールドされ保護されてい
る。The surface acoustic wave element 7 has an adhesive 12 on the periphery of the passive element on the surface on which the above-mentioned passive element circuit is formed, with the main surface on which the comb-shaped electrode 7a and the bonding pad 7b are formed facing up. And the like, and is electrically connected by the bonding pad 7b of the surface acoustic wave element 7, the circuit electrode 3 on the substrate 1 and the wire 11 such as gold. The connection between the surface acoustic wave element 7 by the wire 11 and the circuit electrode 3 of the passive element on the substrate 1, and the wire 11 and the surface acoustic wave element 7 are molded and protected by a resin 8 such as epoxy.
【００１２】図２は本発明の第２の実施例を示す部分断
面図である。この実施例は、弾性表面波素子７を、その
主面を上にして基板１上のコンデンサパターン５の上に
載置した例である。図２において、例えばシリコン基板
などの基板１の表面に酸化膜またはポリイミド膜等の絶
縁層２を形成し、その上に蒸着法またはスパッタリング
法等で、コンデンサパターンの下部電極５ｃとなる薄膜
導体を成膜し、さらにスパッタリング法やホトエッチン
グ法等の手段を用いてコンデンサ用の誘電体５ａをパタ
ーン形成する。その後、抵抗用と電極用の薄膜を成膜
し、ホトエッチング法等で回路電極３，抵抗パターン
４，上部電極５ｂ，コンデンサパターン５等が形成され
る。FIG. 2 is a partial sectional view showing a second embodiment of the present invention. This embodiment is an example in which the surface acoustic wave element 7 is placed on the capacitor pattern 5 on the substrate 1 with its main surface facing upward. In FIG. 2, an insulating layer 2 such as an oxide film or a polyimide film is formed on the surface of a substrate 1 such as a silicon substrate, and a thin film conductor to be the lower electrode 5c of the capacitor pattern is formed on the insulating layer 2 by vapor deposition or sputtering. After forming a film, a dielectric 5a for a capacitor is patterned by using a method such as a sputtering method or a photoetching method. After that, thin films for resistors and electrodes are formed, and the circuit electrodes 3, the resistance pattern 4, the upper electrode 5b, the capacitor pattern 5 and the like are formed by photoetching or the like.
【００１３】上記のコンデンサパターン５の上部電極５
ｂ上に載置固定した弾性表面波素子７のくし形電極７ａ
の上には、薄膜カバー１０により中空部９が確保されて
いる。ここで図面の中空部９の前後の空洞出入口の部分
は樹脂等によりすでに封止されており、受動素子および
弾性表面波素子７とワイヤ１１等を保護する樹脂８の流
れ込みは起こらないようになっている。The upper electrode 5 of the above capacitor pattern 5
comb-shaped electrode 7a of the surface acoustic wave element 7 mounted and fixed on b
The hollow portion 9 is secured by the thin film cover 10 on the upper side. Here, the cavity inlet and outlet portions before and after the hollow portion 9 in the drawing are already sealed with resin or the like, so that the resin 8 for protecting the passive element and the surface acoustic wave element 7, the wire 11 and the like does not flow in. ing.
【００１４】弾性表面波素子７は、くし形電極７ａとボ
ンディングパッド７ｂが形成されている主面を上にし
て、上述のコンデンサパターン５の上部電極５ｂ上に接
着剤１２等で載置固定され、ボンディングパッド７ｂと
基板１上の回路電極３と金等のワイヤ１１により電気的
に接続されている。大容量のコンデンサは大面積が必要
になるが、通常、上部電極５ｂを接地電位にしておけ
ば、その上に弾性表面波素子等のベアチップを搭載して
も電気的影響は無視できる。そうすることで基板上に多
段に素子を積み重ねて構成できるため、実装効率が格段
に上がる。ワイヤ１１による弾性表面波素子７と基板１
上の受動素子の回路電極３との接続部と、ワイヤ１１と
弾性表面波素子７は、エポキシ等の樹脂８でモールドさ
れ保護されている。The surface acoustic wave element 7 is mounted and fixed with an adhesive 12 or the like on the upper electrode 5b of the above-mentioned capacitor pattern 5 with the main surface on which the comb-shaped electrode 7a and the bonding pad 7b are formed facing up. , The bonding pad 7b, the circuit electrode 3 on the substrate 1 and the wire 11 made of gold or the like are electrically connected. A large-capacity capacitor requires a large area, but normally, if the upper electrode 5b is set to the ground potential, even if a bare chip such as a surface acoustic wave element is mounted on it, the electrical influence can be ignored. By doing so, it is possible to stack the elements on the substrate in a multi-tiered manner, so that the mounting efficiency is significantly improved. Surface acoustic wave element 7 and substrate 1 by wire 11
The connection portion of the upper passive element to the circuit electrode 3, the wire 11 and the surface acoustic wave element 7 are molded and protected by a resin 8 such as epoxy.
【００１５】これにより、従来、弾性表面波素子の表面
波励振部を保護するためのパッケージに収められた弾性
表面波装置を使用することなく、弾性表面波素子を、チ
ップ（素子）状態で、薄膜受動素子が既に形成された回
路基板上に実装することができるので、小型、薄型な回
路基板を得ることができる。As a result, the surface acoustic wave element can be mounted in a chip (element) state without using the surface acoustic wave device conventionally housed in a package for protecting the surface wave excitation portion of the surface acoustic wave element. Since the thin film passive element can be mounted on the circuit board on which the thin film passive element is already formed, a small and thin circuit board can be obtained.
【００１６】なお、第１の実施例の基板１上の薄膜受動
素子の構造は限定されず、コンデンサ５について図面で
はＭＩＭ（Metal Insulator Meta）型になっているが、
くし形構造でもよい。またインダクタ６についても図面
ではスパイラル形になっているがミアンダ形等でもよ
い。さらに第２の実施例におけるコンデンサを除く薄膜
受動素子の構造も限定されない。さらに第２の実施例に
おいて、図面ではインダクタが記載されてないが含まれ
ていてもよい。この発明によれば、基板の材質はシリコ
ンのような半導体でもよく、またセラミック，ガラス，
サファイヤ等を基板として使用してもよい。ここで、基
板の材質によっては絶縁層２を省いてもよい。さらに、
薄膜導体等は１層とは限定されず、接続する材質によ
り、拡散による剥離を防止するための薄膜層を追加する
等、２層以上であってもよい。The structure of the thin film passive element on the substrate 1 of the first embodiment is not limited, and the capacitor 5 is of the MIM (Metal Insulator Meta) type in the drawing,
It may have a comb structure. The inductor 6 is also spiral in the drawing, but may be meandering or the like. Further, the structure of the thin film passive element other than the capacitor in the second embodiment is not limited. Further, in the second embodiment, the inductor is not shown in the drawing, but may be included. According to the invention, the material of the substrate may be a semiconductor such as silicon, ceramic, glass,
Sapphire or the like may be used as the substrate. Here, the insulating layer 2 may be omitted depending on the material of the substrate. further,
The thin film conductor and the like are not limited to one layer, and may be two or more layers depending on the material to be connected, such as adding a thin film layer for preventing separation due to diffusion.
【００１７】[0017]
【発明の効果】チップ状弾性表面波素子を他の素子と共
に搭載した本発明の素子複合搭載回路基板は、受動素子
を含む回路が薄膜で形成された回路基板の上から弾性表
面波素子をチップの状態で回路電極に接続することがで
きるため、小型化，薄型化が図れる。チップ状の弾性表
面波素子を直接実装できるので、配線長が短くなり、特
性が向上し、パッケージ等が不要になり、樹脂封止等だ
けでよいため経済的にも利点がある。弾性表面波素子の
下にも他の受動素子等を形成することが可能になるの
で、実装密度が格段に向上できる。According to the element composite mounting circuit board of the present invention in which a chip-shaped surface acoustic wave element is mounted together with other elements, a surface acoustic wave element is chipped on a circuit board on which a circuit including passive elements is formed by a thin film. Since it can be connected to the circuit electrode in this state, the size and thickness can be reduced. Since the chip-shaped surface acoustic wave element can be directly mounted, the wiring length is shortened, the characteristics are improved, the package etc. are not required, and only resin sealing or the like is required, which is economically advantageous. Since other passive elements and the like can be formed under the surface acoustic wave element, the packaging density can be significantly improved.
【図１】本発明の第１の実施例を示す部分断面図であ
る。FIG. 1 is a partial cross-sectional view showing a first embodiment of the present invention.
【図２】本発明の第２の実施例を示す部分断面図であ
る。FIG. 2 is a partial sectional view showing a second embodiment of the present invention.
【図３】従来の弾性表面波装置を搭載した回路基板の部
分断面図である。FIG. 3 is a partial cross-sectional view of a circuit board on which a conventional surface acoustic wave device is mounted.
１ 基板 ２ 絶縁層 ３ 回路電極 ４ 抵抗パターン ５ コンデンサパターン ５ａ 誘電体 ５ｂ 上部電極 ５ｃ 下部電極 ６ インダクタパターン ７ 弾性表面波素子 ７ａ くし形電極 ７ｂ ボンディングパッド ８ 樹脂 ９ 中空部 １０ 薄膜カバー １１ ワイヤ １２ 接着剤 ３１ プリント基板 ３１ａ 配線パターン ３２ セラミックパッケージ ３２ａ キャップ ３２ｂ 外部引出し電極 ３３ チップ部品 ３４ はんだ 1 Substrate 2 Insulating Layer 3 Circuit Electrode 4 Resistance Pattern 5 Capacitor Pattern 5a Dielectric 5b Upper Electrode 5c Lower Electrode 6 Inductor Pattern 7 Surface Acoustic Wave Element 7a Comb-shaped Electrode 7b Bonding Pad 8 Resin 9 Hollow 10 Thin Film Cover 11 Wire 12 Adhesion Agent 31 Printed circuit board 31a Wiring pattern 32 Ceramic package 32a Cap 32b External extraction electrode 33 Chip component 34 Solder
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０３Ｈ 9/145 Ｈ０１Ｌ 41/08 Ｄ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H03H 9/145 H01L 41/08 D
Claims (2)
パターンと薄膜コンデンサパターン及び薄膜インダクタ
パターンのうち少なくとも１つの薄膜回路素子と、圧電
基板上にくし形電極とボンディングパッドと前記くし形
電極の表面波励振面上に中空部を形成する薄膜カバーと
が設けられた主面を上にして前記基板の上に載置接合さ
れたチップ状弾性表面波素子と、該チップ状弾性表面波
素子の前記ボンディングパッドと前記薄膜回路素子の回
路電極とを接続したワイヤと、前記薄膜回路素子とチッ
プ状弾性表面波素子とワイヤとを覆った樹脂とが備えら
れた素子複合搭載回路基板。1. A substrate, at least one thin film circuit element formed on the substrate among a thin film resistance pattern, a thin film capacitor pattern, and a thin film inductor pattern, a comb electrode on a piezoelectric substrate, a bonding pad, and the comb shape. A chip-like surface acoustic wave element mounted and bonded on the substrate with a main surface provided with a thin film cover forming a hollow portion on a surface wave exciting surface of an electrode, and the chip-like surface acoustic wave An element-composite mounting circuit board comprising a wire connecting the bonding pad of the element and a circuit electrode of the thin film circuit element, and a resin covering the thin film circuit element, the chip-shaped surface acoustic wave element and the wire.
膜コンデンサパターンの上部電極の上に載置接合された
ことを特徴とする請求項１記載の素子複合搭載回路基
板。2. The element-composite circuit board according to claim 1, wherein the chip-shaped surface acoustic wave element is mounted and bonded on the upper electrode of the thin film capacitor pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27367995A JP3421179B2 (en) | 1995-09-28 | 1995-09-28 | Element composite mounted circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27367995A JP3421179B2 (en) | 1995-09-28 | 1995-09-28 | Element composite mounted circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0993077A true JPH0993077A (en) | 1997-04-04 |
| JP3421179B2 JP3421179B2 (en) | 2003-06-30 |
Family
ID=17531048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27367995A Expired - Fee Related JP3421179B2 (en) | 1995-09-28 | 1995-09-28 | Element composite mounted circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3421179B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1394856A2 (en) * | 2002-08-29 | 2004-03-03 | Fujitsu Media Devices Limited | Surface-mounted electronic component module and method for manufacturing the same |
| KR100434839B1 (en) * | 2000-05-30 | 2004-06-07 | 알프스 덴키 가부시키가이샤 | An electronic circuit unit |
| WO2012127979A1 (en) * | 2011-03-22 | 2012-09-27 | 株式会社村田製作所 | Manufacturing method for electronic component module and electronic component module |
| KR101341619B1 (en) * | 2011-12-27 | 2014-01-13 | 전자부품연구원 | Semiconductor package and method for manufacturing semiconductor package |
| US20170141756A1 (en) * | 2015-11-17 | 2017-05-18 | Qualcomm Incorporated | Acoustic resonator devices |
| US10135421B2 (en) | 2016-08-11 | 2018-11-20 | Samsung Electro-Mechanics Co., Ltd. | Bulk-acoustic wave filter device |
| US11289246B2 (en) | 2019-05-23 | 2022-03-29 | Seiko Epson Corporation | Vibrator device, electronic apparatus, and vehicle |
-
1995
- 1995-09-28 JP JP27367995A patent/JP3421179B2/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100434839B1 (en) * | 2000-05-30 | 2004-06-07 | 알프스 덴키 가부시키가이샤 | An electronic circuit unit |
| EP1394856A2 (en) * | 2002-08-29 | 2004-03-03 | Fujitsu Media Devices Limited | Surface-mounted electronic component module and method for manufacturing the same |
| WO2012127979A1 (en) * | 2011-03-22 | 2012-09-27 | 株式会社村田製作所 | Manufacturing method for electronic component module and electronic component module |
| CN103444077A (en) * | 2011-03-22 | 2013-12-11 | 株式会社村田制作所 | Manufacturing method for electronic component module and electronic component module |
| JP5626451B2 (en) * | 2011-03-22 | 2014-11-19 | 株式会社村田製作所 | Electronic component module manufacturing method and electronic component module |
| US9590586B2 (en) | 2011-03-22 | 2017-03-07 | Murata Manufacturing Co., Ltd. | Electronic component module |
| KR101341619B1 (en) * | 2011-12-27 | 2014-01-13 | 전자부품연구원 | Semiconductor package and method for manufacturing semiconductor package |
| US20170141756A1 (en) * | 2015-11-17 | 2017-05-18 | Qualcomm Incorporated | Acoustic resonator devices |
| US10069474B2 (en) * | 2015-11-17 | 2018-09-04 | Qualcomm Incorporated | Encapsulation of acoustic resonator devices |
| US10135421B2 (en) | 2016-08-11 | 2018-11-20 | Samsung Electro-Mechanics Co., Ltd. | Bulk-acoustic wave filter device |
| US11289246B2 (en) | 2019-05-23 | 2022-03-29 | Seiko Epson Corporation | Vibrator device, electronic apparatus, and vehicle |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3421179B2 (en) | 2003-06-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6969945B2 (en) | Surface acoustic wave device, method for manufacturing, and electronic circuit device | |
| US6710682B2 (en) | Surface acoustic wave device, method for producing the same, and circuit module using the same | |
| US7251873B2 (en) | Method of manufacturing surface acoustic wave device | |
| JP2003037239A (en) | Semiconductor device and manufacturing method therefor | |
| JPH11177027A (en) | Integrated-circuit semiconductor chip and single-sided package containing inductive coil and manufacture thereof | |
| JP4072816B2 (en) | Composite module and manufacturing method thereof | |
| US8022594B2 (en) | Surface acoustic wave device | |
| JPH05326735A (en) | Semiconductor device and manufacture thereof | |
| JPH08274575A (en) | Composite element mount circuit board | |
| US7876168B2 (en) | Piezoelectric oscillator and method for manufacturing the same | |
| JPH0454973B2 (en) | ||
| JP3421179B2 (en) | Element composite mounted circuit board | |
| JPH0818390A (en) | Surface acoustic wave device | |
| JP6757213B2 (en) | Manufacturing method of semiconductor devices | |
| JPH1050879A (en) | Surface mounting type electronic part | |
| JPH10163798A (en) | Surface acoustic wave element and electronic part using the same | |
| JPH05144953A (en) | Electronic component containing package | |
| JPH10223626A (en) | Semiconductor chip, its manufacture, semiconductor device, and electronic device | |
| KR200148753Y1 (en) | Semiconductor package | |
| JPH06275737A (en) | Package for housing semiconductor element | |
| JP2005027229A (en) | Surface acoustic wave device and its manufacturing method | |
| JPH065731A (en) | Ceramic package and semiconductor device | |
| JPH0449641A (en) | Semiconductor device and printed-circuit board for semiconductor device | |
| JPH10209325A (en) | Flip chip ceramic substrate and its manufacture | |
| JPH05160327A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |