CN115312421A - 用于键合半导体器件的柔性烧结工具 - Google Patents
用于键合半导体器件的柔性烧结工具 Download PDFInfo
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Abstract
一种具有密封板的装置,所述密封板包括刚性硬部和位于所述硬部之间的一个或多个柔性软部,所述装置用于将至少一个半导体器件键合于支撑在平台上的衬底。所述密封板能够在第一位置与第二位置之间移动,所述第一位置与所述衬底隔开,在所述第二位置处,所述密封板的第一侧被配置为与所述衬底接触。隔膜覆盖所述密封板的与所述第一侧相对的第二侧。流体压力发生器对所述隔膜施加流体压力,以致动所述隔膜压缩所述一个或多个软部,从而在键合期间将键合力传递至所述至少一个半导体器件。
Description
技术领域
本发明涉及一种用于键合或烧结半导体器件的装置。
背景技术
在电子器件的制造过程中,烧结工具用于烧结或键合半导体器件。使用的烧结工具通常采用刚性硬质材料。烧结工具通常由金属制成,并且其硬金属表面在烧结过程中压在半导体器件上,以在热量和压力下将半导体器件键合于衬底上。
图1A示出了用于键合半导体器件的现有技术的硬质烧结工具。若干半导体器件12放置于支撑在平台16上的衬底14上,各个半导体器件12具有不同的高度和宽度。多个硬质烧结工具10位于各个半导体器件12上方。各个硬质烧结工具10具有不同的宽度和厚度,并根据其高度设置在各个相应的半导体器件12的上方。在施加合适压力和热量的情况下,将半导体器件12键合于衬底14上。在烧结中使用硬质烧结工具时面临的问题是需要具有不同尺寸的工具来适应具有不同高度和宽度的半导体器件。这将减缓整个键合过程,因为必须手动更换硬质烧结工具以适应放置在衬底上的每个半导体器件的尺寸。
此外,由于所使用的各个硬质烧结工具的厚度和宽度不同,很难对各个半导体器件施加均匀的压力。这将影响半导体器件的整体键合质量,并可能导致寿命缩短或故障。此外,当使用硬质烧结工具时,烧结材料的圆角的位于半导体器件底部边缘的周边之外或者从半导体器件下方挤出的特定部分在键合期间将不会受到烧结压力。这会再次导致键合质量和/或键合产品的质量差,在压力下可能容易出现故障。
此外,在某些情况下,用户需要选择性地对一个或多个特定区域施加烧结压力。而使用现有技术的硬质烧结工具,则无法针对特定区域进行压力选择。
使用硬质烧结工具时面临的另一个困难是无法在一个步骤中对堆叠式半导体器件进行烧结。如图1B所示,在提供的硬质烧结工具的现有技术示例中,管芯顶部系统(DieTop System,DTS)芯片13安装在每个半导体器件12的顶部。通过将半导体器件12键合于衬底14来执行键合工艺的第一步。然后,通过将每个DTS芯片13键合于单独的半导体器件12上来执行键合工艺的第二步。因此,必须执行两步工艺来键合这种堆叠式半导体器件。这个过程很耗时。此外,每个半导体器件12的边角18(在图1B中用虚线表示)往往烧结质量差。
发明内容
因此,本发明的一个目的是寻求提供一种用于将半导体器件键合于衬底上以改进对半导体器件施加烧结压力的工艺的装置,尤其是用于同时键合具有不同厚度的堆叠式半导体器件。
根据本发明的第一方面,提供了一种用于将至少一个半导体器件键合于支撑在平台上的衬底的装置,所述装置包括:密封板,其包括刚性硬部和位于所述硬部之间的一个或多个柔性软部,所述密封板能够在第一位置与第二位置之间移动,所述第一位置与所述衬底隔开,在所述第二位置处,所述密封板的第一侧被配置为与所述衬底接触;隔膜,其覆盖所述密封板的与所述第一侧相对的第二侧;以及与所述隔膜流体连通的流体压力发生器,所述流体压力发生器能够操作用于对所述隔膜施加流体压力,所述流体压力能够进一步操作用于致动所述隔膜压缩所述一个或多个软部,从而使所述至少一个半导体器件与所述一个或多个软部接触,并在键合期间对所述至少一个半导体器件施加键合力。
根据本发明的第二方面,提供了一种将至少一个半导体器件键合于支撑在平台上的衬底的方法,所述方法包括以下步骤:在所述衬底上布置所述至少一个半导体器件;将包括刚性硬部和位于所述硬部之间的一个或多个柔性软部的密封板从第一位置移动至第二位置,所述第一位置与所述衬底隔开,在所述第二位置处,所述密封板的第一侧与所述衬底接触;并且用流体压力发生器在隔膜上生成流体压力,所述隔膜覆盖所述密封板的与所述第一侧相对的第二侧,所述流体压力发生器与隔膜流体连通;其中,对所述隔膜施加的所述流体压力致动所述隔膜压缩所述一个或多个软部,从而使所述至少一个半导体器件与所述一个或多个软部接触,并在键合期间对所述至少一个半导体器件施加键合力。
根据本发明的第三方面,提供了一种制造电子器件的方法,所述电子器件包括至少一个键合于衬底上的半导体器件,所述方法包括以下步骤:在所述衬底上布置所述至少一个半导体器件;将包括刚性硬部和位于所述硬部之间的一个或多个柔性软部的密封板从第一位置移动至第二位置,第一位置与所述衬底隔开,在第二位置处,所述密封板的第一侧与所述衬底接触;并且用流体压力发生器在隔膜上生成流体压力,所述隔膜覆盖所述密封板的与所述第一侧相对的第二侧,所述流体压力发生器与隔膜流体连通;其中,对所述隔膜施加的所述流体压力致动所述隔膜压缩所述一个或多个软部,从而使所述至少一个半导体器件与所述一个或多个软部接触,并在键合期间对所述至少一个半导体器件施加键合力。
附图说明
参考示出本发明特定优选实施例的附图将有助于在下文详细描述本发明。附图和相关描述的特殊性不应被理解为取代权利要求书所限定的本发明的广泛定义的普遍性。
现在将参考附图描述根据本发明的用于将半导体器件键合于衬底的示例性装置,其中:
图1A是根据现有技术的键合装置的侧视图;
图1B是图1A的键合装置在键合堆叠式半导体器件时的侧视图;
图2是根据本发明第一优选实施例的用于将半导体器件键合于衬底的装置的侧视图;
图3是根据本发明第一优选实施例的印模固持器组件和密封板组件的分解等距视图;
图4A至图4C是当密封板组件在不同位置之间移动以将多个半导体器件键合于平面衬底时的侧视图;
图5A至图5C是当密封板组件在不同位置之间移动以将多个半导体器件键合于多个单一衬底时的侧视图;
图6是根据本发明第二优选实施例的印模固持器组件和密封板组件的分解等距视图;
图7A至图7C是当密封板组件在不同位置之间移动以将多个半导体器件键合于多个单一衬底上的侧视图;
图8是根据本发明第二优选实施例的包括压力传感器的密封板组件的侧视图,该压力传感器附接于密封板;
图9是用于将半导体器件键合于衬底的装置的侧视图,该装置具有软质工具部分和硬质工具部分。
除了以上具体描述的之外,还可以对本发明轻易地做出各种变化、修改和/或添加。应当理解,本发明包括落入上述说明书的精神和保护范围之内的所有此类变化、修改和/或添加。
具体实施方式
图2是根据本发明第一优选实施例的用于将半导体器件键合于衬底的装置20的示意性侧视图。装置20通常包括印模固持器组件30和密封板组件40。
印模固持器组件30可包括一个或多个印模32。印模32可以以任何合适的方式布置,例如以规则矩阵或任何其他合适的方式布置。每个印模32可以具有由压力发生器作用的上部32a、以及位于上部32a下方的下部32b。印模32的下部32b靠近密封板组件40,并且可操作用于接触隔膜42。优选地,上部32a具有比下部32b更大的表面积。这有利于提高对密封板组件40所施加的压力。
印模固持器组件30还可以包括印模固持器套筒34和印模固持器本体36。印模固持器套筒34具有一个或多个插槽33,插槽33适于容纳并引导每个印模32的上部32a。印模固持器本体36安装在印模固持器套筒34的下方,并具有适于允许印模32的上部32a进行滑动运动的凹部35。
套环37从印模32水平延伸,并环绕印模32的上部32a的基部。印模32被配置为可在竖直方向上朝向和远离衬底52移动。位于凹部35内的套环37限定了印模32的运动范围。在印模32竖直远离衬底52移动期间,套环37的顶面37a将接触印模固持器套筒34的底面或凹部35的顶面,从而防止印模32进一步向上移动。当印模32朝着衬底52竖直向下移动时,套环37的底面37b将在接触基部39或凹部35的底面时停止。因此,套环37限制了印模32相对于衬底52的运动范围。
密封板组件40位于印模固持器组件30与衬底52之间。密封板组件40包括安装在印模固持器本体36下方的密封板肩部41。密封板肩部41具有通孔,该通孔被设置为容纳印模32的下部32b。图3中更详细地示出了印模固持器组件30和密封板组件40的设置。
密封板组件40还包括位于密封板肩部41下方的密封板44。密封板44具有用于容纳密封插件46的开口。密封插件46具有切口49,适当地设置该切口49的尺寸和形状以容纳软部48。密封板44和形成密封板44的刚性硬部的密封插件46可以由在压力下不可变形的任意合适的刚性硬质材料制成。软部48可以由任何柔软、易弯曲且可弹性变形的材料制成。优选地,软部48由耐热材料制成。软部48适于装配在切口49内,并位于密封板44的由密封插件46形成的硬部之间。可选地,每个密封插件46可以包括密封插件46顶端处的台阶45,台阶45在切口49中形成比在切口49底端处的横截面积更大的横截面积。因此,当对软部48施加压力时,台阶45将软部48固定在密封板44上,以便在键合时对其进行压缩。
隔膜42可以夹在密封板肩部41与密封板44之间,从而覆盖密封板44的上侧。隔膜42是弹性的,从而允许压力有效且均匀地传递至密封板44和软部48。当对隔膜42施加压力时,通过软部48对位于密封板44底侧的半导体器件50施加的压力可以是基本均匀的。
图4A至图4C是当密封板组件40在不同位置之间移动以将多个半导体器件50键合于平面衬底52上时的侧视图。由于可以在不使用印模32的情况下直接对隔膜42施加流体压力以压缩软部48,所以印模固持器组件30和印模32未在图4A至图4C中示出。在图4A所示的示例中,没有对呈平面衬底52形式的衬底进行分离。平面衬底52沿其长度具有不同的高度。在第一位置(如图4A所示)处,密封板44与衬底52隔开。
图4B示出了第二位置,其中,密封板44已朝向平面衬底52竖直向下移动,直至密封板44的底表面与平面衬底52接触。在该示例中,与平面衬底52接触的密封插件46沿着平面衬底52的长度处于不同的高度。该实施例的每个密封插件46能够独立于其他密封插件46移动,并且当与平面衬底52接触时能够相对于其他密封插件46移位。这允许用户指定每个密封插件46对特定区域施加烧结压力。在第二位置处,软部48在进行键合之前还没有接触支撑在平面衬底52上的半导体器件50。还应注意的是,每个密封插件46包括切口49,以在切口49内容纳软部48。
接着,流体压力发生器70对隔膜42施加正压力,进而将压力传递至隔膜42。然后,隔膜42将压力均匀地传递至密封插件46和密封板44的软部48上。流体压力发生器70可以是气动致动器或液压泵。利用流体压力发生器70的优点在于,使用流体压力发生器70更加精确,并且能够实现更好的压力均匀性。
对软部48所施加的均匀压力导致柔性软部被压缩,直至软部48的底表面与多个半导体器件50和平面衬底52接触,如图4C所示。所述压力产生键合力,该键合力在键合期间施加于多个半导体器件50上。半导体器件50由此被键合于平面衬底52上。因此,该优选实施例在确保对各个软部48施加均匀压力的同时,有利于在键合过程期间在沿其长度具有不同高度的平面衬底52上使用该装置20,所以,在键合期间可以对所有半导体器件50施加均匀的键合力。离型膜54可以放置在密封板44的底部,以将半导体器件50与软部48物理分离,并将密封插件46与平面衬底52物理分离。在键合工艺完成后,离型膜54有助于密封板44与平面衬底52的分离。
压力传感器(图4中未示出)可操作地连接于密封板44,用于测量并监控由密封板44施加的压力。压力传感器可以被配置为当密封板44在第一位置与第二位置之间移动时,在整个键合过程中监控密封板44中的压力,直到完成半导体器件50的键合为止。这允许实时监控由密封板44施加或作用在密封板44上的压力,并且根据需要实时进行任意调整。压力传感器还可以用于测量并监控在每个活动区域施加的压力。压力传感器可以是任何合适的压力传感器,但优选为能够耐高温的压力传感器。
第一优选实施例的装置20还可以用于将半导体器件键合于呈单一晶圆或面板形式的衬底52。图5A至图5C是当密封板组件在不同位置之间移动以将半导体器件键合于一个或多个单一衬底52上时的侧视图。如图5A所示,键合期间,在将衬底52支撑在载体或平台80上的同时,已经对其进行分离并彼此隔开。每个单一衬底52固持一个或多个半导体器件50。平台80可以具有由台阶84限定的凹陷部分82。平台80的凹陷部分82适于容纳单一的衬底52。在第一位置(如图5A所示)处,密封板44与衬底52隔开。
图5B示出了第二位置,在该位置,密封板44已经竖直向下移动,直至密封板44的底侧与衬底52接触。在第二位置处,密封板44的底侧也可以接触台阶84,使得密封插件46同时接触平台80和平面衬底52。在台阶84处,单一衬底52的顶表面与平台80的顶表面基本上处于相同的高度,以使密封板44能够同时接触单一衬底52和平台80。在所示示例中,每个单一衬底52的高度大致相同。然而,与图4B所示的先前示例一样,本领域技术人员将理解,如果各个单一衬底52的高度不同,密封插件46也可以如前所述相对于彼此移位。在第二位置处,软部48在进行键合之前还没有接触支撑在单一衬底52上的半导体器件50。
接着,流体压力发生器70对隔膜42施加正压力。然后,隔膜42将均匀压力传递至密封板44和软部48上。对软部48所施加的均匀压力压缩柔性软部48,直至软部48与半导体器件50和单一衬底52接触,如图5C所示。所述压力使得在键合期间对半导体器件50施加键合力。半导体器件50由此被键合于单一衬底52上。
图6是根据本发明第二优选实施例的印模固持器组件130和密封板组件140的分解等距视图。第二优选实施例与第一优选实施例的不同之处在于,在第二优选实施例中,只有单个软部148,该软部148具有装配在密封板144的单个切口中的整体扁平本体。在本发明的第二优选实施例中,印模固持器组件130(其对于装置的操作是可选的)包括具有单个压印表面的印模132。印模132可具有上部132a和位于上部132a下方的下部132b。印模132的下部132b靠近密封板组件140。优选地,上部132a的表面积大于下部132b的表面积。这有利于提高对密封板组件140所施加的压力。
印模固持器组件130还包括印模固持器套筒134和印模固持器本体136。印模固持器套筒134具有插槽133,印模132的上部132a可在插槽133内移动。印模固持器本体136安装在印模固持器套筒134的下方,并且具有邻近印模132的下部132b的凹部135。
套环137位于印模132的上部132a的基部附近。印模132被配置为可在竖直方向上朝向或远离衬底移动。套环137确保印模132的运动被限制在凹部135内。在印模132竖直远离衬底移动期间,套环137的上端会接触印模固持器套筒134的底面,从而防止印模132进一步向上移动。当印模132朝着衬底向下移动时,套环137的下端137b会在接触印模固持器本体136的顶面时停止进一步移动。这会避免印模132朝着衬底进一步向下移动。
密封板组件140位于印模固持器组件130与衬底之间。密封板组件140包括密封板144。密封板144可具有开口147,设置该开口147的尺寸和形状以容纳单个软部148。密封板144可以由在压力下不可变形的任意合适的刚性硬质材料制成。软部148可以由任何柔软、易弯曲且可弹性变形的材料制成。优选地,软部148由耐热材料制成。软部148适于装配在密封板144的开口147内。隔膜142夹在印模固持器本体136与密封板144之间。隔膜142有弹性,并且隔膜142的弹性使得压力能够均匀地传递至密封板144和软部148。当对隔膜142施加压力时,软部148对所有半导体器件施加基本相同的压力。
图7A至图7C是当密封板组件在不同位置之间移动以键合支撑在多个单一衬底152上的半导体器件150时的侧视图。如图7A所示,单一衬底152已经被分离并支撑在载体或平台180上。每个单一衬底152固持一个或多个半导体器件150。平台180中可以具有凹陷部分182,并且适于容纳多个单一衬底152。密封板144和软部148与单一衬底152隔开(如图7A所示)。单一衬底152可通过固定在单一衬底152上的固持板156定位在平台180上,其中单一衬底152通过形成于固持板156上的通孔暴露。固持板156放置在单一衬底152顶部的平台180的凹陷部分182中,并且将每个单一衬底152牢固地支撑并固定在平台180上的适当位置。
图7B示出了第二位置,在该位置,密封板144已经竖直向下移动,直至密封板144的底侧与固持板156接触。接着,流体压力发生器170对隔膜142施加正压力。然后,隔膜142将压力均匀地传递至密封板144的软部148,其中软部148包括整体扁平本体。软部148的整体扁平本体容纳于密封板144中形成的单个切口中。流体压力发生器170可以是气动致动器或液压泵。
对软部148所施加的均匀压力导致柔性软部148被压缩,直至软部148与所有半导体器件150、单一衬底152和固持板156接触,如图7C所示。所述压力使得在键合期间对半导体器件150施加键合力。半导体器件150由此被键合于单一衬底152上。离型膜154可以放置在密封板144和软部148的底部、半导体器件150和单一衬底152的上方。
在图7B所示的示例中,示出了密封板144在第二位置处与单一衬底152和固持板156均接触。然而,密封板144也可以如图8所示布置,在图8中密封板144仅与平台180接触。
图8是根据本发明第二优选实施例的包括压力传感器160的密封板组件的侧视图,该压力传感器160附接于密封板144。在如图8所的第二优选实施例中的密封板144的第二位置处,密封板144的刚性硬部仅与平台180接触,而不与单一衬底152接触。压力传感器160可以安装在密封板144中,用于测量并监控施加于密封板144或由密封板144施加的压力。当密封板144在第一位置与第二位置之间移动时,压力传感器160可以被配置为在整个键合工艺中监控密封板144中的压力,直至完成对半导体器件150的键合。这允许用户实时监控压力并根据需要对压力进行任意调整。压力传感器160可以是任何合适的压力传感器,但是应该能够耐高温。
图9是用于将半导体器件150键合于衬底152的装置的侧视图,该装置具有软质工具部分194和硬质工具部分192。在许多键合应用中,有时可能需要将堆叠式半导体器件键合在一起。这种半导体器件可以包括DTS芯片,或彼此叠置的多个管芯。在这种情况下,密封板144在其第二位置处接触衬底152和平台180。对软部148所施加的压力将依次均匀地施加在所有半导体器件150上。因此,密封板144的柔性软部148使得可以在单个步骤中将堆叠式半导体器件150键合或烧结在衬底152上。
在半导体器件150是不能通过软部148可靠地键合或烧结的厚管芯(例如NTC芯片)的情况下,将硬质工具部分192中的非柔性硬质工具190提供给本发明的装置是有利的。这种装置将包括软质工具部分194(包括密封板144和软部148)和硬质工具部分192(采用合适的硬质工具190)。这允许在固持有不同类型和厚度的半导体器件150的衬底上同时进行键合或烧结。
本发明的所述实施例相对于现有技术具有多个优点。例如,通过使用密封插件144和一个或多个软部148,用户现在能够指定特定区域以选择性地施加键合或烧结压力。此外,隔膜对密封板144和软部148的密封确保软部148被限制在密封插件146中所限定的凹部内。因此,软部148不会从密封板144与印模132之间形成的任意间隙中露出。同时,可以在所有半导体器件150上实现基本均匀的烧结压力。此外,所述实施例允许使用硬质工具部分192和软质工具部分194的组合,这对于需要使用这两种工具的应用是有益的。
尽管已经参照某些实施例相当详细地描述了本发明,但是其他实施例也是可能的。例如,还可以将衬底52、152支撑在密封板144上方,而不是如上所述支撑在密封板144下方,使得密封板144从第一位置向上移动至第二位置以接触衬底52、152和/或平台180。
因此,所附权利要求书的精神和范围不应局限于本文包含的实施例的描述。
Claims (20)
1.一种用于将至少一个半导体器件键合于支撑在平台上的衬底的装置,所述装置包括:
密封板,其包括刚性硬部和位于所述硬部之间的一个或多个柔性软部,所述密封板能够在第一位置与第二位置之间移动,所述第一位置与所述衬底隔开,在所述第二位置处,所述密封板的第一侧被配置为与所述衬底接触;
隔膜,其覆盖所述密封板的与所述第一侧相对的第二侧;以及
与所述隔膜流体连通的流体压力发生器,所述流体压力发生器操作性地用于对所述隔膜施加流体压力,所述流体压力进一步操作性地用于致动所述隔膜压缩所述一个或多个软部,从而使所述至少一个半导体器件与所述一个或多个软部接触,并在键合期间对所述至少一个半导体器件施加键合力。
2.根据权利要求1所述的装置,其中,在所述第二位置处,所述密封板的所述第一侧上的所述硬部与所述衬底接触。
3.根据权利要求1所述的装置,其中,在所述第二位置处,所述密封板的所述第一侧上的所述硬部与所述平台接触,所述密封板的所述第一侧上的所述软部与所述衬底接触。
4.根据权利要求1所述的装置,其中,所述刚性硬部由多个密封插件组成,每个密封插件包括一个切口,设置所述切口的尺寸和形状以容纳所述软部。
5.根据权利要求4所述的装置,还包括所述密封插件顶端处的台阶,所述台阶在所述切口中形成比在所述切口底端处更大的横截面积,用于当所述软部在键合期间被压缩时将所述软部固定在所述切口中。
6.根据权利要求4所述的装置,其中,当所述密封插件与所述衬底接触时,每个密封插件能够相对于另一个密封插件移位。
7.根据权利要求4所述的装置,其中,所述密封插件操作性用于同时接触所述平台和所述衬底。
8.根据权利要求1所述的装置,还包括一个或多个设置在所述密封板的所述第二侧上以接触所述隔膜的印模,所述印模或每个印模位于所述流体压力发生器与所述隔膜之间,用于将压力从所述流体压力发生器传递至所述一个或多个软部。
9.根据权利要求8所述的装置,其中,所述一个或多个印模还包括至少一个由所述流体压力发生器作用的第一部分以及操作性用于接触所述隔膜的第二部分,所述第一部分的表面积大于所述第二部分的表面积。
10.根据权利要求8所述的装置,其中,所述印模还包括从所述印模延伸的套环,所述套环被配置为接触位于插槽内的凹部的顶面和底面,所述印模能够沿着所述插槽滑动,所述凹部还限定了所述套环和所述印模相对于所述衬底的运动范围。
11.根据权利要求1所述的装置,其中,所述衬底包括在键合期间在所述平台上彼此隔开的多个单一衬底。
12.根据权利要求11所述的装置,其中,所述平台包括凹陷部分,所述单一衬底容纳在所述凹陷部分内,使得所述单一衬底的顶面基本上与所述平台的顶面处于相同的高度,并且所述密封板被配置为基本上同时接触所述单一衬底和所述平台。
13.根据权利要求12所述的装置,还包括固定在所述凹陷部分中的固持板,所述固持板包括用于支撑容纳在所述凹陷部分中的所述单一衬底的通孔。
14.根据权利要求1所述的装置,其中,所述密封板具有单个切口,设置所述单个切口的尺寸和形状以容纳单个整体扁平软部,以对所述衬底上的所有所述半导体器件施加均匀的键合力。
15.根据权利要求14所述的装置,其中,所述密封板的所述刚性硬部在键合期间仅接触所述平台,而所述整体扁平软部接触所述半导体器件和所述衬底。
16.根据权利要求1所述的装置,其中,所述软部包含于软质工具部分,并且所述装置还包括硬质工具部分,所述硬质工具部分包括非柔性硬质工具,用于对安装在所述衬底上的另外一个或多个半导体器件施加键合压力。
17.根据权利要求1所述的装置,还包括安装于所述密封板中的压力传感器,用于测量由所述密封板施加的压力。
18.根据权利要求1所述的装置,还包括离型膜,其位于所述密封板附近、所述至少一个半导体器件与所述一个或多个软部之间。
19.一种用于将至少一个半导体器件键合于支撑在平台上的衬底上的方法,所述方法包括以下步骤:
在所述衬底上设置所述至少一个半导体器件;
将包括刚性硬部和位于所述硬部之间的一个或多个柔性软部的密封板从第一位置移动至第二位置,所述第一位置与所述衬底隔开,在所述第二位置处,所述密封板的第一侧与所述衬底接触;以及
用流体压力发生器在隔膜上生成流体压力,所述隔膜覆盖所述密封板的与所述第一侧相对的第二侧,所述流体压力发生器与所述隔膜流体连通;
其中,对所述隔膜施加的所述流体压力致动所述隔膜压缩所述一个或多个软部,从而使所述至少一个半导体器件与所述一个或多个软部接触,并在键合期间对所述至少一个半导体器件施加键合力。
20.一种制造电子器件的方法,所述电子器件包括至少一个键合于衬底上的半导体器件,所述方法包括以下步骤:
在所述衬底上设置所述至少一个半导体器件;
将包括刚性硬部和位于所述硬部之间的一个或多个柔性软部的密封板从第一位置移动至第二位置,所述第一位置与所述衬底隔开,在所述第二位置处,所述密封板的第一侧与所述衬底接触;以及
用流体压力发生器在隔膜上生成流体压力,所述隔膜覆盖所述密封板的与所述第一侧相对的第二侧,所述流体压力发生器与所述隔膜流体连通;
其中,对所述隔膜施加的所述流体压力致动所述隔膜压缩所述一个或多个软部,从而使所述至少一个半导体器件与所述一个或多个软部接触,并在键合期间对所述至少一个半导体器件施加键合力。
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US20050277244A1 (en) | 2002-07-23 | 2005-12-15 | Norbert Galster | Method for fastening microtool components to objects |
JP2004119594A (ja) | 2002-09-25 | 2004-04-15 | Canon Inc | 一括接合装置 |
US6821813B2 (en) * | 2002-12-19 | 2004-11-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for bonding solder bumps to a substrate |
EP1845556A4 (en) | 2005-02-02 | 2010-02-10 | Sony Chem & Inf Device Corp | ATTACHING DEVICE FOR ELECTRICAL COMPONENTS |
JP4692101B2 (ja) | 2005-06-27 | 2011-06-01 | ソニー株式会社 | 部品接合方法 |
DE102005058794A1 (de) | 2005-12-09 | 2007-06-14 | Semikron Elektronik Gmbh & Co. Kg | Vorrichtung und getaktetes Verfahren zur Drucksinterverbindung |
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US8278142B2 (en) * | 2008-05-22 | 2012-10-02 | Texas Instruments Incorporated | Combined metallic bonding and molding for electronic assemblies including void-reduced underfill |
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