CN115274827A - 一种高压肖特基二极管及其制造方法 - Google Patents
一种高压肖特基二极管及其制造方法 Download PDFInfo
- Publication number
- CN115274827A CN115274827A CN202211039573.6A CN202211039573A CN115274827A CN 115274827 A CN115274827 A CN 115274827A CN 202211039573 A CN202211039573 A CN 202211039573A CN 115274827 A CN115274827 A CN 115274827A
- Authority
- CN
- China
- Prior art keywords
- layer
- schottky diode
- jbs
- type epitaxial
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 8
- 238000005566 electron beam evaporation Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 238000002294 plasma sputter deposition Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000001727 in vivo Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical group 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开了一种高压肖特基二极管,属于半导体技术领域。该高压肖特基二极管包括阴极金属、N+型基板、N‑型外延层和阳极金属,所述N‑型外延层的上表面侧面设有P+JBS区域,所述P+JBS区域的掺杂浓度比所述N‑外延层的掺杂浓度高,其中,所述N‑型外延层的上表面还设有P‑层。本发明的高压肖特基二极管在N型半导体层的表面加入了相对较薄的P‑层可提高JBS二极管的导通状态(正向偏置)性能,减小器件的反向漏电流。本发明的高压肖特基二极管在P+区两侧引入沟槽SiO2介质区,屏蔽肖特结的表面电场,降低肖特基接触区的表面电场强度,使器件在体内发生击穿,进一步减小器件的反向漏电流。
Description
技术领域
本发明属于半导体技术领域,涉及一种高压肖特基二极管及其制造方法。
背景技术
如图1所示,常规现有技术结势垒肖特基(JBS)二极管包括与半导体材料顶部表面的N型漂移区直接接触的顶部金属层。顶部金属层形成JBS二极管的阳极。深P+区域置于上表面的侧面。N+层从底部金属层垂直分离出N-外延层,底部金属层置于N+层下形成JBS二极管的阴极。其中深P+区掺杂浓度比N-外延层的掺杂浓度高。
图1中传统的JBS二极管结构是将PIN连接置于SBD的活性区域来降低反向偏置漏电流,但高掺杂P+区域的加入降低了肖特基二极管的接触面积,减少的接触面积导致正向偏置电流减少。同时当外加偏压逐渐增大时,P+欧姆接触区开始导通,器件开始由单极性导电模式向双极性导电模式转换,此时器件中的空穴参与导电,同时器件会产生一个电压回跳现象,即snapback效应,会严重影响器件的正向导通性能,从而导致器件的工作性能不稳定。
现有技术的JBS二极管将PIN连接置于SBD的活性区域来降低反向偏置漏电流,但高掺杂P+区域的加入降低了肖特基二极管的接触面积,减少的接触面积导致正向偏置电流减少。同时当外加偏压逐渐增大时,P+欧姆接触区开始导通,器件开始由单极性导电模式向双极性导电模式转换,此时器件中的空穴参与导电,器件会产生一个电压回跳现象,从而严重影响器件的正向导通性能。
发明内容
针对现有技术JBS二极管的缺点,本发明介绍了一种肖特基二极管的制造方法。本发明中肖特基二极管在半导体层的表面形成较薄的P-层,使P-层在零偏置时载流子完全耗尽,有利于提高JBS二极管的导通状态(正向偏置)性能,也可减少器件的反向泄漏。此外,于P型层两侧引入沟槽SiO2介质区,降低肖特基接触区的表面电场强度,进一步减小器件的反向漏电流。且在正向导通时,当器件工作在单极型导电模式下,沟槽SiO2介质区能有效抑制电压回跳现象,最终消除传统JBS器件带来的snapback效应,增强器件的工作稳定性。
本发明的第一方面在于公开一种高压肖特基二极管,包括阴极金属、N+型基板、N-型外延层和阳极金属,所述N-型外延层的上表面侧面设有P+JBS区域,所述P+JBS区域的掺杂浓度比所述N-外延层的掺杂浓度高,其中,所述N-型外延层的上表面还设有P-层。
在本发明的一些的实施方式中,所述P-层的厚度为100-150nm。
在本发明的一些的实施方式中,所述P-层的掺杂浓度为1×1015-3×1016atoms/cm3。
在本发明的一些的实施方式中,还包括位于所述P+JBS区域内侧的氧化层SiO2。
在本发明的一些的实施方式中,所述阳极金属(4)包括Ti层、TiN层和Al/Cu层,厚度为1-3μm;
所述阴极金属(5)包括Ti层、Ni层和Ag层,厚度为1-2μm。
在本发明的一些的实施方式中,所述P+JBS区域的横向宽度为2.0-3.0μm,垂直深度为0.4-0.8μm,掺杂浓度为1×1020-2×1020atoms/cm3。
本发明的第二方面在于公开一种第一方面所述的高压肖特基二极管的制造方法,包括以下步骤:
S01,选取N+型<100>晶向单晶衬底,外延生长N-型外延层;
S02,在所述N-型外延层形成沟槽,采用SiO2填充沟槽;
S03,在阳极端形成P-层;
S04,再形成重掺杂的P+JBS区;
S05,形成阴极金属和阳极金属。
在本发明的一些的实施方式中,S02中,采用光刻、干法刻蚀或者湿法刻蚀形成沟槽,采用化学气相沉积填充所述沟槽。
在本发明的一些的实施方式中,S03和S04中均采用离子注入分别形成所述P-层和所述P+JBS区。
在本发明的一些的实施方式中,S05中,采用等离子体溅射或电子束蒸发淀积形成所述阴极金属和阳极金属。
本发明的有益效果:
1.本发明的高压肖特基二极管在N型半导体层的表面加入了相对较薄的P-层可提高JBS二极管的导通状态(正向偏置)性能,减小器件的反向漏电流。
2.本发明的高压肖特基二极管在P+区两侧引入沟槽SiO2介质区,屏蔽肖特结的表面电场,降低肖特基接触区的表面电场强度,使器件在体内发生击穿,进一步减小器件的反向漏电流。
3.本发明的高压肖特基二极管引入沟槽SiO2介质区,有效抑制电压回跳现象,增强器件的工作稳定性。
4.本发明的高压肖特基二极管根据肖特基二极管的不同正向压降需求,可通过主工作区域阳极金属下的P-层厚度来辅助调整,灵活性更高。
附图说明
图1为传统JBS二极管的示意图。
图2是本发明一种实施方式的JBS二极管的示意图。
图3是图2的JBS二极管的制备流程图。
图4是本发明另一种实施方式的JBS二极管的示意图。
图5是传统JBS二极管与本发明实施方式的JBS二极管在正向导通时的输出特性曲线横向比较图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
若非特别指出,实施例和对比例为组分、组分含量、制备步骤、制备参数相同的平行试验。
本发明中肖特基二极管的制造方法包括以下步骤。
选取N+型<100>晶向单晶衬底(1),外延生长N-漂移区(2);
其次,通过光刻,刻蚀工艺(干法刻蚀或者湿法刻蚀)在N-外延层(2)形成一个沟槽,采用化学气相沉积进行SiO2淀积(6),填充沟槽;
在阳极端先进行离子注入,形成P-层(7);
在本发明中,P-层(7)的深度为100-150nm,掺杂浓度为1×1015-3×1016atoms/cm3;确保P-层(7)在零偏置下完全耗尽;
再进行离子注入,形成重掺杂的P+JBS区(3);
在本发明中,P+JBS区域(3)被布置在N-外延层(2)中,每个区域的横向宽度约为2.0-3.0μm,垂直深度为0.4-0.8μm,掺杂浓度为1×1020-2×1020atoms/cm3;
利用等离子体溅射或电子束蒸发淀积Ti、Ni或Ag金属,在衬底背面形成良好的欧姆接触,形成阴极金属(5),其厚度为0.1-2μm;利用等离子体溅射或电子束蒸发淀积金属Ti,接着在其表面淀积Ti/TiN层,最后利用等离子体溅射或电子束蒸发淀积金属Al/Cu层,形成阳极金属(4),其厚度为0.1-2μm;
实施例1:
如图2所示,P-层(7)的深度为150nm,掺杂浓度选择为2×1015atoms/cm3,确保P-层(7)在零偏置下完全耗尽。P+JBS区域(3)的横向宽度为2.0μm,垂直深度为0.5μm,掺杂浓度为1×1020atoms/cm3;
如图3所示,为实施例1二极管的主要工艺流程。其具体实现方法包括:①选取N+型<100>晶向单晶衬底,外延生长N-漂移区;②利用光刻、刻蚀工艺在N-外延层刻蚀形成一个沟槽,然后对刻蚀的沟槽进行SiO2淀积,填充沟槽;③在阳极端先进行离子注入,形成P-层;④再进行离子注入,形成重掺杂的P+JBS区;⑤利用等离子体溅射或电子束蒸发分别淀积及金属层,在衬底背面形成良好的欧姆接触,形成阴极金属;⑥利用等离子体溅射或电子束蒸发淀积金属接着在其表面淀积TiN层最后利用等离子体溅射或电子束蒸发淀积合金Al/Cu层形成厚度为2μm的阳极金属。
实施例2:
如图4所示,利用光刻工艺在顶部金属层与P+JBS区的界面处形成浅P-层,其余方面与图2所示的实施例1JBS二极管都是相同的,即N-外延层的顶面直接接触表层金属(4)形成肖特基接触。确保每个P-区域在零偏置下完全耗尽,这一结构对器件的正向偏置性能影响极小,且可以降低金属-半导体界面处的电场。
如图5所示,给出了传统JBS二极管(其结构如图1所示)、实施例1(其结构如图2所示)器件和实施例2(其结构如图4所示)器件在正向导通时的输出特性曲线横向比较图。根据实验结果,当正向电流密度为一定时,本发明所提出的实施例1和实施例2器件的开启电压与传统的JBS器件的开启电压相比,出现明显的降低。因此,本发明提出的JBS二极管具有更小的开启电压。同时,当器件开始由单极性导电模式向双极性导电模式转变时,传统的JBS器件的正向偏置电压为3.70V,回跳电压的差值△VSB为0.50V,存在明显的电压回跳现象(即Snapback效应),这种现象会严重影响器件的正向导通性能,导致器件的工作不稳定性。本发明所提出的实施例器件不存在Snapback效应,器件的正向导通性能十分稳定可靠,沟槽SiO2介质区能阻止电子直接流向肖特基接触区,使得电子在P+JBS区下面不断积累,当PIN结达到开启电压时,P+JBS区将会向N-外延层注入空穴,器件将工作在双极性导电模式下,从而有效抑制电压回跳现象。因此,本发明所提出的JBS器件不存在Snapback效应。
基于上述,本发明通过在半导体层的表面加入了相对较薄的P-层,从而大大降低表面电场,减小反向偏置漏电流,同时在p型层两侧引入SiO2介质层,可有效抑制电压回跳现象,增强器件的工作稳定性,也可有效降低反向偏置漏电流。
以上对本发明优选的具体实施方式和实施例作了详细说明,但是本发明并不限于上述实施方式和实施例,在本领域技术人员所具备的知识范围内,还可以在不脱离本发明构思的前提下作出各种变化。
Claims (10)
1.一种高压肖特基二极管,其特征在于,包括阴极金属(5)、N+型基板(1)、N-型外延层(2)和阳极金属(4),所述N-型外延层(2)的上表面侧面设有P+JBS区域(3a,3b),所述P+JBS区域(3a,3b)的掺杂浓度比所述N-外延层(2)的掺杂浓度高,其中,所述N-型外延层(2)的上表面还设有P-层(7)。
2.根据权利要求1所述的高压肖特基二极管,其特征在于,所述P-层(7)的厚度为100-150nm。
3.根据权利要求1或2所述的高压肖特基二极管,其特征在于,所述P-层(7)的掺杂浓度为1×1015-3×1016atoms/cm3。
4.根据权利要求1-3任一所述的高压肖特基二极管,其特征在于,还包括位于所述P+JBS区域(3a,3b)内侧的氧化层SiO2(6)。
5.根据权利要求1-3任一所述的高压肖特基二极管,其特征在于,所述阳极金属(4)包括Ti层、TiN层和Al/Cu层,厚度为1-3μm;
所述阴极金属(5)包括Ti层、Ni层和Ag层,厚度为1-2μm。
6.根据权利要求1-3任一所述的高压肖特基二极管,其特征在于,所述P+JBS区域(3a,3b)的横向宽度为2.0-3.0μm,垂直深度为0.4-0.8μm,掺杂浓度为1×1020-2×1020atoms/cm3。
7.一种根据权利要求1-6任一所述的高压肖特基二极管的制造方法,其特征在于,包括以下步骤:
S01,选取N+型<100>晶向单晶衬底(1),外延生长N-型外延层(2);
S02,在所述N-型外延层(2)形成沟槽,采用SiO2填充沟槽;
S03,在阳极端形成P-层(7);
S04,再形成重掺杂的P+JBS区(3);
S05,形成阴极金属(5)和阳极金属(4)。
8.根据权利要求7所述的高压肖特基二极管的制备方法,其特征在于,S02中,采用光刻、干法刻蚀或者湿法刻蚀形成沟槽,采用化学气相沉积填充所述沟槽。
9.根据权利要求7或8所述的高压肖特基二极管的制备方法,其特征在于,S03和S04中均采用离子注入分别形成所述P-层(7)和所述P+JBS区(3)。
10.根据权利要求7-9所述的高压肖特基二极管的制备方法,其特征在于,S05中,采用等离子体溅射或电子束蒸发淀积形成所述阴极金属(5)和阳极金属(4)。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202211039573.6A CN115274827A (zh) | 2022-08-29 | 2022-08-29 | 一种高压肖特基二极管及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202211039573.6A CN115274827A (zh) | 2022-08-29 | 2022-08-29 | 一种高压肖特基二极管及其制造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115274827A true CN115274827A (zh) | 2022-11-01 |
Family
ID=83755845
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202211039573.6A Pending CN115274827A (zh) | 2022-08-29 | 2022-08-29 | 一种高压肖特基二极管及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN115274827A (zh) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000252479A (ja) * | 1999-03-01 | 2000-09-14 | Fuji Electric Co Ltd | ショットキーバリアダイオードおよびその製造方法 |
US6303969B1 (en) * | 1998-05-01 | 2001-10-16 | Allen Tan | Schottky diode with dielectric trench |
CN111668824A (zh) * | 2019-03-05 | 2020-09-15 | 意法半导体股份有限公司 | 过电压保护设备 |
CN112242449A (zh) * | 2020-10-19 | 2021-01-19 | 重庆邮电大学 | 一种基于SiC衬底沟槽型MPS二极管元胞结构 |
US20220059708A1 (en) * | 2020-02-19 | 2022-02-24 | Semiq Incorporated | Counter-Doped Silicon Carbide Schottky Barrier Diode |
-
2022
- 2022-08-29 CN CN202211039573.6A patent/CN115274827A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6303969B1 (en) * | 1998-05-01 | 2001-10-16 | Allen Tan | Schottky diode with dielectric trench |
JP2000252479A (ja) * | 1999-03-01 | 2000-09-14 | Fuji Electric Co Ltd | ショットキーバリアダイオードおよびその製造方法 |
CN111668824A (zh) * | 2019-03-05 | 2020-09-15 | 意法半导体股份有限公司 | 过电压保护设备 |
US20220059708A1 (en) * | 2020-02-19 | 2022-02-24 | Semiq Incorporated | Counter-Doped Silicon Carbide Schottky Barrier Diode |
CN112242449A (zh) * | 2020-10-19 | 2021-01-19 | 重庆邮电大学 | 一种基于SiC衬底沟槽型MPS二极管元胞结构 |
Non-Patent Citations (2)
Title |
---|
松波弘之等编著: "《碳化硅半导体技术与应用 原书第2版》", 31 July 2022, 机械工业出版社, pages: 253 - 254 * |
高远等编著: "《碳化硅功率器件 特性、测试和应用技术》", 31 July 2021, 机械工业出版社, pages: 4 - 5 * |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8258032B2 (en) | Power semiconductor devices and methods for manufacturing the same | |
US7605441B2 (en) | Semiconductor device | |
US5241195A (en) | Merged P-I-N/Schottky power rectifier having extended P-I-N junction | |
JP6104575B2 (ja) | 半導体装置 | |
US20150270369A1 (en) | Method of Manufacturing an Insulated Gate Bipolar Transistor with Mesa Sections Between Cell Trench Structures | |
US8878327B2 (en) | Schottky barrier device having a plurality of double-recessed trenches | |
TWI521693B (zh) | 蕭基能障二極體及其製造方法 | |
KR100514398B1 (ko) | 실리콘 카바이드 전계제어 바이폴라 스위치 | |
US9929285B2 (en) | Super-junction schottky diode | |
CN106876256B (zh) | SiC双槽UMOSFET器件及其制备方法 | |
US20160197201A1 (en) | Power semiconductor devices having superjunction structures with implanted sidewalls and methods of fabricating such devices | |
US20240063311A1 (en) | Gan-based trench metal oxide schottky barrier diode and preparation method therefor | |
CN211017091U (zh) | 一种垂直型GaN基凹槽结势垒肖特基二极管 | |
CN113782587A (zh) | 一种具有屏蔽环结构的垂直型ⅲ族氮化物功率半导体器件及其制备方法 | |
CN110931571A (zh) | 一种垂直型GaN基凹槽结势垒肖特基二极管及其制作方法 | |
CN207947287U (zh) | 一种碳化硅肖特基二极管 | |
CN115274827A (zh) | 一种高压肖特基二极管及其制造方法 | |
CN116053325A (zh) | 一种高电阻场板屏蔽栅沟槽型场效应管器件及制造方法 | |
CN110534582B (zh) | 一种具有复合结构的快恢复二极管及其制造方法 | |
JP3357793B2 (ja) | 半導体装置及びその製造方法 | |
CN111799337A (zh) | 一种SiC JBS二极管器件及其制备方法 | |
CN108461549A (zh) | 一种碳化硅二极管器件及其制备方法 | |
CN113363330B (zh) | 一种肖特基半导体器件及其制作方法 | |
CN112466926A (zh) | 肖特基二极管及其制备方法 | |
JPH05110062A (ja) | 整流用半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination |