CN115274467A - Chip packaging method and packaging mechanism - Google Patents

Chip packaging method and packaging mechanism Download PDF

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Publication number
CN115274467A
CN115274467A CN202111333134.1A CN202111333134A CN115274467A CN 115274467 A CN115274467 A CN 115274467A CN 202111333134 A CN202111333134 A CN 202111333134A CN 115274467 A CN115274467 A CN 115274467A
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China
Prior art keywords
chip
conductive
conductive piece
layer
target metal
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CN202111333134.1A
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Chinese (zh)
Inventor
高宸山
李俞虹
宋关强
刘德波
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Sky Chip Interconnection Technology Co Ltd
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Sky Chip Interconnection Technology Co Ltd
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Priority to CN202111333134.1A priority Critical patent/CN115274467A/en
Publication of CN115274467A publication Critical patent/CN115274467A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The invention discloses a chip packaging method and a chip packaging mechanism, wherein the chip packaging method comprises the following steps: acquiring a preset carrier, and a first conductive piece, a second conductive piece and a third conductive piece which are attached to the same side of the preset carrier; fixing the chip to the first conductive piece and one side of the second conductive piece far away from the preset carrier, and fixing the target metal column to one side of the third conductive piece far away from the preset carrier; plastically packaging the chip and the target metal column to form a plastic packaging layer wrapping the chip and the target metal column, and removing the preset carrier; thinning the plastic packaging layer from the side of the plastic packaging layer far away from the first conductive piece until the chip and the target metal column are exposed; and carrying out whole-plate metallization on one side of the thinned plastic packaging layer exposed out of the chip so as to electrically connect the chip with the target metal column. Through the mode, the heat dissipation area of the packaging mechanism can be greatly increased, and the heat dissipation effect of the packaging mechanism is improved.

Description

Chip packaging method and packaging mechanism
Technical Field
The invention is applied to the technical field of processing chip packaging, in particular to a chip packaging method and a chip packaging mechanism.
Background
The chip packaging technology is used for mounting a housing for a semiconductor integrated circuit chip, plays a role in mounting, fixing, sealing, protecting the chip and enhancing the electrothermal performance, and is also a bridge for communicating an internal circuit of the chip with an external circuit.
With the rapid development of science and technology, the high-density requirements of various industries on chip packaging and related applications thereof are higher and higher. In practical applications, the requirement for the heat dissipation effect of the chip package is gradually increased while the chip package is developed in a high density.
However, the heat dissipation effect of the current packaged chip is poor, which affects the reliability of the chip.
Disclosure of Invention
The invention provides a chip packaging method and a chip packaging mechanism, which aim to solve the problem of poor heat dissipation effect of the packaging mechanism.
In order to solve the above technical problem, the present invention provides a chip packaging method, including: acquiring a preset carrier, and a first conductive piece, a second conductive piece and a third conductive piece which are attached to the same side of the preset carrier; fixing the chip to the first conductive piece and one side of the second conductive piece far away from the preset carrier, and fixing the target metal column to one side of the third conductive piece far away from the preset carrier; plastically packaging the chip and the target metal column to form a plastic packaging layer wrapping the chip and the target metal column, and removing the preset carrier; thinning the plastic packaging layer from one side of the plastic packaging layer away from the first conductive piece, the second conductive piece and the third conductive piece until the chip and the target metal column are exposed; and carrying out whole-plate metallization on one side of the thinned plastic packaging layer exposed out of the chip so as to electrically connect the chip with the target metal column.
Wherein, carry out the plastic envelope to chip and target metal post to form the plastic envelope layer of parcel chip and target metal post, and include after the step of getting rid of the carrier of predetermineeing: a supporting layer is arranged on one side of the plastic packaging layer, which is close to the first conductive piece, the second conductive piece and the third conductive piece in a whole-plate fit mode; drilling the supporting layer to expose the first conductive piece, the second conductive piece and the third conductive piece; the step of carrying out whole-plate metallization on one side of the thinned plastic packaging layer exposed chip so as to electrically connect the chip and the target metal column comprises the following steps: and simultaneously electroplating one side of the thinned plastic packaging layer, which is exposed to the chip, and one side of the supporting layer, which is far away from the plastic packaging layer, so as to form a metal layer on the whole plate on one side of the thinned plastic packaging layer, which is exposed to the chip, and metalize holes in the supporting layer.
Wherein, the step of drilling the supporting layer to expose the first conductive piece, the second conductive piece and the third conductive piece further comprises: drilling the supporting layer to obtain a first blind hole exposing the first conductive piece, a second blind hole exposing the second conductive piece and a third blind hole exposing the third conductive piece; sticking a dry film on the side of the supporting layer, which is far away from the chip, except for a preset position; the preset positions comprise corresponding positions of the first blind hole, the second blind hole and the third blind hole.
Wherein, one side and the supporting layer of the exposed chip of plastic-sealed layer after to the attenuate keep away from one side of plastic-sealed layer and electroplate simultaneously to the whole board of one side of the exposed chip of plastic-sealed layer after the attenuate forms the metal level and carries out the step that metallizes to the hole in the supporting layer and include: electroplating one side of the supporting layer, which is far away from the plastic packaging layer, until the first blind hole, the second blind hole and the third blind hole are metalized, correspondingly obtaining a first conductive hole, a second conductive hole and a third conductive hole, respectively preparing electroplated layers at preset positions, and leading out a source, a grid and a drain of the chip; wherein, each electroplated layer is correspondingly connected with the first blind hole, the second blind hole and the third blind hole respectively.
Wherein, the step of fixing the chip to the first conductive piece and the second conductive piece on the side far away from the preset carrier, and the step of fixing the target metal column to the third conductive piece on the side far away from the preset carrier comprises: performing reflow soldering on the chip to fix the chip to the first conductive piece and one side, far away from the preset carrier, of the second conductive piece; conducting conductive paste coating and reflow soldering are sequentially carried out on the target metal column, so that the target metal column is fixed to one side, away from the preset carrier, of the third conductive piece; wherein, the height of the target metal column is the same as the thickness of the chip.
Wherein, carry out the plastic envelope to chip and target metal post to form the plastic envelope layer of parcel chip and target metal post, and the step of getting rid of preset carrier includes: plastically packaging the chip and the target metal column by using an insulating material until the chip and a gap between the target metal column and a preset carrier are filled to obtain a plastic packaging layer wrapping the chip and the target metal column; and removing the preset carrier to expose one sides of the first conductive piece, the second conductive piece and the third conductive piece far away from the chip.
Wherein the thickness range of the preset carrier is more than 600 microns.
In order to solve the above technical problem, the present invention further provides a packaging mechanism, including: one side of the chip is connected with the first conductive piece and the second conductive piece; the same side of the target metal column is connected with a third conductive piece, wherein the first conductive piece, the second conductive piece and the third conductive piece are positioned on the same plane; the plastic packaging layer wraps the chip and the side surface of the target metal column and exposes one sides of the first conductive piece, the second conductive piece and the third conductive piece far away from the chip and one sides of the chip and the target metal column far away from the conductive pieces; and the metal layer is attached to one side of the chip and one side of the target metal column, which are far away from the conductive parts, so as to be electrically connected with the chip and the target metal column.
Wherein, packaging mechanism still includes: the first conductive hole, the second conductive hole, the third conductive hole and the support layer; the first conductive hole, the second conductive hole and the third conductive hole are positioned in the supporting layer and are respectively connected with one sides of the first conductive piece, the second conductive piece and the third conductive piece, which are far away from the chip; and one sides of the first conductive holes, the second conductive holes and the third conductive holes, which are far away from the corresponding conductive pieces, are correspondingly connected with the electroplated layers on one sides of the supporting layers, which are far away from the chip.
Wherein, the thickness of the target metal column is the same as that of the chip.
The invention has the advantages that; different from the situation of the prior art, the chip packaging mechanism is characterized in that a preset carrier, a first conductive piece, a second conductive piece and a third conductive piece are obtained firstly, and then the chip is fixed to one side, far away from the preset carrier, of the first conductive piece and the second conductive piece, so that the flip fixing of the chip is completed, the fixing space of the chip is saved, and the miniaturization and the lightness of the whole packaging mechanism are realized; and then plastically packaging the chip and the target metal column to form a plastic packaging layer wrapping the chip and the target metal column, removing the preset carrier, thinning the plastic packaging layer from one side of the plastic packaging layer away from the first conductive piece, the second conductive piece and the third conductive piece until the chip and the target metal column are exposed, finally performing whole-plate metallization on one side of the thinned plastic packaging layer exposed to the chip, wherein the whole-plate metallization can be utilized to realize the electric connection between the chip and the target metal column, the heat dissipation area of the packaging structure can be increased, the heat dissipation effect of the packaging structure is improved, the reliability and the quality of the packaging structure are further improved, and the service life of the packaging structure is prolonged.
Drawings
FIG. 1 is a flow chart illustrating a method for packaging a chip according to an embodiment of the present invention;
FIG. 2 is a flow chart of another embodiment of a chip packaging method provided by the present invention;
FIG. 3 is a schematic structural diagram of one embodiment of a packaging mechanism after step S24 in the embodiment of FIG. 2;
fig. 4 is a schematic structural diagram of an embodiment of the packaging mechanism provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a chip packaging method according to an embodiment of the present invention.
Step S11: obtaining a preset carrier, and attaching a first conductive piece, a second conductive piece and a third conductive piece which are arranged on the same side of the preset carrier.
The method comprises the steps of obtaining a preset carrier, and attaching a first conductive piece, a second conductive piece and a third conductive piece which are arranged on the same side of the preset carrier. The first conductive piece, the second conductive piece and the third conductive piece are arranged at intervals respectively.
In a specific application scenario, a preset carrier can be obtained first, a copper foil is arranged on one side of the preset carrier in a fitting manner, and then the copper foil is subjected to local etching or depth control, so that positions corresponding to the first conductive piece, the second conductive piece and the third conductive piece on the copper foil are reserved, and the copper foils at other positions are removed. In another specific application scenario, a preset carrier may be obtained first, and copper deposition electroplating is performed on one side of the preset carrier based on corresponding positions of the first conductive piece, the second conductive piece, and the third conductive piece, so that the first conductive piece, the second conductive piece, and the third conductive piece are formed on one side of the preset carrier. The specific method for obtaining the predetermined carrier, the first conductive member, the second conductive member, and the third conductive member is not limited herein.
The predetermined carrier may include a high temperature resistant tape or other insulating adhesive. The first conductive member, the second conductive member and the third conductive member may include conductive materials such as copper foil, metal blocks or metal frames.
Step S12: and fixing the chip to the first conductive piece and one side of the second conductive piece far away from the preset carrier, and fixing the target metal column to one side of the third conductive piece far away from the preset carrier.
After the preset carrier and the first conductive piece, the second conductive piece and the third conductive piece which are arranged on the same side of the preset carrier in a fitting mode are obtained, the chip is fixed to one side, away from the preset carrier, of the first conductive piece and the second conductive piece, and the target metal column is fixed to one side, away from the preset carrier, of the third conductive piece.
Specifically, the same chip may be flip-chip mounted on the first conductive component and the second conductive component away from the predetermined carrier at the same time, that is, different bumps of the chip may be mounted on the first conductive component and the second conductive component away from the predetermined carrier. The chip is directly and fixedly connected with the conductive piece, the oversize caused by lead bonding connection can be avoided, and the miniaturization and the lightness of chip packaging are facilitated.
The target metal pillar may include a metal conductive pillar such as a copper pillar, a silver pillar, or a gold pillar, and the specific material thereof is not limited herein.
The number of the first conductive pieces, the second conductive pieces and the third conductive pieces on the same side of the preset carrier corresponds to the number of the chips. In a specific application scenario, when the chip package of this embodiment needs to package 2 chips, the number of the first conductive component, the second conductive component, and the third conductive component on the same side of the predetermined carrier may be 2 respectively, so as to correspond to each chip. In another specific application scenario, when the chip package of this embodiment needs to package 1 chip, the number of the first conductive component, the second conductive component, and the third conductive component on the same side of the preset carrier may be 1 respectively.
Step S13: and plastically packaging the chip and the target metal column to form a plastic packaging layer wrapping the chip and the target metal column, and removing the preset carrier.
After the fixing is finished, the chip and the target metal column are subjected to plastic package to form a plastic package layer wrapping the chip and the target metal column. The preset carrier can be used for supporting the first conductive piece, the second conductive piece and the third conductive piece so as to ensure the stability of the first conductive piece, the second conductive piece and the third conductive piece and ensure the smooth completion of the plastic packaging process.
And removing the preset carrier after plastic packaging is finished. When the preset carrier is removed, the side, originally attached to the preset carrier, of each of the first conductive piece, the second conductive piece and the third conductive piece is exposed to lead out a chip to form an electrode of the chip.
Step S14: and thinning the plastic packaging layer from one side of the plastic packaging layer far away from the first conductive piece, the second conductive piece and the third conductive piece until the chip and the target metal column are exposed.
And after plastic packaging is finished, thinning the plastic packaging layer from one side of the plastic packaging layer, which is far away from the first conductive piece, the second conductive piece and the third conductive piece, until the chip and the target metal column are exposed.
In a specific application scenario, the plastic package layer can be thinned in a plate grinding, plate brushing or water jet cutting mode until the chip and the target metal column are exposed.
Step S15: and carrying out whole-plate metallization on one side of the thinned plastic packaging layer exposed out of the chip so as to electrically connect the chip with the target metal column.
And carrying out whole-plate metallization on one side of the thinned plastic packaging layer exposed out of the chip so as to electrically connect the chip with the target metal column.
In a specific application scenario, the whole plate electroplating may be performed on one side of the thinned plastic packaging layer exposed to the chip, so as to form a metal layer on the whole plate on one side of the thinned plastic packaging layer exposed to the chip, thereby electrically connecting the chip and the target metal column.
In another specific application scenario, the metal plate not smaller than the thinned plastic package layer may also be directly and fixedly connected to one side of the thinned plastic package layer exposed to the chip, so as to form a metal layer on the whole plate of one side of the thinned plastic package layer exposed to the chip, thereby electrically connecting the chip and the target metal column.
The chip is electrically connected with the target metal column through the flip chip on one side of the exposed chip of the plastic packaging layer, the connecting path between the chip and the target metal column is prolonged, and the connecting path is exposed, so that the heat dissipation area of the whole packaging mechanism can be increased, and the efficiency of the packaged heat dissipation mechanism is increased. In step S14, one side of the chip and one side of the target metal pillar are exposed, so that the metal layer obtained after metallization of the whole board can be electrically connected to the whole exposed side of the chip and the target metal pillar, and thus the contact area and the heat dissipation area between the chip and the target metal pillar are increased, and the stability and the reliability of the electrical connection between the chip and the target metal pillar are improved. And because this embodiment is all metallized to the whole side of plastic envelope layer, improved the external heat radiating area of packaging mechanism to a very big extent, and then can effectively promote packaging mechanism's radiating effect.
At this time, the chip can lead out electric signals through the first conductive piece and the second conductive piece which are directly connected to form partial electrodes, and lead out electric signals in sequence through the metal layer, the target metal column and the third conductive piece on one side of the chip to form other electrodes, so that the packaging of the chip is completed.
In a specific application scenario, a gate of a chip may be formed by a first conductive member directly connected to the chip, a source of the chip may be formed by a second conductive member directly connected to the chip, and a drain of the chip may be formed by a metal layer on one side of the chip, a target metal pillar, and a third conductive member sequentially connected to each other. The specific positions among the gate, the source and the drain of the chip may be set based on actual requirements, which is not limited herein.
By the method, the chip packaging method of the embodiment acquires the preset carrier, the first conductive piece, the second conductive piece and the third conductive piece, fixes the chip to one side of the first conductive piece and the second conductive piece away from the preset carrier, and fixes the target metal column to one side of the third conductive piece away from the preset carrier, so that the flip-chip fixation of the chip is completed, the fixing space of the chip is saved, and the miniaturization and the lightness of the whole packaging mechanism are realized; and then plastically packaging the chip and the target metal column to form a plastic packaging layer wrapping the chip and the target metal column, removing the preset carrier, thinning the plastic packaging layer from one side of the plastic packaging layer away from the first conductive piece, the second conductive piece and the third conductive piece until the chip and the target metal column are exposed, finally performing whole-plate metallization on one side of the thinned plastic packaging layer exposed to the chip, wherein the whole-plate metallization can be utilized to realize the electric connection between the chip and the target metal column, the heat dissipation area of the chip can be increased, the heat dissipation area of the packaging structure is increased, the heat dissipation effect of the packaging structure is improved, the reliability and the quality of the packaging structure are improved, and the service life of the packaging structure is prolonged. In addition, the electrode is led out by adopting a mode of connecting the target metal column, so that the time for copper deposition and electroplating can be greatly reduced, the surge current resistance of the circuit of the packaging mechanism is improved, and the quality of the packaging mechanism is improved. The target metal column for leading out the chip electrode and the chip are arranged on the same layer, so that the size of the packaging mechanism can be further reduced, and the miniaturization and the lightness of chip packaging are realized.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a chip packaging method according to another embodiment of the present invention.
Step S21: obtaining a preset carrier, and attaching a first conductive piece, a second conductive piece and a third conductive piece which are arranged on the same side of the preset carrier.
The method comprises the steps of obtaining a preset carrier, and attaching a first conductive piece, a second conductive piece and a third conductive piece which are arranged on the same side of the preset carrier. The first conductive piece, the second conductive piece and the third conductive piece are arranged at intervals respectively.
The preset carrier of the embodiment comprises a high-temperature-resistant adhesive tape so as to avoid the influence of overhigh reflux temperature on the preset carrier in the subsequent chip welding process. The high temperature resistant range of the adhesive tape can be above 200 ℃, for example: 200 degrees celsius, 260 degrees celsius, 310 degrees celsius, 420 degrees celsius, 500 degrees celsius, etc., which may be specifically set based on actual conditions, and are not limited herein. The thickness range of the preset carrier can be more than 600 microns so as to enhance the strength of the preset carrier and avoid the influence on the preset carrier caused by overhigh reflux temperature. Specifically, the thickness may be 600 micrometers, 700 micrometers, 1000 micrometers, 2000 micrometers, 3000 micrometers, 10000 micrometers, or the like, and may be set based on actual conditions, which is not limited herein.
In a specific application scenario, when the predetermined carrier is an adhesive tape, the first conductive component, the second conductive component, and the third conductive component may be fixed to the predetermined carrier by adhesive. The specific method for obtaining the preset carrier, the first conductive device, the second conductive device, and the third conductive device is the same as step S11 in the foregoing embodiment, and please refer to the foregoing, which is not described herein again.
Step S22: performing reflow soldering on the chip to fix the chip to the first conductive piece and one side, far away from the preset carrier, of the second conductive piece; and sequentially carrying out conductive paste coating and reflow soldering on the target metal column so as to fix the target metal column to one side, far away from the preset carrier, of the third conductive piece.
And carrying out reflow soldering on the chip so as to solder and fix the chip to the first conductive piece and one side of the second conductive piece, which is far away from the preset carrier. Specifically, different welding points of the chip may be respectively welded and fixed to the first conductive member and the second conductive member on the side away from the predetermined carrier, so as to lead out electrical signals of the chip through the first conductive member and the second conductive member to form electrodes. In a specific application scenario, the Chip may be Flip-Chip soldered and fixed to the first conductive member and a side of the second conductive member away from the predetermined carrier by a Flip-Chip Flip process.
And sequentially carrying out conductive paste coating and reflow soldering on the target metal column so as to fix the target metal column to one side of the third conductive piece far away from the preset carrier, and leading out electric signals of the chip through the target metal column and the third conductive piece to form an electrode. The conductive paste comprises at least one or more of tin paste, nano copper paste, silver paste, copper paste and other conductive pastes.
Wherein, the height of the target metal column is the same as the thickness of the chip. Therefore, when the plastic packaging layer is thinned based on the position of the chip and the target metal column, the thinning process can be simplified, the thinning difficulty is reduced, and the yield of the packaging mechanism is improved.
In addition, in the step, the chip and the target metal column are arranged at the same layer and at the same height, and the accommodating space of the target metal column for leading out the chip electric signal and the accommodating space of the chip can be overlapped to a certain extent, so that the size of the packaging mechanism is reduced, and the miniaturization and the lightness of the packaging mechanism are facilitated.
Step S23: plastically packaging the chip and the target metal column by using an insulating material until the chip and a gap between the target metal column and a preset carrier are filled to obtain a plastic packaging layer wrapping the chip and the target metal column; and removing the preset carrier to expose one sides of the first conductive piece, the second conductive piece and the third conductive piece far away from the chip.
And plastically packaging the chip and the target metal column by using an insulating material until the chip and a gap between the target metal column and the preset carrier are filled to obtain a plastic packaging layer wrapping the chip and the target metal column. The insulating material may include a film material, a liquid epoxy, and other insulating substances.
And removing the preset carrier after plastic packaging is finished, wherein one sides of the first conductive piece, the second conductive piece and the third conductive piece are attached to the preset carrier during plastic packaging, and after the preset carrier is removed, one sides of the first conductive piece, the second conductive piece and the third conductive piece, which are attached to the preset carrier, are exposed for leading out the chip to form an electrode of the chip.
Step S24: and thinning the plastic packaging layer from one side of the plastic packaging layer far away from the first conductive piece, the second conductive piece and the third conductive piece until the chip and the target metal column are exposed.
And after plastic packaging is finished, thinning the plastic packaging layer from one side of the plastic packaging layer, which is far away from the first conductive piece, the second conductive piece and the third conductive piece, until the chip and the target metal column are exposed.
In this embodiment, since the height of the target metal pillar is the same as the thickness of the chip, after thinning, the exposed surfaces of the chip and the target metal pillar are located on the same plane.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of the packaging mechanism after step S24 in the embodiment of fig. 2. The schematic diagram is illustrated by taking the number of chips of the packaging mechanism as 1, and when there are a plurality of chips, the structure is similar to that of the embodiment, and details are not repeated here.
The packaging mechanism 100 of the present embodiment includes a first conductive member 101, a second conductive member 102, a third conductive member 103, a chip 104, a target metal pillar 105, and a molding layer 106.
The first conductive member 101, the second conductive member 102, and the third conductive member 103 are disposed on the same plane, wherein a chip 104 is disposed on one side of the first conductive member 101 and the second conductive member 102, and a target metal pillar 105 is disposed on the same side of the third conductive member 103. The chip 104 and the target metal pillar 105 are disposed in the same layer and have the same thickness.
The molding layer 106 wraps the chip 104 and the target metal pillar 105, and fills the gaps between the chip 104 and the target metal pillar 105 and the first, second, and third conductive members 101, 102, and 103. The molding layer 106 exposes the first conductive element 101 and the second conductive element 102 away from the chip 104, and exposes the third conductive element 103 away from the target metal pillar 105.
The molding compound layer 106 further exposes the chip 104 and the target metal pillar 105 on a side away from the first conductive member 101, the second conductive member 102, and the third conductive member 103.
Step S25: and (3) arranging a supporting layer on the whole plastic package layer close to the first conductive piece, the second conductive piece and the third conductive piece, and drilling holes in the supporting layer to expose the first conductive piece, the second conductive piece and the third conductive piece.
And a supporting layer is attached to the whole side, close to the first conductive piece, the second conductive piece and the third conductive piece, of the plastic packaging layer. Because the rigidity of the first conductive piece, the second conductive piece and the third conductive piece is not enough, the supporting layer is arranged on one side of the plastic packaging layer close to the first conductive piece, the second conductive piece and the third conductive piece in a whole-plate attaching mode, so that the structural rigidity of the first conductive piece, the second conductive piece, the third conductive piece and the whole packaging mechanism is improved by utilizing the rigidity of the supporting layer, and the stability and the reliability of the packaging mechanism are further improved.
The support layer may include a resin layer with glass fibers or other insulating layers with certain rigidity. In a specific application scenario, when the supporting layer is a resin layer with glass fibers, the supporting layer may be arranged on a side of the plastic package layer close to the first conductive component, the second conductive component, and the third conductive component by pressing, so as to fix the supporting layer on the side of the plastic package layer.
And after the supporting layer is attached, drilling the supporting layer to obtain a first blind hole exposing the first conductive piece, a second blind hole exposing the second conductive piece and a third blind hole exposing the third conductive piece. Specifically, during drilling, the supporting layer is drilled based on the positions of the first conductive piece, the second conductive piece and the third conductive piece, so that a first blind hole exposing the first conductive piece, a second blind hole exposing the second conductive piece and a second blind hole exposing the second conductive piece are obtained.
Then, a dry film is pasted on the side, far away from the chip, of the supporting layer except for the preset position; the preset positions comprise corresponding positions of the first blind hole, the second blind hole and the third blind hole. In a specific application scenario, the corresponding position of the first blind hole may be the first blind hole orifice and the area near the first blind hole orifice, the corresponding position of the second blind hole may be the second blind hole orifice and the area near the second blind hole orifice, and the corresponding position of the third blind hole may be the third blind hole orifice and the area near the third blind hole orifice. The size of the preset position is larger than the hole opening of each blind hole, so that the area of an electroplated layer after subsequent electroplating is improved, the electric connection area of the chip electrode is further improved, and the stability and the reliability of connection between the chip electrode and external equipment or a circuit are improved.
The dry film may include a plating resist, or the like. For preventing the dry film covered region from being plated.
Step S26: and simultaneously electroplating one side of the thinned plastic packaging layer, which is exposed to the chip, and one side of the supporting layer, which is far away from the plastic packaging layer, so as to form a metal layer on the whole plate on one side of the thinned plastic packaging layer, which is exposed to the chip, and metalize holes in the supporting layer.
And simultaneously electroplating one side of the thinned plastic packaging layer, which is exposed to the chip, and one side of the supporting layer, which is far away from the plastic packaging layer, so as to form a metal layer on the whole plate on one side of the thinned plastic packaging layer, which is exposed to the chip, and metalize holes in the supporting layer. Because the two opposite surfaces of the packaging mechanism need to be metallized, the two surfaces of the packaging mechanism are metallized by electroplating at the same time, so that the preparation steps can be reduced, the capacity consumption can be reduced, and the preparation efficiency of the packaging mechanism can be improved.
Specifically, when the whole plate of one side of the thinned plastic packaging layer exposed chip is electroplated, a metal layer is formed on the whole plate of one side of the thinned plastic packaging layer exposed chip so as to electrically connect the chip and the target metal column. When one side of the support layer, which is far away from the plastic package layer, is electroplated until the first blind hole, the second blind hole and the third blind hole are metalized, the first conductive hole, the second conductive hole and the third conductive hole are correspondingly obtained, and the first electroplated layer, the second electroplated layer and the third electroplated layer are respectively prepared at preset positions, so that a source electrode, a grid electrode and a drain electrode of the chip are led out. Wherein, each electroplated layer is correspondingly connected with the first blind hole, the second blind hole and the third blind hole respectively.
At this time, the chip may form a gate through the first metal layer, the first extension metal pillar, and the first plating layer, a source through the second metal layer, the second extension metal pillar, and the second plating layer, and a drain through the metal layer, the target metal pillar, the third conductive member, and the third plating layer. And the metal layer above the drain is directly connected with the drain, so that the contact resistance of the drain and the resistance of the whole packaging mechanism can be reduced.
Because the first blind hole, the second blind hole and the third blind hole with certain depth are required to be metalized on one side of the supporting layer of the packaging mechanism, after the electroplating is completed to the metallization of each blind hole, the metal layer on one side of the plastic packaging layer, which is far away from the supporting layer, can also have certain thickness, so that the rigidity of the metal layer is improved, the heat dissipation area of the metal layer is enlarged, and the heat dissipation effect of the packaging mechanism is further improved.
After electroplating, the area of each electroplated layer formed on the supporting layer is larger than that of each conductive hole, so that the heat dissipation of the packaging mechanism can be further increased while the stability of connection between the chip and other equipment and circuits is guaranteed, and the heat dissipation effect of the packaging mechanism is improved. Meanwhile, the electrodes of the chip are prolonged through the arrangement of the first conductive hole, the second conductive hole and the third conductive hole, so that the chip can be adapted to various application scenes and application sizes.
And after the electroplating is finished, removing the dry film to obtain the final packaging mechanism.
After the traditional chip is packaged, the source and drain two stages of the chip can be respectively led out to two sides of the chip, so that the volume of the packaged chip is larger, the grid electrode, the source stage and the drain stage of the packaged chip can be led out at the same side, the volume and the size of the packaged chip can be further reduced, and the miniaturization and the lightness of the packaged chip are realized.
Through the steps, the chip is fixed to the side, away from the preset carrier, of the first conductive piece and the second conductive piece by performing reflow soldering on the chip, so that the flip-chip fixation of the chip is completed, the fixing space of the chip is saved, and the miniaturization and the lightness of the whole packaging mechanism are realized; the electrodes of the chip are led out in a mode of connecting the target metal column, so that the time of copper deposition and electroplating is reduced, and the surge current resistance of the packaging mechanism is improved. And the conductive holes are correspondingly arranged on the sides, far away from the first supporting layer, of the first conductive piece, the second conductive piece and the third conductive piece respectively, the electrodes of the chip can be prolonged and fixed through the conductive holes, and the stability and the rigidity of the electrodes are improved. In addition, the supporting layer is respectively pressed on one side of the packaging mechanism, so that the rigidity and the stability of the whole packaging mechanism are improved by utilizing the rigidity of the supporting layer, the situations of poor contact and structural deformation caused by looseness of the packaging mechanism are reduced, and the service life of the packaging mechanism is prolonged. The embodiment also electroplates the side of the supporting layer which is far away from the chip after being pasted with the dry film and the side of the thinned plastic packaging layer which exposes the chip simultaneously, can realize double-sided metallization through simultaneous electroplating, can reduce preparation steps, reduce the production capacity consumption and improve the preparation efficiency of the packaging mechanism. And the metal layer and the electroplated layer which cover the whole plate outside the packaging mechanism are utilized, so that the electric connection is realized, the heat dissipation area of the packaging mechanism is increased to a great extent, the heat dissipation efficiency of the packaging mechanism is improved, and the packaging mechanism has multiple functions.
Referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment of a packaging mechanism provided in the present invention. The number of chips of the packaging mechanism is 1 for example, and when there are a plurality of chips, the structure is similar to that of this embodiment, and details are not repeated here.
The packaging mechanism 200 of the present embodiment includes a chip 204, a target metal pillar 205, a first conductive member 201, a second conductive member 202, a third conductive member 203, a molding layer 206, and a metal layer 207.
One side of the chip 204 is connected to the first conductive member 201 and the second conductive member 202, and the same side of the target metal pillar 205 is connected to the third conductive member 203, wherein the first conductive member 201, the second conductive member 202, and the third conductive member 203 are located on the same plane.
The molding layer 206 wraps the chip 204 and the target metal pillar 205 and exposes the first conductive member 201, the second conductive member 202 and the third conductive member 203 at a side away from the chip 204 and the target metal pillar 205. And the bare chip 204 and the target metal stud 205 are away from the sides of the conductive members.
The metal layer 207 is disposed on a side of the chip 204 and the target metal pillar 205 away from the conductive members, so as to electrically connect the chip 204 and the target metal pillar 205. That is, the entire surfaces of the chip 204 and the target metal pillar 205 close to the metal layer 207 are attached to the target metal pillar 205, so that the heat dissipation and conduction efficiency of the chip 204 and the target metal pillar 205 can be greatly improved, and the heat dissipation effect of the chip 204 and the target metal pillar 205 can be improved. Moreover, since the area of the metal layer 207 is not smaller than the area of the side of the entire plastic package layer 206 away from the conductive members, the external heat dissipation area and heat dissipation effect of the metal layer 207 can be greatly enlarged, and the heat dissipation efficiency of the entire packaging mechanism 200 is further improved.
The present embodiment may form one electrode of the chip 204 by the first conductive member 201, one electrode of the chip 204 by the second conductive member 202, and one electrode of the chip 204 by the metal layer 207, the target metal pillar 205, and the third conductive member 203 to complete the function setting of the chip 204.
Through the structure, the packaging mechanism of the embodiment saves the fixing space of the chip by fixing the chip on the first conductive piece and the second conductive piece in an inverted manner, and realizes the miniaturization and the lightness of the whole packaging mechanism. The chip of this embodiment passes through the metal level and connects target metal post, and rethread third electrically conductive draws forth the electrode, can utilize the structure of target metal post to reduce the time of heavy copper electroplating greatly to improve the ability of the surge current of packaging mechanism circuit, improve packaging mechanism's quality. In addition, the target metal column for leading out the chip electrode and the chip are arranged on the same layer, so that the size of the packaging mechanism can be further reduced, and the miniaturization and the lightness of chip packaging are realized. The metal layer that this embodiment can also utilize whole board to set up improves packaging structure's heat radiating area, improves packaging structure's radiating effect, and then promotes packaging structure's reliability and quality, extension packaging structure's life.
In other embodiments, the chip 204 and the target metal pillar 205 are in the same layer and have the same thickness, so that the accommodating space of the target metal pillar 205 for leading out the electrical signal of the chip 204 overlaps with the accommodating space of the chip 204 to a certain extent, thereby reducing the size of the packaging mechanism 200 and facilitating the miniaturization and the lightness of the packaging mechanism 200.
In other embodiments, the molding layer 206 wraps the chip 204 and the target metal pillar 205 and fills the gaps between the chip 204 and the target metal pillar 205 and the first, second, and third conductive members 201, 202, 203.
In other embodiments, the packaging mechanism 200 further comprises: a first conductive via 2011, a second conductive via 2021, a third conductive via 2031, and a support layer 208.
The first conductive via 2011, the second conductive via 2021, and the third conductive via 2031 are located in the support layer 208 and are connected to the first conductive member 201, the second conductive member 202, and the third conductive member 203 at a side away from the chip 204. And the sides of the first conductive via 2011, the second conductive via 2021, and the third conductive via 2031 away from the corresponding conductive members are correspondingly connected to the plating layers on the side of the supporting layer 208 away from the chip 204.
That is, the first conductive via 2011 is connected to the first conductive member 201, the second conductive via 2021 is connected to the second conductive member 202, and the third conductive via 2031 is connected to the third conductive member 203.
And the sides of the first conductive via 2011, the second conductive via 2021, and the third conductive via 2031 away from the corresponding conductive members are correspondingly connected to the corresponding first plating layer 2012, the second plating layer 2022, and the third plating layer 2032 on the side of the supporting layer 208 away from the chip 204. That is, the first conductive via 2011 is electrically connected to the first plating layer 2012, the second conductive via 2021 is electrically connected to the second plating layer 2022, and the third conductive via 2031 is electrically connected to the third plating layer 2032. That is, the chip 204 may form a gate of the chip 204 through the first conductive member 201, the first conductive via 2011 and the first plating layer 2012, the chip 204 may form a source of the chip 204 through the second conductive member 202, the second conductive via 2021 and the second plating layer 2022, and the chip 204 may form a drain of the chip 204 through the metal layer 207, the target metal pillar 205, the third conductive member 203, the third conductive via 2031 and the third plating layer 2032.
The supporting layer 208 is disposed on a side of the first conductive member 201, the second conductive member 202, and the third conductive member 203 away from the chip 204 and the target metal pillar 205, and the thicknesses of the first conductive hole 2011, the second conductive hole 2021, and the third conductive hole 2031 are the same as the thickness of the supporting layer 208, so that the first conductive hole 2011, the second conductive hole 2021, and the third conductive hole 2031 can be connected to the corresponding first plating layer 2012, the second plating layer 2022, and the third plating layer 2032. The arrangement of the first conductive via 2011, the second conductive via 2021 and the third conductive via 2031 can extend the electrode length of the chip 204, so that the chip can be adapted to various application environments and application sizes.
And one side of the molding compound layer 206 close to the first conductive member 201, the second conductive member 202 and the third conductive member 203 is attached with the support layer 208, so that the rigidity and stability of the whole packaging mechanism 200 are improved by using the support layer 208, and the reliability and quality of the packaging mechanism 200 are further improved.
Wherein. Because the metal layer 207 is disposed on the outermost layer of the packaging mechanism 200, in the working process of the chip 204, the metal layer 207 may be used for conducting signals and increasing the heat dissipation area of the packaging mechanism 200, especially the leakage stage, so as to improve the heat dissipation effect of the packaging mechanism 200, improve the reliability of the packaging mechanism 200, and prolong the service life of the packaging mechanism 200.
Moreover, the areas of the first plating layer 2012, the second plating layer 2022, and the third plating layer 2032 on the supporting layer are larger than the areas of the conductive holes, so that the heat dissipation of the packaging mechanism 200 can be further increased while the connection stability between the chip 204 and other devices and circuits is ensured, and the heat dissipation effect of the packaging mechanism 200 is improved.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. A method for packaging a chip, the method comprising:
acquiring a preset carrier, and a first conductive piece, a second conductive piece and a third conductive piece which are attached to the same side of the preset carrier;
fixing a chip to one side of the first conductive piece and the second conductive piece away from the preset carrier, and fixing a target metal column to one side of the third conductive piece away from the preset carrier;
plastically packaging the chip and the target metal column to form a plastic packaging layer wrapping the chip and the target metal column, and removing the preset carrier;
thinning the plastic packaging layer from one side of the plastic packaging layer, which is far away from the first conductive piece, the second conductive piece and the third conductive piece, until the chip and the target metal column are exposed;
and carrying out whole-plate metallization on one side of the thinned plastic packaging layer exposed out of the chip so as to electrically connect the chip with the target metal column.
2. The method for packaging a chip according to claim 1, wherein the step of plastically packaging the chip and the target metal pillar to form a plastic packaging layer wrapping the chip and the target metal pillar, and removing the predetermined carrier comprises:
a supporting layer is arranged on one side of the plastic packaging layer, which is close to the first conductive piece, the second conductive piece and the third conductive piece, in a way of being integrally attached to the plastic packaging layer;
drilling the supporting layer to expose the first conductive piece, the second conductive piece and the third conductive piece;
the step of exposing the plastic packaging layer after the thinning the one side of the chip is metallized by a whole plate so as to enable the chip to be electrically connected with the target metal column comprises the following steps:
the plastic-sealed layer after the attenuate is exposed one side of chip and the supporting layer is kept away from one side of plastic-sealed layer is electroplated simultaneously to the plastic-sealed layer after the attenuate is exposed one side whole board of chip forms the metal level and to carry out the metallization in the hole in the supporting layer.
3. The method for packaging a chip according to claim 2, wherein the step of drilling the supporting layer to expose the first, second and third conductive members further comprises:
drilling the supporting layer to obtain a first blind hole exposing the first conductive piece, a second blind hole exposing the second conductive piece and a third blind hole exposing the third conductive piece;
pasting a dry film on the side of the supporting layer, which is far away from the chip, except for a preset position; the preset positions comprise corresponding positions of the first blind hole, the second blind hole and the third blind hole.
4. The method for packaging the chip according to claim 3, wherein the step of simultaneously electroplating the thinned molding compound layer on the side exposing the chip and the side of the supporting layer away from the molding compound layer to form the metal layer on the side exposing the chip of the thinned molding compound layer and metalize the hole in the supporting layer comprises:
electroplating one side of the supporting layer, which is far away from the plastic package layer, until the first blind hole, the second blind hole and the third blind hole are metalized, correspondingly obtaining a first conductive hole, a second conductive hole and a third conductive hole, respectively preparing electroplated layers at preset positions, and leading out a source electrode, a grid electrode and a drain electrode of the chip;
and each electroplated layer is correspondingly connected with the first blind hole, the second blind hole and the third blind hole respectively.
5. The method for packaging a chip according to claim 1, wherein the steps of fixing the chip to the first conductive member and the second conductive member on the side away from the predetermined carrier, and fixing the target metal pillar to the third conductive member on the side away from the predetermined carrier comprise:
performing reflow soldering on the chip to fix the chip to the first conductive piece and the second conductive piece on the side away from the preset carrier;
conducting conductive paste coating and reflow soldering are sequentially conducted on the target metal column, so that the target metal column is fixed to one side, away from the preset carrier, of the third conductive piece;
wherein the height of the target metal pillar is the same as the thickness of the chip.
6. The method for packaging a chip according to claim 1, wherein the step of plastically packaging the chip and the target metal pillar to form a plastic packaging layer wrapping the chip and the target metal pillar, and the step of removing the predetermined carrier includes:
plastically packaging the chip and the target metal column by using an insulating material until the chip and a gap between the target metal column and the preset carrier are filled with the chip, so as to obtain a plastic packaging layer wrapping the chip and the target metal column;
and removing the preset carrier to expose one sides of the first conductive piece, the second conductive piece and the third conductive piece far away from the chip.
7. The method of claim 1, wherein the predetermined carrier has a thickness greater than 600 μm.
8. A packaging mechanism for packaging a chip, the packaging mechanism comprising:
one side of the chip is connected with the first conductive piece and the second conductive piece;
the same side of the target metal column is connected with a third conductive piece, wherein the first conductive piece, the second conductive piece and the third conductive piece are positioned on the same plane;
the plastic package layer wraps the side surfaces of the chip and the target metal column and exposes one sides of the first conductive piece, the second conductive piece and the third conductive piece, which are far away from the chip, and one sides of the chip and the target metal column, which are far away from the conductive pieces;
and the metal layer is attached to one side, away from the conductive pieces, of the chip and the target metal column so as to be electrically connected with the chip and the target metal column.
9. The packaging mechanism of claim 8, further comprising: the first conductive hole, the second conductive hole, the third conductive hole and the support layer;
the first conductive hole, the second conductive hole and the third conductive hole are positioned in the supporting layer and are respectively connected with one sides of the first conductive piece, the second conductive piece and the third conductive piece, which are far away from the chip;
and one sides of the first conductive holes, the second conductive holes and the third conductive holes, which are far away from the corresponding conductive pieces, are correspondingly connected with the electroplated layers on one sides of the supporting layers, which are far away from the chip.
10. The packaging mechanism of claim 8, wherein the target metal pillar is the same thickness as the chip.
CN202111333134.1A 2021-11-11 2021-11-11 Chip packaging method and packaging mechanism Pending CN115274467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111333134.1A CN115274467A (en) 2021-11-11 2021-11-11 Chip packaging method and packaging mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111333134.1A CN115274467A (en) 2021-11-11 2021-11-11 Chip packaging method and packaging mechanism

Publications (1)

Publication Number Publication Date
CN115274467A true CN115274467A (en) 2022-11-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111333134.1A Pending CN115274467A (en) 2021-11-11 2021-11-11 Chip packaging method and packaging mechanism

Country Status (1)

Country Link
CN (1) CN115274467A (en)

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