CN115265608A

CN115265608A - Capacitive sensor and manufacturing method thereof

Info

Publication number: CN115265608A
Application number: CN202110977233.7A
Authority: CN
Inventors: 李恭谨; 汪鹏辉; 秦培
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2022-11-01
Also published as: CN112985471B; WO2022227346A1; CN112985471A

Abstract

The application relates to the field of sensors, in particular to a capacitive sensor and a manufacturing method thereof. A capacitive sensor comprises a plurality of pixel units arranged side by side, wherein each pixel unit comprises a silicon substrate, a structural layer and a passivation layer; the structural layer is arranged on the upper surface of the silicon substrate and comprises a top metal layer and a dielectric layer; the dielectric layer is arranged below the top metal layer, and the passivation layer is arranged on the upper surface of the structural layer; one or more through holes are formed in the top metal layer, and the through holes are circular; the passivation layer is provided with one or more grooves, and the symmetry axis of the grooves is coincident with the symmetry axis of the through holes. The problem of chip failure caused by a damp and hot environment is solved by arranging the circular through hole in the top metal layer of the pixel unit.

Description

Capacitive sensor and manufacturing method thereof

The application date of the original application is 2021, 04 and 30, and the application number is 202110485091.2, and the invention name is 'a capacitive sensor and a manufacturing method thereof'.

Technical Field

The application relates to the field of sensors, in particular to a capacitive sensor and a manufacturing method thereof.

Background

In view of the advantages of low raw material and production cost of resin and efficient mass production, resin encapsulation technology represented by epoxy resin is the most important technical branch in the field of electronic encapsulation currently and in the future. However, the resin-based molding material and the inorganic silicon material-based wafer are two different materials having significantly different characteristics. Under the action of damp and hot environment or stress, plastic packaging delamination is easy to occur, so that the internal structure of the chip is damaged, and further the function of the component is completely or partially lost. Particularly, for a capacitive sensor with sensitive plastic package lamination, the plastic package lamination phenomenon of the capacitive sensor is likely to cause inaccuracy of capacitance measurement, even chip failure, so that the reliability of a product is reduced.

Disclosure of Invention

The embodiment of the application provides a capacitive sensor and a manufacturing method thereof, aiming at the problem of reliability reduction caused by plastic package layering of the capacitive sensor in the prior art.

A first aspect of embodiments of the present application provides a capacitive sensor comprising a plurality of pixel cells arranged side by side, the pixel cells comprising a silicon substrate, a structural layer and a passivation layer;

the structural layer is arranged on the upper surface of the silicon substrate and comprises a top metal layer and a dielectric layer;

the dielectric layer is arranged below the top metal layer, and the passivation layer is arranged on the upper surface of the structural layer;

one or more through holes are formed in the top metal layer, and the through holes are circular;

the passivation layer is provided with one or more grooves, and the symmetry axis of the grooves is coincident with the symmetry axis of the through holes.

According to the first aspect, in one possible implementation, the upper opening of the through hole is circular; the lower opening of the through hole is circular; the diameter of the upper opening of the through hole is larger than 2 μm.

According to the first aspect, in a possible implementation manner, the top metal layer is provided with a through hole; the diameter of the upper opening of the through hole is not less than 7.5 μm and not more than 9.5 μm, and the farthest distance between the edge of the through hole and the edge of the top metal layer is less than or equal to 35 μm.

According to the first aspect, in one possible implementation, the center of the via is no more than 6.9 μm from the center of the top metal layer.

According to the first aspect, in one possible implementation, the center of the via is 6.7 μm from the center of the top metal layer.

In a possible implementation form according to the first aspect, the via is disposed in a central position of the top metal layer.

According to the first aspect, in a possible implementation, the diameter of the upper opening of the through hole is 7.9 μm; the diameter of the lower opening of the through-hole was 7.5 μm.

According to the first aspect, in a possible implementation, the top metal layer is provided with four vias, the four vias are equidistant from the center of the top metal layer, and the upper openings of the vias have a diameter of 4.5 μm.

According to the first aspect, in a possible implementation manner, the metal layer structure further includes a capacitance detection circuit, the capacitance detection circuit is disposed below the top metal layer, and the through hole is disposed at a position not directly above the capacitance detection circuit.

According to the first aspect, in a possible implementation manner, the groove is arranged right above the through hole, and the area of the opening on the groove is larger than the area of the bottom surface of the groove.

According to the first aspect, in one possible implementation, the groove is provided inside the through hole, and the area of the opening on the groove is larger than the area of the bottom surface of the groove.

According to the first aspect, in one possible implementation manner, the groove is a U-shaped groove or a truncated cone-shaped groove, and the area of the upper bottom surface of the truncated cone-shaped groove is larger than the area of the lower bottom surface of the truncated cone-shaped groove.

According to the first aspect, in one possible implementation, the angle of the slope formed by the side faces of the groove decreases as the horizontal height increases.

According to the first aspect, in one possible implementation, the lower bottom surface of the groove forms an obtuse angle with the side surface of the groove.

In a possible implementation form according to the first aspect, the angle formed by the lower bottom surface of the groove and the side surface of the groove is greater than or equal to 100 degrees.

According to the first aspect, in one possible implementation, the angle formed by the lower bottom surface of the groove and the side surface of the groove is equal to 145 degrees.

According to the first aspect, in a possible implementation manner, the through hole is a cylindrical through hole or a truncated cone through hole;

the area of the upper bottom surface of the truncated cone-shaped through hole is larger than that of the lower bottom surface of the truncated cone-shaped through hole;

the side face of the truncated cone-shaped through hole has an inclination angle of 85 degrees.

In a possible implementation form according to the first aspect, the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, the silicon nitride layer being arranged above the silicon dioxide layer.

According to the first aspect, in a possible implementation, the thickness of the top metal layer is not less than 0.8 μm and not more than 0.9 μm; the top metal layer is an aluminum layer; the length of the top metal layer is greater than or equal to 35 μm; the width of the top metal layer is greater than or equal to 35 μm.

In a possible implementation form according to the first aspect, the thickness of the passivation layer on the upper surface of the top metal layer is greater than or equal to 2.85 μm.

According to the first aspect, in one possible implementation, the thickness of the passivation layer on the upper surface of the top metal layer is 3.15 μm; the thickness of the top metal layer was 0.9 μm.

According to the first aspect, in a possible implementation manner, the plastic package structure further comprises a plastic package layer; the plastic packaging layer is arranged on the upper surface of the passivation layer.

According to the first aspect, in one possible implementation, the side length of the pixel unit is 45 μm.

A second aspect of embodiments of the present application provides a method of manufacturing a capacitive sensor, for manufacturing a capacitive sensor as in any one of the first aspects, comprising:

a circular through hole is formed in a top metal layer of a pixel unit of the capacitive sensor;

forming a passivation layer on the upper surface of the structural layer of the capacitive sensor; the structural layer comprises a top metal layer and a dielectric layer, and the dielectric layer is arranged below the top metal layer.

According to the second aspect, in a possible implementation manner, before forming a circular through hole in a top metal layer of a pixel unit of a capacitive sensor, the method further includes:

depositing a top metal layer of a pixel unit of the capacitive sensor in a sputtering mode;

the pattern of circular vias is calibrated to be no more than 6.9 μm from the center of the top metal layer of the pixel cell.

According to the second aspect, in one possible implementation manner, the opening of the circular via hole in the top metal layer of the pixel unit of the capacitive sensor includes: and etching a circular through hole in the top metal layer of the pixel unit according to the pattern by using a reactive ion etching process.

According to the second aspect, in one possible implementation, the forming of the passivation layer on the upper surface of the structural layer of the capacitive sensor comprises: the passivation layer is deposited using a chemical vapor deposition process.

Compared with the prior art, the beneficial effects of the embodiment of the application lie in that: the reliability of the capacitive sensor is not improved by plastic package materials and a plastic package process, but by improving the structural design of a pixel unit of the capacitive sensor, one or more circular through holes are formed in a top metal layer of the capacitive sensor, so that the reliability problem of the capacitive sensor caused by plastic package layering is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic diagram of a chip package provided in an embodiment of the present application after removing a molding layer;

FIG. 2 is a cross-sectional view of a failed chip according to an embodiment of the present application;

FIG. 3 is a cross-sectional view of another exemplary embodiment of the present disclosure after a chip failure;

FIG. 4 is a cross-sectional view of a chip according to an embodiment of the present application;

FIG. 5 is a top view and a cross-sectional view of a sensing unit according to an embodiment of the present disclosure;

fig. 6 is a schematic perspective view of a sensing unit according to an embodiment of the present disclosure;

FIG. 7 is a cross-sectional view of a sensing unit according to an embodiment of the present application;

FIG. 8 is a cross-sectional view of yet another sensing unit provided by an embodiment of the present application;

fig. 9 is a flowchart of a method for manufacturing a capacitive sensor according to an embodiment of the present disclosure;

FIG. 10 is a flow chart of a method for fabricating a capacitive sensor according to an embodiment of the present disclosure;

fig. 11 is a flowchart illustrating a method for manufacturing a capacitive sensor according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram illustrating a cross-section of a wafer during various steps of a wafer fabrication process according to an embodiment of the present application;

FIG. 13 is a top view of a portion of a capacitive sensor including a plurality of pixel cells according to embodiments of the present application;

fig. 14 is a top view of a pixel unit provided with 4 rectangular through holes on a top metal layer of the pixel unit according to an embodiment of the present disclosure;

fig. 15 is a top view of a pixel unit provided with 4 circular through holes on a top metal layer of the pixel unit according to an embodiment of the present application;

fig. 16 is a top view of a pixel unit provided with 1 circular via hole in a top metal layer of the pixel unit according to an embodiment of the present disclosure;

fig. 17 is a maximum shear stress variation trend graph of the maximum shear stress at the upper and lower edges of the groove corresponding to the angle of the slope of the groove provided in the embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, some embodiments of the present application will be described in detail by way of example with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

The failure mechanism is analyzed, and the reason for plastic packaging material delamination under the damp and hot environment mainly has three aspects: firstly, epoxy Molding Compound (EMC) inevitably has a moisture absorption rate of 0.1% -0.2% in a hot and humid environment, and the adhesion of the Molding Compound to a bare chip (Die) is reduced by about one order of magnitude by the ingress of water vapor; secondly, the occurrence of plastic lamination is related to the Coefficient of Thermal Expansion (CTE) of the material, which is a basic physical property of the material, and as the temperature rises, the thermal vibration of the atoms inside the material is intensified, so that the average distance between adjacent atoms is increased, and finally, the macroscopic expansion of the material generates the stress causing lamination. The greater the coefficient of thermal expansion, the greater the degree to which the material stretches at elevated temperatures, i.e., the greater the degree of expansion; the situation is reversed when the temperature is lowered, and the description is omitted here. Meanwhile, the resin material swells obviously after absorbing moisture, the volume of the plastic package material is increased due to the fact that the resin material has a thermal expansion coefficient far larger than that of the inorganic silicon material, and the stress generated by the two expansions further deteriorates an adhesion interface between the plastic package layer and a Passivation layer (PA); in addition, moisture entering the plastic package structure is gasified at high temperature to bring extra stress, so that plastic package layering and even plastic package breakage are aggravated, and chip failure is easily caused.

Based on the above analysis, the occurrence or non-occurrence of plastic lamination actually depends on the competition between the adhesion of the plastic package interface and the internal stress of the plastic package body. Therefore, the plastic packaging layering is improved, and the plastic packaging interface adhesion force can be enhanced and the internal stress of a plastic packaging body can be reduced. In order to solve the problem of plastic packaging layering, an adhesion auxiliary agent can be added into the plastic packaging resin to directly enhance the adhesion of the plastic packaging material; in addition, organic resin with low moisture absorption rate or the amount of hydrophilic inorganic filler can be reduced, and the deterioration of the interface adhesion force caused by water vapor can be reduced by reducing the water absorption rate of the plastic packaging layer. As can be seen from these examples of improving the mold delamination, the problem of mold delamination can be improved by improving the material of the mold. However, the optimization of the adhesion, moisture absorption rate and expansion coefficient of the plastic package material is close to the limit due to the production process and material parameter specification.

In the process of packaging or using the chip, the situation of environmental temperature and humidity change is often encountered, and therefore, the risk of chip failure needs to be evaluated, namely failure analysis. For example, high and low temperature cycle tests may be performed, and after the high and low temperature cycle tests, the package structure may have defects such as delamination, warpage, or cracks. Based on the analysis of the failure cases related to the reliability of the chips in recent years, the initial position of the plastic packaging layer is found to have certain regularity.

In this embodiment, a failure region is located through a functional test, and a Focused Ion Beam (FIB) technology is used to analyze a chip, and it is found that after a high temperature and high Humidity condition such as 55 ℃/95% Relative Humidity (RH), plastic package layering almost entirely concentrates on a rectangular groove position on the surface of the chip in fig. 1, fig. 1 is a schematic diagram of a capacitive sensor chip after the plastic package layer is removed from the chip package, fig. 1 is a top view of a local capacitive sensor chip only, and includes two pixel units, a top metal layer of each pixel unit is provided with 4 square slotted structures, and FIB analysis is performed on the chip and an area near the rectangular groove is selected for observation, so that the schematic diagram of the plastic package layering phenomenon shown in fig. 2 and fig. 3 can be obtained. A passivation Layer 2 is arranged below the plastic packaging Layer 1, the passivation Layer 2 can be transparent, a Top-metal Layer (Top-metal Layer) 3 is arranged below the passivation Layer 2, and various fillers with different sizes and shapes are arranged in the plastic packaging Layer 1. As shown by the arrows in fig. 2 and 3, a significant gap exists between the molding layer 1 and the passivation layer 2. The scheme that figure 1 adopted sets up square groove at the top layer metal level of the pixel unit of chip, can discover through emulation atress condition, the middle part on four borders of square groove produces local stress concentration phenomenon easily, from the angle of adhesion, the difficult clearance of filth in the square groove, thereby the adhesion is lower in difficult packing of plastic-sealed material granule filler, consequently, from the angle of stress state and adhesion, it can not restrain the plastic-sealed layering phenomenon well to set up rectangular groove at the top layer metal level of the pixel unit of chip.

The top metal layer of the pixel unit of the capacitive sensor needs to be provided with a Through-hole (Through-hole) for releasing stress due to the size relationship, and the risk of plastic package delamination is further worsened by improper Through-hole design. Generally, wafer fabrication has a certain Design Rule (Design Rule), for example, for wafer fabrication processes of 0.18 μm and below, a trench structure is required to be arranged whenever a large-area continuous metal layer of 35 μm × 35 μm or more appears. A rectangular slot as shown in fig. 1 may be arranged, for example, in the top metal layer of the pixel cell. The rectangular slotted structure plays a role in stress buffering in a Chemical Mechanical Polishing (CMP) process after the deposition of the top metal layer, can effectively solve the planarization problem caused by the middle sinking of the over-wide metal, and is also beneficial to the control of the uniformity of the etching process in a region with large metal proportion. Such a grooved structure of a continuous bulk metal layer is unavoidable from the mechanical properties and process point of view.

Fig. 4 (a) is a schematic cross-sectional view of a capacitive sensor, the capacitive sensor includes a plurality of pixel units, each pixel unit includes a silicon substrate 4, a structural layer 5 disposed above the silicon substrate 4, and a passivation layer disposed on a surface of the structural layer, the structural layer 5 includes a top metal layer and various layers of dielectric and metal structures thereunder, it can be understood that the structural layer 5 includes a doped well fabricated on the silicon substrate 4 and various layers of metal and dielectric layers above and between the top metal layer, fig. 4 (b) is a partially enlarged schematic view of the structural layer 5, the structural layer 5 includes multiple layers of metal and dielectric layers, wherein the passivation layer 2 is disposed on an upper surface of the structural layer, the top metal layer 3 is provided with a circular via structure, and the passivation layer 2 can be formed by Chemical Vapor Deposition (CVD); fig. 4 (c) is a schematic diagram illustrating a groove structure of a passivation layer of a pixel unit, where a top metal layer 3 of the pixel unit is provided with a circular through hole, an upper surface of the structure layer is provided with a passivation layer 2, the passivation layer 2 is provided with a groove 4, and the groove is arranged right above the circular through hole. Referring to (c) of fig. 4, it can be understood that the step coverage of CVD is difficult to reach the ideal state of 100%, and thus, the process difficulty of forming the mesa-shaped groove in the passivation layer is large.

Based on the disclosure of the above embodiments, in the present embodiment, the groove 4 on the passivation layer is right above the through hole, and when the passivation layer is thin, the shape of the groove may be a U-shaped groove, and the U-shaped groove does not require a particularly high step coverage. In addition, referring to (c) of fig. 4, the side surface of the groove is more gentle as the level increases, that is, as the level increases, the angle of the slope formed by the side surface of the groove of the passivation layer decreases, for example, for the angle at the side surface AA of the groove shown in (c) of fig. 4 approaching 90 degrees, the angle at the side surface BB of the groove approaching a plane, and the angle at the side surface BB of the groove approaching 0 degree.

Based on the disclosure of the above embodiments, in the present embodiment, please refer to the schematic diagram of the pixel unit shown in fig. 5, wherein (a) in fig. 5 is a top view thereof, and (b) in fig. 5 is a cross-sectional view thereof, and refer to the top view of the top metal layer of the pixel unit shown in (a) in fig. 5, the top metal layer 33 of the pixel unit may be provided with a circular via 35, and an upper opening and a lower opening of the via are both circular. As shown in the cross-sectional view of the pixel unit in fig. 5 (b), the top metal layer 33 of the pixel unit may be provided with a circular through hole 35, in this embodiment, the circular through hole may be a cylindrical through hole or a truncated cone-shaped through hole, and fig. 5 (b) illustrates that the circular through hole 35 is a truncated cone-shaped through hole, and the area of the upper bottom surface of the truncated cone-shaped through hole 35 is greater than that of the lower bottom surface thereof, which is beneficial to process implementation. For example, the inclination angle of the side surface of the truncated cone-shaped through hole 35 may be 85 degrees, and the truncated cone-shaped through hole with the inclination angle of 85 degrees is more beneficial to the realization of the process and the cost saving. For a cylindrical via, the area of its upper bottom surface is equal to the area of its lower bottom surface. Referring to fig. 5 (b), the passivation layer 32 may be disposed on the upper surface of the top metal layer 33, in this embodiment, the passivation layer is disposed on the upper surface of the structural layer, the structural layer includes the top metal layer and the dielectric layer below the top metal layer, the passivation layer is not only disposed on the upper surface of the top metal layer, but also disposed in the through hole of the top metal layer. The passivation layer is provided with a groove 34, and the groove 34 is arranged right above the through hole 35, it can be understood that the groove 34 is axisymmetric to the through hole 35, and the groove 34 coincides with the symmetry axis of the through hole 35. In this embodiment, the through hole is a truncated cone-shaped through hole as shown in (b) of fig. 5, which is easier to be implemented in terms of process than a cylindrical through hole. Specifically, when the through hole is formed by ion etching, the longer the exposure time of the top metal layer is, the wider the lateral expansion distance is, and for the cylindrical through hole, it is difficult to realize the vertical of the side surface and the bottom surface of the cylindrical through hole in the process, and the cost of the cylindrical through hole is relatively high; in addition, compared with a cylindrical through hole, the circular truncated cone-shaped through hole is less prone to plastic package layering, and it can be understood that the area of the upper bottom surface of the circular truncated cone-shaped through hole is larger than that of the lower bottom surface of the circular truncated cone-shaped through hole, therefore, an angle formed between the side surface and the lower bottom surface of the circular truncated cone-shaped through hole is larger than 90 degrees, after a passivation layer is formed on a top metal layer with the circular truncated cone-shaped through hole, the angle formed between the lower bottom surface and the side surface of a groove of the passivation layer is more prone to being larger than 90 degrees, namely, the lower bottom surface and the side surface of the groove of the passivation layer are more gentle, and the plastic package layer is more beneficial to full contact of fillers and the passivation layer. According to the embodiment of the application, the occurrence probability of plastic package layering is reduced by adjusting the geometric characteristics of the through holes, the technical limitation and bottleneck of improving the reliability of a plastic package material are broken through, the plastic package interface stress is further improved, the filling uniformity of the plastic package material is improved, the improvement effect is particularly obvious in a damp and hot environment, and the reliability of a chip can be remarkably improved.

The capacitive sensor provided in the embodiment of the present application is composed of a plurality of Pixel units, and is described by taking a Pixel unit (Pixel) as an example, please refer to a schematic diagram of a Pixel unit shown in fig. 6, where a circular through hole 6 with a diameter phi greater than 2 μm is disposed on a top metal layer of the Pixel unit, when only one through hole is disposed on the top metal layer of the Pixel unit, the diameter phi may be set between 7.5 μm and 9.5 μm, and the through hole may be disposed at a center position of the top metal layer, and a distance from an edge of the through hole to a farthest boundary of the Pixel unit is less than or equal to 35 μm. As shown in (a) of fig. 5, the diameter of the circular via hole Φ may be set to any value of 7.5 μm to 9.5 μm, and for example, a circular via hole having a diameter of 7.5 μm or 7.8 μm may be directly provided on the top metal layer. The diameter of the upper opening of the circular through-hole in the present embodiment may be equal to the diameter of the lower opening, for example, a cylindrical through-hole, and both the diameter of the upper opening and the diameter of the lower opening of the circular through-hole are equal to 7.5 μm. In addition, the circular through hole in the embodiment may also be a truncated cone-shaped through hole, for example, the diameter of the upper opening of the truncated cone-shaped through hole is 7.9 μm, and the diameter of the lower opening of the truncated cone-shaped through hole is 7.5 μm, which is more beneficial to process implementation and can save cost.

For the plastic package layer, the resin plastic package material used for chip package generally consists of an epoxy resin matrix, silicon oxide, aluminum oxide particle filler and a small amount of various auxiliaries. The proportion of the particle filler can reach 80 percent generally, so that whether the particle filler can smoothly enter the groove area of the passivation layer has a crucial influence on the filling uniformity of the plastic package body.

Based on the statistics of the particle size of the filler of the special plastic packaging material for capacitor products provided by main epoxy resin plastic packaging material suppliers in the industry, the central value of the particle size distribution of the filler particles is 9 microns, the particle sizes of most of the filler particles are concentrated in a range of 6-10 microns, and the proportion of the particles with small particle sizes of about 3 microns is less than 20%. Based on the plastic package mold flow analysis, considering the limited mold flow distance in the plastic package process, filler particles with excessively large particle sizes cannot be filled into the grooves with smaller diameters of the passivation layers, the filling effect is poor, and even tiny gaps may be generated due to incomplete filling, so that the filler particles become the inducing factor of plastic package delamination or cracks. The filling nonuniformity can be clearly seen on the electron microscope photos for analyzing the regularity of the failure sample shown in fig. 2 and fig. 3, and particularly, it can be visually seen through fig. 3 that filler particles with an excessively large particle size cannot be filled into a smaller groove formed on the passivation layer, so that the diameter of the circular through hole is larger than or equal to 7.5 μm in the embodiment, the particle filler is conveniently filled into the small groove formed on the passivation layer, the filling of filler particles of about six percent can be ensured to be unaffected at least, and the filling effect of the plastic package material is greatly improved; in addition, the diameter of the circular through hole of the top metal layer is less than or equal to 9.5 μm, so as to avoid the phenomenon that the signal intensity of the capacitance sensor is easily influenced due to the fact that the through hole is too large, and a circuit structure which is possibly and easily interfered by the outside world and is arranged below the top metal layer in the structural layer, such as a capacitance detection circuit, can be avoided. This embodiment is through the diameter of adjusting circular through-hole, guarantees the reliability of chip on the one hand, thereby in addition, is favorable to the through-hole to set up the position and staggers each other the stability that increases the circuit with the position of the electric capacity detection circuitry of top layer metal level below.

Based on the disclosure of the above embodiment, in the present embodiment, as shown in (b) of fig. 5, the groove 34 formed on the passivation layer 32 is disposed directly above the through hole 35, and the bottom of the groove 34 forms an obtuse angle with the side surface of the groove, the obtuse angle being greater than or equal to 100 degrees, for example, the obtuse angle may be equal to 145 degrees. Or it can be understood that the groove 34 is in the form of a truncated cone, the sides of which form a ramp having an angle a of less than 80, for example, the angle of the ramp can be 45. As can be seen from fig. 5 (b), the diameter of the upper opening of the groove 34 is larger than the diameter of the bottom surface of the groove, i.e., the area of the upper bottom surface of the groove is larger than the area of the lower bottom surface of the groove.

Taking the capacitive sensor as an example of an aluminum process, the upper surface of the top metal layer may be a silicon dioxide layer or a silicon nitride layer, i.e., the passivation layer may be a silicon dioxide layer or a silicon nitride layer. In addition, the passivation layer can include a silicon dioxide layer and a silicon nitride layer, when the passivation layer includes the silicon dioxide layer and the silicon nitride layer, the insulating property of the capacitance sensor is good, and the water vapor blocking capacity is also strong, specifically, the silicon nitride layer is arranged on the surface of the silicon dioxide layer, the insulating property of the silicon nitride layer is good, and the water vapor blocking capacity is strong, but the silicon nitride layer is fragile and easy to damage, so that the silicon dioxide layer arranged below the silicon nitride layer can improve the toughness of the passivation layer, and is not easy to damage.

In this embodiment, the groove with a slope at a specific angle may be obtained by controlling the thicknesses of the top metal layer and the passivation layer, where a cross-sectional view obtained by FIB is illustrated as follows: referring to fig. 7, a partial cross-sectional view of a pixel unit formed by depositing a passivation layer with a thickness of 2.74 μm on a top metal layer with a thickness of 2.66 μm is shown in fig. 7, where L2=2.74 μm, L3=2.66 μm, a depth D1=3 μm of a groove of the passivation layer, and L1=1.2 μm of the passivation layer at an opening of the top metal layer. Fig. 8 shows a cross-sectional view of a portion of a pixel unit formed by depositing a passivation layer with a thickness of 2.86 μm on a top metal layer with a thickness of 0.73 μm, and referring to fig. 8, a thickness L1=2.86 μm of the passivation layer on the top surface of the top metal layer, a thickness L2=0.73 μm of the top metal layer, a depth D1=0.87 μm of a groove of the passivation layer, a thickness L3=2.2 μm of the passivation layer at an opening of the top metal layer, and an angle of a slope of the groove is α ≈ 45 degrees. The angle of the slope of the groove shown in fig. 7 near the bottom of the groove is significantly greater than 45 degrees, i.e., the groove of fig. 7 is much steeper than the groove of fig. 8. Comparing fig. 7 and fig. 8, it can be seen that decreasing the thickness of the top metal layer is beneficial to obtaining a smaller groove slope angle, increasing the thickness of the passivation layer is also beneficial to obtaining a smaller groove slope angle, and conversely, increasing the thickness of the top metal layer and decreasing the thickness of the passivation layer makes the groove slope steeper, and the principle is similar to that of natural snowflakes covering stair steps. In the partial cross-sectional view of the pixel cell shown in fig. 8, the thicknesses of the top metal layer and the passivation layer were 0.73 μm and 2.86 μm, respectively, as measured by scanning electron microscopy, and the slope angle was obtained to be about 45 °. In addition, the angles of the respective portions of the actual slopes vary depending on the step coverage characteristics of CVD itself, and are not strictly equal to 45 ° everywhere.

In this embodiment, the angle of the slope of the groove of the passivation layer is adjusted by controlling the thickness of the top metal layer and/or the thickness of the passivation layer. Specifically, the slope angle can be reduced by reducing the thickness of the top metal layer and increasing the thickness of the passivation layer. The smaller the angle on slope is, the easier this recess of filling is filled to the packing granule, and the adhesion of plastic envelope layer and passivation layer is bigger, is more difficult to appear the plastic envelope layering phenomenon, and in addition, the actual technological level of board should also be considered to the thickness of each layer sets up.

The scheme of the embodiment of the application can be applied to the capacitive sensor. For the capacitive sensor, the top metal layer plays a role of a capacitor plate, and sensing information is obtained through the size of the sensing capacitor of the target to be detected. The sensing function of the sensor is easily influenced by plastic package layering due to the sensing principle, and the unit sensing capacitance value of a pixel unit of the sensor can be obviously changed due to tiny layering and moisture and heat water vapor accumulation under a moist and heat environment, so that the device fails. The circular through holes are formed in the top metal layer of the pixel unit, so that the plastic package layering of the capacitive sensor can be effectively inhibited, and the reliability of a chip is remarkably improved.

Taking the pixel unit adopting the scheme as an example for explanation, as shown in fig. 6, a circular through hole is arranged at a position, close to the center, of the top of the pixel unit of the capacitive sensor in a cube shape, or a circular through hole is arranged at a position of the center of the top metal layer, and the through hole can be a hollow cylinder or a hollow inverted round table; the capacitive sensor is composed of hundreds or even thousands of pixel units which are periodically arranged along the XY direction, and each pixel unit can be provided with the circular through hole at a position close to the center. The circular through hole is formed in the middle of the top metal layer of each pixel unit of the capacitive sensor, so that the interfacial stress between the wafer and the plastic package material in a damp and hot environment can be effectively reduced, the plastic package material can be effectively and uniformly filled into the groove of the passivation layer, and the occurrence of plastic package layering can be effectively inhibited.

The structure for forming the through hole in the top metal layer of the pixel unit is suitable for a conventional aluminum process of a capacitive sensor. The top metal layer is provided with one or more circular through holes, so that the interfacial stress between the wafer and the plastic package material in a damp and hot environment can be effectively reduced, the plastic package material can be effectively and uniformly filled, and the occurrence of plastic package layering is further inhibited. In addition, an angle target value of a slope of the groove of the passivation layer can be obtained by adjusting the thicknesses of the top metal layer and the passivation layer, for example, the slope of the groove can be set to be 45 degrees, so that the problem of plastic packaging delamination is solved.

Based on the disclosure of the foregoing embodiments, the present embodiment provides a method for manufacturing a capacitive sensor to form the capacitive sensor disclosed in the foregoing embodiments, and with reference to fig. 9, the method specifically includes the following steps:

s901: a circular through hole is formed in a top metal layer of a pixel unit of the capacitive sensor;

s902: forming a passivation layer on the upper surface of the structural layer of the capacitive sensor;

based on the disclosure of the above embodiments, in this embodiment, the structural layer includes a top metal layer and a dielectric layer, and the dielectric layer is disposed below the top metal layer. Referring to fig. 10, before step S901, the method may further include the steps of: s1001: depositing a top metal layer of a pixel unit of the capacitive sensor in a sputtering mode; the pattern of circular vias is calibrated to be no more than 6.9 μm from the center of the top metal layer of the pixel cell. In step S1001, a pattern of a circular via hole may be marked in the center of the top metal layer. In this embodiment, the top metal layer may be manufactured by a physical deposition process typified by sputtering, the shape of the through hole is defined to be circular on the top metal layer by a photolithography process, and the through hole is formed on the top metal layer by a reactive ion etching process. Steps S1002 and S1003 in fig. 10 are the same as or similar to steps S901 and S902 in the foregoing embodiment, and are not described again here.

Based on the disclosure of the above embodiments, in this embodiment, step S901 may include: and etching a circular through hole on the top metal layer of the pixel unit according to the pattern by a reactive ion etching process.

Based on the disclosure of the above embodiments, taking the capacitive sensor as an example, a method for manufacturing the capacitive sensor is further described, please refer to fig. 11, which includes the following steps:

s1101: manufacturing a CMOS (complementary metal oxide semiconductor) of the capacitance sensor, and structures of each layer of metal and dielectric layer;

step S1101 may complete a preamble process, which includes most processes of a front pass, a middle pass and a back pass of a wafer fabrication plant, and taking a capacitive sensor as an example, it can be understood as completing the fabrication of a Complementary Metal-Oxide-Semiconductor (CMOS) structure and each layer of Metal and dielectric layer structures of the capacitive sensor, and a cross-sectional view of a chip structure formed through the preamble process of step S1101 is shown in fig. 12 (a).

S1102: depositing a top metal layer in a sputtering mode;

in step S1102, the deposition of the top metal layer may be completed, for example, by a sputtering process, and after the polishing and cleaning processes are performed on the wafer processed by the previous layers in S1101, step S1102 is performed to deposit the top metal layer by sputtering, where the thickness of the top metal layer is not less than 0.8 μm and not more than 0.9 μm. For example, a 0.8 μm thick layer of metallic aluminum is deposited by sputtering, i.e., the top metal layer may be a 0.8 μm thick layer of aluminum, and additionally, a dimensional tolerance of 15% is allowed in view of the deposition process capability. The thickness of the top metal layer may also be 0.73 μm, for example. The cross-sectional view of the chip structure formed through step S1102 is shown in fig. 12 (b).

S1103: coating photoresist on the surface, and calibrating the position of the circular through hole on the surface of the top metal layer after deep ultraviolet exposure;

after step S1102, the wafer has completed metal deposition, and after cleaning, a photoresist is coated on the surface of the wafer, and then a series of photolithography processes such as pre-baking, deep ultraviolet exposure, post-baking, and developing are performed, and finally, the position of the circular through hole is defined on the upper surface of the top metal layer of the wafer, for example, a single circular pattern is defined at the center of the wafer, in this embodiment, the position of the circular through hole is calibrated to be used as an etching mask, and a cross-sectional view of the chip structure formed through step S1103 is shown in (c) in fig. 12.

S1104: etching a circular through hole on the top metal layer by a reactive ion etching process;

step S1104 may also be referred to as reactive ion etching, i.e. the lithographic pattern is transferred to the top metal layer by a reactive ion etching process. It can be understood that a circular through hole structure is etched in the top metal layer of the wafer, and in addition, other structures of the top metal can also be etched simultaneously through reactive ion etching. After the etching process is completed, a post-treatment and a cleaning process may be performed, and a cross-sectional view of the chip structure formed through step S1104 is shown in fig. 12 (d).

S1105: depositing a passivation layer on the surface of the wafer with the top metal layer;

step S1205 completes depositing the passivation layer, and a silicon dioxide layer and a silicon nitride layer may be deposited on the surface of the top metal layer by a CVD process, where the deposition thickness is, for example, over 2.85 μm, that is, the thickness of the passivation layer on the surface of the top metal layer may be greater than or equal to 2.85 μm, for example, the thickness of the passivation layer on the upper surface of the top metal layer may be set to 3.15 μm, the thickness of the top metal layer may be set to 0.9 μm, and a passivation layer with a specific thickness is deposited on the top metal layer with a specific thickness, so that the angle of the slope of the groove of the passivation layer is more gradual, and the plastic package delamination problem of the capacitive sensor is more significantly improved. The cross-sectional view of the chip structure formed through step S1105 is shown in fig. 12 (e).

S1106: carrying out routing and Pad windowing on the wafer;

step S1106 may complete subsequent processes after depositing the passivation layer, for example, a row of subsequent wafer processes such as wire bonding, electrode (Pad) windowing, and the cross-sectional view of the chip structure formed in step S1106 is shown in fig. 12 (f).

The shape of the via hole of the top metal layer of the completed pixel unit can be referred to as (a) in fig. 5, and the diameter of the via hole can be 7.8 μm. Referring to the top view of the capacitive sensor shown in fig. 13, a circular through hole is disposed at a position close to the center of the top metal layer of each pixel unit. If there is a circuit structure, such as a capacitor, a differential amplifier, etc., below the top metal layer, which is easily affected by the outside, and the capacitor includes a compensation capacitor, a feedback capacitor, etc., in order to make the via hole avoid the sensitive circuit structure, the circular via hole may be shifted by 0 μm to 6.9 μm based on the center position of the wafer to protect the capacitance detection circuit. For example, for a pixel cell with a side length of 50 μm, the center of the circular via of the top metal layer may be offset from the center of the pixel cell by less than 6.4 μm, and for a pixel cell with a side length of 45 μm, if the diameter of the circular via of the top metal layer is 7.5 μm, the center of the circular via may be offset by 6.7 μm based on the centered position of the pixel cell, and the distance from the edge of the circular via to the edge of the pixel cell may not exceed 35 μm. In this embodiment, the offset refers to an offset in the horizontal direction, i.e., the distance between the center of the via and the center of the top metal layer refers to the distance in the horizontal direction.

Based on the disclosure of the above embodiments, in this embodiment, a distance between a center of the through hole and a center of the top metal layer of the pixel unit is not greater than 6.9 μm, specifically, a distance between a center of the through hole and a center of the top metal layer may be 6.7 μm, and in this embodiment, the distance between the through hole and an edge of the pixel unit is adjusted to make a position of the through hole and a position of the capacitance detection circuit below the top metal layer staggered with each other, so as to increase stability of the circuit.

In this embodiment, the geometric parameters of the through holes are different based on the process, and the circular through holes of the top metal layer do not bring difficulties to the wafer manufacturing process.

By performing mechanical simulation on the plastic package interface, the stress distribution condition of the chip in a damp and hot environment can be obtained. Taking pixel units with three different structures as an example for comparison, the first structure is as shown in fig. 14, four rectangular through holes are arranged on the top metal layer of the pixel unit of the capacitive sensor, wherein the area of each rectangular through hole is 4 μm × 4 μm; in a second structure, as shown in fig. 15, four circular through holes are uniformly distributed in a top metal layer of a pixel unit of a capacitive sensor, wherein the diameter of each circular through hole is phi =4.5 μm, and the distance between each through hole and the center of the top metal layer is equal; in a third structure, as shown in fig. 16, a circular through hole is disposed in a top metal layer of a pixel unit of a capacitive sensor, and the diameter of the circular through hole is phi =9 μm. The stress condition of the three structures in a damp and hot environment can be analyzed through simulation.

After temperature rise or moisture absorption, the volume change of the resin plastic package material of the chip is far larger than that of the inorganic passivation layer material, so that shear stress is generated on a connecting interface of the plastic package layer and the passivation layer. When the shear stress exceeds the adhesion of the plastic package material to the passivation layer, plastic package delamination occurs. As can be obtained through mechanical simulation analysis, compared with the top metal layer structure with 4 rectangular through holes shown in fig. 14, the maximum shear stress in the vicinity of the through hole of the top metal layer structure with 4 circular through holes having the same area shown in fig. 15 is about 78% of the maximum shear stress of the structure shown in fig. 14, and the higher stress region of the structure shown in fig. 15 is significantly reduced; while the maximum shear stress of the top metal layer with a single large circular through hole in fig. 16 is about 45% of the maximum shear stress of the structure shown in fig. 14 in the vicinity of the through hole, the structure of fig. 15 and 16 has a significant effect of relieving the thermal wet stress. As can be seen from a comparison of the stress distributions corresponding to the structures of fig. 15 and 16, the larger the area of the circular through hole, the more the stress can be relieved. When the total area of the through holes is kept fixed, compared with the scheme that 4 small through holes are arranged on the top metal layer, the plastic package material has a better filling effect in the scheme that 1 large through hole is arranged on the top metal layer no matter the angle of the filling effect of the plastic package material is analyzed from the shearing stress borne by the top metal layer under the damp and hot environment.

From the angle analysis of the wafer process, for rectangular through holes and circular through holes with the same area, the packaging structure with the circular through holes arranged on the top metal layer is more favorable for the wafer process before plastic packaging, and particularly for the step of effectively cleaning the adhered dirt in the groove, the circular through hole structure is more convenient for cleaning the adhered dirt, so that the adhesive force of the plastic packaging layer is improved. It can be understood that the through hole with corners on the sides, such as the rectangular through hole, is structurally not beneficial to effectively cleaning corner dirt by a cleaning solution in a plastic packaging preorder process, and the round through hole avoids the corners of 90 degrees formed by the two sides, so that the wafer can be conveniently cleaned in a wafer process before plastic packaging.

For the grooves formed in the passivation layer, the grooves in the shape of the inverted truncated cone are beneficial to reducing the shear stress between the plastic packaging layer and the passivation layer, and the stress conditions of the grooves at different slope angles in a damp and hot environment can be verified through mechanical simulation analysis. With the upper opening area of the grooves of the same size and other modeling parameters, stress distribution of different schemes can be obtained by controlling the slope angle only by adjusting the area of the bottom of the groove, for example, the angles of the slopes of the grooves of the passivation layer in scheme 1, scheme 2, scheme 3, scheme 4 and scheme 5 are 90 degrees, 86.7 degrees, 83 degrees, 80.5 degrees and 77.4 degrees, respectively. The side face of the passivation layer in the scheme 1 is perpendicular to the top metal layer, stress concentration is obvious in the upper edge area of the groove structure, and the upper edge area, namely the area close to the plastic packaging layer, is a high-component risk area of plastic packaging layering in a damp and hot environment. The region of high shear stress is significantly reduced as the ramp angle of the recess is continuously reduced. When the slope angle is smaller than 80 degrees, the shear stress is obviously reduced, and the slope angle is further reduced, so that the distribution of the shear stress in the slope area tends to be consistent and is basically lower. Specifically, detailed data of the scheme 1, the scheme 2, the scheme 3, the scheme 4 and the scheme 5 are shown in table 1, where "Max" represents a maximum stress value, "Min" represents a minimum stress value, "P-upper opening" represents a stress value at a certain point at the upper opening, "P-bottom" represents a stress value at a certain point at the bottom surface, and further, referring to a maximum shear stress variation trend graph of the upper and lower edges of the groove shown in fig. 17, it can be seen from data in table 1 and fig. 4 that when the angle α is equal to 83 °, 80.5 ° or 77.4 °, the stress at the upper opening of the groove of the passivation layer is significantly reduced compared to when the angle α is equal to 86.7 ° or 90 °. Therefore, it can be understood that when the angle of the slope of the groove is less than or equal to 80 degrees, the stress in the hot and humid state is significantly reduced. The stress near the upper edge of the groove, namely the upper opening of the P-shape groove, is reduced along with the reduction of the angle, the stress near the lower edge of the groove, namely the bottom of the P-shape groove, is only slightly increased along with the reduction of the angle, and in brief, the more gradual the slope is, the closer the state without the groove is, the more uniform the stress distribution is. In the examples of the present application, the units of the data in table 1 and fig. 4 are dimensionless a.u, and are only used for comparing the variation trend of the stress.

Table 1: different slope angle stress comparison table

	Max	Min	P-upper opening	P-bottom
					Scheme one (alpha =90 degree)	0.00052432	4.8584e^(-7)	2.2911e^(-4)	1.0039e^(-4)
Scheme two (α =86.7 °)	0.00046375	4.0332e^(-7)	2.811e^(-4)	1.0206e^(-4)
					Scheme three (α =83 °)	0.00052178	4.8584e^(-7)	1.8021e^(-4)	1.0933e^(-4)
Scheme four (alpha =80.5 degree)	0.00052432	4.8584e^(-7)	1.7759e^(-4)	1.1939e^(-4)
					Scheme five (α =77.4 °)	0.00052204	4.8584e^(-7)	1.659e^(-4)	1.2883e^(-4)

The scheme that the top metal layer of the pixel unit is provided with the circular through hole can be applied to a capacitance sensor. For the top metal layer of the pixel unit of the wafer which plays a role of the capacitance sensing polar plate, the function of the capacitance sensor chip is basically not influenced by the circular through hole. Referring to the application scene of the capacitance fingerprint chip, the electrical signals of the sensing chip under different through holes are simulated, and the capacitance value simulation result is shown in table 2:

table 2: analysis table for influence of different through hole schemes of top metal layer on capacitance sensing function

Pixel notching condition	C_max(fF)	C_min(fF)	△C	C	△C/C
						4 square total area 36 mu m 2	0.848	0.369	0.480	0.609	78.8％
4 circular total area 72 mu m 2	0.845	0.367	0.478	0.606	78.9％
						2 circular total area 72 mu m 2	0.843	0.367	0.477	0.605	78.8％

In table C_max、C_minCapacitance values corresponding to fingerprint ridge and valley areas after fingers are pressed respectively, and delta C and C are respectively the difference value of the capacitance values of the fingerprint ridge and valley and the background capacitance value of the sensing chip, wherein the delta C and C influence the signal quantity after the fingers are pressed, and the ratio delta C/C influences the sensitivity of capacitance sensing. The Pixel notching condition "4 Square Total area 36 μm ^2" in Table 2 indicates that the top metal layer of the Pixel cell has 4 areas equalThe square through hole scheme, the total area of the 4 square through holes is 36 mu m ^2; the Pixel notching condition "4 circular total area 72 μm ^2" in Table 2 indicates that the top metal layer of the Pixel cell has a scheme with 4 circular through holes with equal area, and the total area of the 4 circular through holes is 72 μm ^2; the Pixel notching case "2 circular total area 72 μm 2" in Table 2 indicates a scheme where the top metal layer of the Pixel cell has 2 circular vias of equal area, the total area of the 2 circular vias being 72 μm 2. As can be seen from the data in table 1, changing the via shape or increasing the via area within a certain range generally does not affect the function of the capacitive sensor. The structure of the top metal layer with a single circular through hole does not influence the function of the capacitance sensor generally, and the area of the single circular through hole arranged on the top metal layer can be 64 mu m ^2.

The scheme that the circular through holes are formed in the top metal layer can effectively inhibit plastic package interface layering, reliability of the capacitive sensor is improved, and in addition, adverse effects on functions based on the signal quantity cannot be caused. Certainly, considering the capacitance to sense the functional parameters such as the signal-to-noise ratio, the layout of the circuit structure below the top metal layer, particularly the partial sensitive circuit, can appropriately avoid the through hole area of the top metal layer to achieve a better shielding effect. In this embodiment, the performance of the capacitive sensor can be improved by adjusting the size or the position of the through hole, and if the chip includes components such as capacitors and amplifiers, and these circuits are disposed below the top metal layer, the through hole can be disposed at a position other than directly above these components, for example, the capacitor detection circuit is disposed below the top metal layer, and the through hole is disposed at a position other than directly above the capacitor detection circuit, which can also be understood as that the through hole and the circuit below the top metal layer are not overlapped in the vertical direction.

The capacitive sensor provided by this embodiment includes any one of the pixel units in the foregoing embodiments, and a plurality of pixel units are arranged side by side. Referring to fig. 13, each rectangular frame shown in fig. 13 is a capacitive sensing unit, or pixel unit. A sufficient number of pixel units are arranged side by side to take on the sensing function, the side length of the pixel unit is not less than 40 μm and not more than 50 μm, for example, the side length of the pixel unit can be 45 μm, and in the embodiment, the shape of the pixel unit can be a cube. In addition, the length of the top metal layer is greater than or equal to 35 μm, and the width of the top metal layer is greater than or equal to 35 μm. The light circular shading of the pixel cell surface in the middle of fig. 13 is a mark for microscope focusing to indicate focusing accuracy. For specific implementation of the capacitive sensor provided in the embodiment of the present application, reference is made to the above embodiments, and details are not described herein again.

It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

In addition, the term "and/or" herein is only one kind of association relationship describing the association object, and means that there may be three kinds of relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A capacitive sensor comprising a plurality of pixel cells arranged side by side, the pixel cells comprising a silicon substrate, a structural layer and a passivation layer;

the passivation layer is provided with one or more grooves which are arranged right above the through hole.

2. A capacitive sensor according to claim 1 wherein the upper opening of the through-hole is circular; the lower opening of the through hole is circular; the diameter of the upper opening of the through hole is larger than 2 mu m.

3. A capacitive sensor according to claim 2, wherein the top metal layer is provided with one of the vias; the diameter of the upper opening of the through hole is not less than 7.5 μm and not more than 9.5 μm, and the farthest distance between the edge of the through hole and the edge of the top metal layer is less than or equal to 35 μm.

4. A capacitive sensor according to claim 3 wherein the centre of the via is no more than 6.9 μm from the centre of the top metal layer.

5. A capacitive sensor according to claim 4 wherein the center of the via is 6.7 μm from the center of the top metal layer.

6. A capacitive sensor according to claim 4, wherein the via is provided in a central position of the top metal layer.

7. A capacitive sensor according to claim 6 wherein the diameter of the upper opening of the via is 7.9 μm; the diameter of the lower opening of the through hole is 7.5 μm.

8. A capacitive sensor according to claim 1 wherein the top metal layer is provided with four said vias, said four vias being equidistant from the center of the top metal layer, the upper opening of said vias having a diameter of 4.5 μm.

9. The capacitive sensor of any one of claims 1 to 8 further comprising a capacitance detection circuit disposed below the top metal layer, the via disposed at a location other than directly above the capacitance detection circuit; the top metal layer is used for playing a role of the capacitance sensing polar plate.

10. A capacitive sensor according to any one of claims 1 to 8, wherein the recess is provided directly above the through-hole, the area of the opening in the recess being greater than the area of the floor of the recess.

11. A capacitive sensor according to any of claims 1 to 8, wherein the recess is provided inside the through-hole, the area of the opening in the recess being greater than the area of the bottom surface of the recess.

12. A capacitive sensor according to any one of claims 1 to 8, wherein the recess is a U-shaped recess or a truncated cone-shaped recess, the area of the upper bottom surface of the truncated cone-shaped recess being greater than the area of the lower bottom surface of the truncated cone-shaped recess.

13. A capacitive sensor according to any one of claims 1 to 8, wherein the angle of the slope formed by the sides of the recess decreases with increasing horizontal height.

14. A capacitive sensor according to any one of claims 1 to 8, wherein the lower floor of the recess forms an obtuse angle with the side of the recess.

15. A capacitive sensor according to any of claims 1 to 8, wherein the angle formed by the lower floor of the recess and the side of the recess is greater than or equal to 100 degrees.

16. A capacitive sensor according to any one of claims 1 to 8, wherein the angle formed by the lower floor of the recess and the side faces of the recess is equal to 145 degrees.

17. The capacitive sensor according to any one of claims 1 to 8, wherein the through hole is a cylindrical through hole or a truncated cone through hole;

the area of the upper bottom surface of the circular truncated cone-shaped through hole is larger than that of the lower bottom surface of the circular truncated cone-shaped through hole;

the inclination angle of the side surface of the truncated cone-shaped through hole is 85 degrees.

18. A capacitive sensor according to any one of claims 1 to 8, wherein the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, the silicon nitride layer being disposed over the silicon dioxide layer.

19. A capacitive sensor according to any one of claims 1 to 8 wherein the thickness of the top metal layer is not less than 0.8 μm and not more than 0.9 μm; the top metal layer is an aluminum layer; the length of the top metal layer is greater than or equal to 35 μm; the width of the top metal layer is greater than or equal to 35 μm.

20. A capacitive sensor according to any of claims 1 to 8, wherein the thickness of the passivation layer on the upper surface of the top metal layer is greater than or equal to 2.85 μm.

21. A capacitive sensor according to any one of claims 1 to 8, wherein the thickness of the passivation layer on the upper surface of the top metal layer is 3.15 μm; the thickness of the top metal layer is 0.9 μm.

22. A capacitive sensor according to any one of claims 1 to 8, further comprising a plastics layer; the plastic packaging layer is arranged on the upper surface of the passivation layer.

23. A capacitive sensor according to any one of claims 1 to 8, wherein the pixel cell has a side length of 45 μm.

24. A method of making a capacitive sensor for making a capacitive sensor according to any one of claims 1 to 23, comprising:

forming a circular through hole in a top metal layer of a pixel unit of the capacitive sensor;

forming a passivation layer on the upper surface of the structural layer of the capacitive sensor; the structural layer comprises the top metal layer and a dielectric layer, and the dielectric layer is arranged below the top metal layer.

25. The method of claim 24, wherein before forming the circular via hole in the top metal layer of the pixel unit of the capacitive sensor, the method further comprises:

depositing the top metal layer of the pixel unit of the capacitive sensor by sputtering;

calibrating the pattern of the circular through hole with a distance of not more than 6.9 μm from the center of the top metal layer of the pixel unit.

26. The method of claim 25, wherein forming a circular via in a top metal layer of a pixel unit of the capacitive sensor comprises: and etching the circular through hole in the top metal layer of the pixel unit according to the pattern by a reactive ion etching process.

27. The method of claim 24, wherein the forming a passivation layer on an upper surface of the structural layer of the capacitive sensor comprises: depositing the passivation layer using a chemical vapor deposition process.