CN108417558A - Fuse-wires structure and forming method thereof - Google Patents
Fuse-wires structure and forming method thereof Download PDFInfo
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- CN108417558A CN108417558A CN201810442638.9A CN201810442638A CN108417558A CN 108417558 A CN108417558 A CN 108417558A CN 201810442638 A CN201810442638 A CN 201810442638A CN 108417558 A CN108417558 A CN 108417558A
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- fuse
- layer
- dielectric layer
- pad
- metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of fuse-wires structure forming methods, include the following steps：First medium layer, the first metal layer, second dielectric layer, second metal layer and passivation layer are sequentially formed on silicon substrate；Silicon chip surface resist coating etches the passivation layer of fuse region and the passivation layer of pad area, then the upper surface of the first metal layer is performed etching and stopped to the second dielectric layer of fuse region；Silicon chip surface deposits third dielectric layer；Silicon chip surface resist coating simultaneously makes photoresist be filled up completely fuse through-hole and pad through-holes；Photoresist of the photoresist inside pad through-holes is etched by until etching completely；The third dielectric layer on etching silicon wafer surface is until the third dielectric layer on pad through-holes is etched completely；All photoresists for removing silicon chip surface form the third dielectric layer of U-shaped in fuse through-hole.The uniformity of thickness of dielectric layers in the present invention on fuse-wires structure is uniquely determined by the uniformity of third dielectric layer deposition, can meet the demand for having high request in fuse-wires structure to the dielectric layer on metal layer.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process area, more particularly to a kind of fuse-wires structure and its formation side
Method.
Background technology
With the improvement of semiconductor process technology and the raising of IC complexity, the size of chip persistently increases
Add, semiconductor components and devices also becomes to be more prone to be influenced by silicon wafer volume defect or impurity, and single component such as transistor
Or the failure of storage unit, it frequently can lead to the disabler of entire integrated circuit.
In order to solve this problem, common method is to form some connecting lines that can be fused in integrated circuits,
It is exactly fuse (fuse) structure, to ensure the availability of integrated circuit.In general, fuse-wires structure is for connecting in integrated circuit
Redundant circuit (redundancy circuit), if finding that defect occurs in certain block circuit after technique, so that it may with by fuse
Fusing, makes it that can not work using fuse-wires structure, and is repaired or replaced using redundant circuit and absent circuit structure occur.
Fuse-wires structure is frequently used in memory, when memory chip production is completed, if wherein having partial memory cell or electricity
There is function problem in road, so that it may by (or destruction) and the relevant fuse-wires structure of defective circuits of selectively fusing, to swash simultaneously
The storage unit or circuit of redundancy living are replaced with forming new circuit, realize the purpose of reparation.In addition, fuse-wires structure is also common
In programmable circuit, according to user's needs, the standard logical unit in circuit is programmed using fuse-wires structure, for real
Now specific function.Alternatively, a general integrated circuit of design, according to the demand of different user, by unwanted circuit mould
Block is blown by fuse-wires structure, and IC design a in this way can manufacture and be suitable for different visitors in an economical manner
Family.
Currently, the laser fuse structures made using metal wire in many chips, i.e. metal fuse (metal fuse), tool
Body structure is as shown in Figure 1 d.It is formed with first medium layer 2 on silicon substrate 1, is the first metal layer 3 on first medium layer 2, the
It is the second dielectric layer 4 of one layer of skiving on one metal layer 3.In fuse region, the first metal layer is exactly metal fuse wire structure, skiving
Second dielectric layer 4 is exactly the protective layer of metal fuse wire structure, and the two constitutes fuse-wires structure 8.Positioned at the first metal layer 3 of pad area
Upper is normal second dielectric layer 4, is second metal layer 5 in second dielectric layer 4 herein, which forms pad
Structure 7.It is to be situated between that entire silicon chip, which removes fuse region and pad area also to have a passivation layer 6, the passivation layer 6 with the top of exterior domain,
Matter, for example, silica, silicon nitride, silicon oxynitride etc..
Above-mentioned fuse-wires structure 8 usually requires to form an opening, as shown in Figure 1 d, the i.e. second medium of skiving in top layer
There is no passivation layer 6 on layer 4.Cutting metal fuse wire structure mostly uses greatly laser and blows at present, and in fusing, laser needs accurately
It is directed at fuse-wires structure and other adjacent devices must not be destroyed.
The forming method of existing metal fuse wire structure 8 shown in Fig. 1 d, as shown in Fig. 2, specifically comprising the following steps：
1st step, please refers to Fig.1 a, and first medium layer 2, the first metal layer 3, second medium are sequentially formed on silicon substrate 1
Layer 4；
2nd step please refers to Fig.1 b, defines second metal layer 5, forms pad；
The definition second metal layer 5 is exactly the second metal layer 5 for first depositing a flood, then by the of subregion
Two metal layers get rid of (because not needing), and the second metal layer 5 in remaining region is retained, and at least retain the second gold medal of pad area
Belong to layer 5；
3rd step, please refers to Fig.1 c, in one layer of dielectric material of entire wafer deposition as passivation layer 6, for protecting in chip
Portion's circuit；
4th step, please refers to Fig.1 d, and the passivation layer in pad area is removed, and pad structures 7 is formed, to make pad expose
Come, for follow-up lead and encapsulates；Also by fuse region passivation layer and part second dielectric layer 4 remove, only protected in fuse region
One layer of second dielectric layer 4 for staying lower thickness H, to form metal fuse wire structure 8.
Traditional fuse-wires structure has certain appearance to the thickness H of dielectric layer (i.e. second dielectric layer 4 in Fig. 1 d) thereon
Bear range, exceeds this tolerance, will result in the failure of circuit mending.But in traditional forming method, fuse knot
Uniformity on structure between the thickness of dielectric layer, wafer and in wafer is all uniformity when being deposited by second dielectric layer 4, second is situated between
What the uniformity of uniformity and fuse etching when matter layer 4 is ground determined, this manufacturing process is for there is high uniformity to require
Chip just cannot be satisfied demand.
Invention content
The technical problem to be solved in the present invention is to provide a kind of fuse-wires structures and forming method thereof, can solve existing manufacture
Dielectric layer homogeneity question in technique on fuse-wires structure.
In order to solve the above technical problems, fuse-wires structure forming method provided by the invention, includes the following steps：
Step 1 sequentially forms first medium layer, the first metal layer, second dielectric layer, second metal layer on a silicon substrate
And passivation layer；
Step 2 forms the photoetching offset plate figure of fuse region and pad area in silicon chip surface resist coating；
Step 3 etches the passivation layer of fuse region and the passivation layer of pad area, then is carried out to the second dielectric layer of fuse region
The upper surface of the first metal layer is etched and stopped at, fuse through-hole and pad through-holes are formed；
Step 4 deposits a third dielectric layer, the thickness and fuse-wires structure of the third dielectric layer in entire silicon chip surface
Protective layer thickness require it is consistent；
Step 5 in silicon chip surface resist coating, and makes photoresist be filled up completely fuse through-hole and pad through-holes；
Step 6 etches photoresist, and the photoresist inside pad through-holes by until etching completely；
Step 7, the third dielectric layer on etching silicon wafer surface, until the third dielectric layer on pad through-holes is etched completely；
Step 8 removes all photoresists of silicon chip surface, and the third dielectric layer of U-shaped is formed in fuse through-hole.
Wherein, in step 1, first medium layer, the first metal layer, second dielectric layer are first sequentially formed on a silicon substrate,
Then second metal layer is defined, at least retains second metal layer in pad area, finally in entire wafer deposition passivation layer.
Wherein, in step 4, one layer is all formed in the bottom and side wall of fuse through-hole, the bottom and side wall of pad through-holes
Third dielectric layer.
Wherein, in step 7, the third dielectric layer in pad through-holes is also etched completely.
The present invention includes the first metal layer on being formed in first medium layer using fuse-wires structure made of the above method
On be a U-shaped third dielectric layer, the bottom surface of the third dielectric layer is in contact with the top surface of the first metal layer, the first metal layer
For metal fuse wire structure, the third dielectric layer of U-shaped is the protective layer of the metal fuse wire structure.
The forming method of the present invention can significantly improve the uniformity for being located at the dielectric layer on metal layer in fuse-wires structure
Relative to traditional fuse via etch process, the present invention is by the upper surface of fuse via etch to the first metal layer, then passes through
Deposit meets the third dielectric layer of fuse-wires structure thickness requirement, so that thickness of dielectric layers in metal fuse wire structure it is uniform
Property is uniquely determined that can meet in fuse-wires structure has the dielectric layer on metal layer by the uniformity of third dielectric layer deposition completely
The demand of high request.
Description of the drawings
Fig. 1 a to Fig. 1 d are the fuse-wires structure cross-sectional view of preparation method of the prior art；
Fig. 2 is the production method flow chart of the fuse-wires structure of the prior art；
Fig. 3 to Fig. 9 is the fuse-wires structure cross-sectional view of preparation method of the present invention；
Figure 10 is the production method flow chart of the fuse-wires structure of the present invention.
Wherein the reference numerals are as follows：
1 is silicon substrate；2 be first medium layer；3 be the first metal layer；4 be second dielectric layer；5 be second metal layer；6 are
Passivation layer；7 be pad structures；8,8 ' be fuse-wires structure；9 be third dielectric layer；10 be photoresist.
Specific implementation mode
The present invention is described in further detail with specific implementation mode below in conjunction with the accompanying drawings.
The fuse-wires structure of the present invention, is formed in as shown in figure 9, being included on first medium layer 2 (being formed on silicon substrate 1)
The first metal layer 3 on be a U-shaped third dielectric layer 9, the top surface of the bottom surface and the first metal layer 2 of the third dielectric layer 9
It is in contact, the first metal layer 2 is metal fuse wire structure, and the third dielectric layer 9 of U-shaped is the protective layer of the metal fuse wire structure.
In addition, being second dielectric layer 4 on the first metal layer 3, which is retained in the area in addition to fuse region
Domain, being defined on second dielectric layer 4 has second metal layer 5, forms pad structure.Entire silicon chip removes fuse region and pad area
The top in region in addition also has passivation layer 6.
Fuse-wires structure forming method provided by the invention includes the following steps as shown in Figure 10：
Step 1 sequentially forms first medium layer 2, the first metal layer 3, second dielectric layer 4, the second gold medal on silicon substrate 1
Belong to layer 5 and passivation layer 6, as shown in Figure 3；
Specifically, first medium layer 2, the first metal layer 3, second dielectric layer 4 are sequentially formed on silicon substrate 1 first, so
Second metal layer 5 is defined afterwards (first to deposit the second metal layer 5 of a flood, then remove the second metal layer of subregion
Fall (because not needing), the second metal layer 5 in remaining region is retained, at least retains the second metal layer 5 of pad area, finally exist
Entire wafer deposition passivation layer 6；
Step 2 forms the photoetching offset plate figure of fuse region and pad area in silicon chip surface resist coating；
Step 3, etches the passivation layer 6 of fuse region and the passivation layer 6 of pad area, then to the second dielectric layer 4 of fuse region into
Row etches and stops at the upper surface of the first metal layer 3, forms fuse through-hole and pad through-holes, as shown in Figure 4；
Step 4 deposits a third dielectric layer 9, bottom and side wall, pad through-holes in fuse through-hole in entire silicon chip surface
Bottom and side wall all form one layer of third dielectric layer 9, the thickness H ' of the third dielectric layer 9 and the protection thickness of fuse-wires structure
Degree requires unanimously, as shown in Figure 5；
Step 5 in silicon chip surface resist coating 10, and makes photoresist 10 be filled up completely fuse through-hole and pad through-holes, such as
Shown in Fig. 6；
Step 6, etches photoresist 10, and photoresist 10 inside pad through-holes by until etching completely, such as Fig. 7 institutes
Show；
Step 7, the third dielectric layer 9 on etching silicon wafer surface, until the third dielectric layer on pad through-holes and in pad through-holes
9 are etched completely, as shown in Figure 8；
Step 8 removes all photoresists 10 of silicon chip surface, the third dielectric layer 9 of U-shaped is formed in fuse through-hole, such as
Shown in Fig. 9.
The forming method of the present invention can significantly improve the uniformity for being located at the dielectric layer on metal layer in fuse-wires structure
Relative to traditional fuse via etch process, the present invention is by the upper surface of fuse via etch to the first metal layer, then passes through
Deposit meets the third dielectric layer of fuse-wires structure thickness requirement, so that thickness of dielectric layers in metal fuse wire structure it is uniform
Property is uniquely determined that can meet in fuse-wires structure has the dielectric layer on metal layer by the uniformity of third dielectric layer deposition completely
The demand of high request.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can make many modification and improvement, these should also be regarded
For protection scope of the present invention.
Claims (5)
1. a kind of fuse-wires structure forming method, which is characterized in that include the following steps：
Step 1 sequentially forms first medium layer, the first metal layer, second dielectric layer, second metal layer and blunt on a silicon substrate
Change layer；
Step 2 forms the photoetching offset plate figure of fuse region and pad area in silicon chip surface resist coating；
Step 3 etches the passivation layer of fuse region and the passivation layer of pad area, then is performed etching to the second dielectric layer of fuse region
And the upper surface of the first metal layer is stopped at, form fuse through-hole and pad through-holes；
Step 4 deposits a third dielectric layer, the guarantor of the thickness and fuse-wires structure of the third dielectric layer in entire silicon chip surface
Covering thickness requires consistent；
Step 5 in silicon chip surface resist coating, and makes photoresist be filled up completely fuse through-hole and pad through-holes；
Step 6 etches photoresist, and the photoresist inside pad through-holes by until etching completely；
Step 7, the third dielectric layer on etching silicon wafer surface, until the third dielectric layer on pad through-holes is etched completely；
Step 8 removes all photoresists of silicon chip surface, and the third dielectric layer of U-shaped is formed in fuse through-hole.
2. fuse-wires structure forming method according to claim 1, which is characterized in that in step 1, first on a silicon substrate
First medium layer, the first metal layer, second dielectric layer are sequentially formed, second metal layer is then defined, is at least retained in pad area
Second metal layer, finally in entire wafer deposition passivation layer.
3. fuse-wires structure forming method according to claim 1, which is characterized in that in step 4, in fuse through-hole
Bottom and side wall, the bottom and side wall of pad through-holes all form one layer of third dielectric layer.
4. fuse-wires structure forming method according to claim 1, which is characterized in that in step 7, in pad through-holes
Three dielectric layers are also etched completely.
5. a kind of using fuse-wires structure made of fuse-wires structure forming method described in claim 1, which is characterized in that be included in
Be formed on the first metal layer on first medium layer be a U-shaped third dielectric layer, the bottom surface of the third dielectric layer and the
The top surface of one metal layer is in contact, and the first metal layer is metal fuse wire structure, and the third dielectric layer of U-shaped is the metal fuse knot
The protective layer of structure.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810442638.9A CN108417558A (en) | 2018-05-10 | 2018-05-10 | Fuse-wires structure and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810442638.9A CN108417558A (en) | 2018-05-10 | 2018-05-10 | Fuse-wires structure and forming method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109830459A (en) * | 2019-01-28 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of forming method of fuse-wires structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1467815A (en) * | 2002-06-05 | 2004-01-14 | �����ɷ� | Method of forming a fuse |
| US20070023860A1 (en) * | 2005-07-12 | 2007-02-01 | Samsung Electronics Co., Ltd. | Semiconductor device having a fuse barrier pattern and fabrication method thereof |
| CN1979817A (en) * | 2005-12-01 | 2007-06-13 | 联华电子股份有限公司 | Semiconductor structure and its preparing process |
| CN101047147A (en) * | 2006-03-27 | 2007-10-03 | 台湾积体电路制造股份有限公司 | IC structure and its making method |
| US20070284702A1 (en) * | 2006-05-10 | 2007-12-13 | Gyong-Sub Im | Semiconductor device having a bonding pad and fuse and method for forming the same |
| CN104576603A (en) * | 2013-10-28 | 2015-04-29 | 北大方正集团有限公司 | Integrated circuit including laser fuse wire and manufacturing method thereof |
-
2018
- 2018-05-10 CN CN201810442638.9A patent/CN108417558A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1467815A (en) * | 2002-06-05 | 2004-01-14 | �����ɷ� | Method of forming a fuse |
| US20070023860A1 (en) * | 2005-07-12 | 2007-02-01 | Samsung Electronics Co., Ltd. | Semiconductor device having a fuse barrier pattern and fabrication method thereof |
| CN1979817A (en) * | 2005-12-01 | 2007-06-13 | 联华电子股份有限公司 | Semiconductor structure and its preparing process |
| CN101047147A (en) * | 2006-03-27 | 2007-10-03 | 台湾积体电路制造股份有限公司 | IC structure and its making method |
| US20070284702A1 (en) * | 2006-05-10 | 2007-12-13 | Gyong-Sub Im | Semiconductor device having a bonding pad and fuse and method for forming the same |
| CN104576603A (en) * | 2013-10-28 | 2015-04-29 | 北大方正集团有限公司 | Integrated circuit including laser fuse wire and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109830459A (en) * | 2019-01-28 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of forming method of fuse-wires structure |
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