CN104576603A - Integrated circuit including laser fuse wire and manufacturing method thereof - Google Patents
Integrated circuit including laser fuse wire and manufacturing method thereof Download PDFInfo
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- CN104576603A CN104576603A CN201310516555.7A CN201310516555A CN104576603A CN 104576603 A CN104576603 A CN 104576603A CN 201310516555 A CN201310516555 A CN 201310516555A CN 104576603 A CN104576603 A CN 104576603A
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Abstract
The invention relates to the field of manufacturing of integrated circuits, and in particular relates to an integrated circuit including a laser fuse wire and a manufacturing method of the integrated circuit. The problem in the prior art that sputtered metal residues fall into the integrated circuit and onto the surface of a substrate in a passivation layer window of the laser fuse wire after the integrated circuit including the laser fuse wire is repaired and maintained to cause relatively low pass percentage of the repaired and maintained integrated circuit is solved. According to the integrated circuit including the laser fuse wire and the manufacturing method of the integrated circuit provided by the embodiment of the invention, the passivation layer window corresponding to the laser fuse wire in the integrated circuit comprises a passivation layer with certain thickness, and the thickness of the passivation layer of the passivation layer window corresponding to the laser fuse wire is less than that of the passivation layer of an area outside the passivation layer window corresponding to the laser fuse wire; when the integrated circuit including the laser fuse wire is repaired and maintained, because the fuse wire is coated with the passivation layer, , sputtering of fuse wire metals, caused by fusing the fuse wire by laser beams, is reduced, and the pass percentage of laser repairing and maintenance is increased.
Description
Technical field
The present invention relates to IC manufacturing field, particularly relate to a kind of integrated circuit and the manufacture method thereof that comprise laser fuse.
Background technology
Fuse is a resistor-type structure in integrated circuit, and its Main Function is by blow out fuse, reaches the adjustment function of integrated circuit or the object of parameter.
According to the blowout method of fuse, fuse can be divided into electric fuse (Electrical Fuse) and laser fuse (Laser Fuse).Wherein, laser fuse typically refers to and carries out fusing process to metal, and laser fuse directly adopts the laser beam irradiation fuse of certain energy to make fuse failure usually.
As shown in Figure 1, be traditional manufacture method comprising laser fuse integrated circuit, the method comprises:
Step 101: form dielectric layer on underlay substrate, dielectric layer is formed pressure welding pad and laser fuse; Form the integrated circuit semi-finished product after pressure welding pad and laser fuse as shown in Figure 2, wherein 201 is underlay substrate, and 202 is dielectric layer, and 203 is pressure welding pad, and 204 is laser fuse;
Step 102: the integrated circuit semi-finished product after forming pressure welding pad and laser fuse first deposit one deck silica, then deposits one deck silicon nitride, forms passivation layer; Be illustrated in figure 3 the integrated circuit semi-finished product after deposit passivation layer, 310 is passivation layer, and wherein 301 is the silicon oxide layer in passivation layer, and 302 is the silicon nitride layer in passivation layer;
Step 103: apply one deck photoresist on the integrated circuit semi-finished product forming passivation layer, and graphical treatment is carried out to the integrated circuit semi-finished product of coating photoresist, form required photoresist graph window; Be illustrated in figure 4 the integrated circuit semi-finished product after forming required photoresist graph window, wherein 401 is photoresist, and 402 is photoresist graph window;
Step 104: carry out etching processing to the integrated circuit semi-finished product forming photoresist graph window, removes the passivation layer that photoresist graph window is corresponding, forms passivation layer window; As shown in Figure 5, for the integrated circuit semi-finished product after etching processing, wherein 501 is the passivation layer window that pressure welding pad is corresponding, 502 is the passivation layer window that laser fuse is corresponding, Figure 6 shows that the vertical view of passivation layer window, wherein 501 is the passivation layer window that pressure welding pad is corresponding, and 203 is pressure welding pad, 502 is the passivation layer window that laser fuse is corresponding, and 204 is laser fuse;
Step 105: remove remaining photoresist, forms the integrated circuit comprising laser fuse; Be illustrated in figure 7 the integrated circuit comprising laser fuse.
Wherein, pressure welding pad and laser fuse are normally formed by multiple layer metal superposition, and topmost metal layer is generally titanium nitride metal layer, and titanium nitride easily causes the qualification rate of " routing " technique of integrated circuit to decline.When therefore etching processing being carried out to the integrated circuit semi-finished product forming photoresist graph window in step 104, not only need to remove the passivation layer in photoresist graph window, and need the titanium nitride metal layer on pressure welding pad surface to etch away.Therefore in step 104, need the integrated circuit semi-finished product to forming photoresist graph window to carry out over etching process.After the passivation layer window figure corresponding to laser fuse carries out over etching process, when the passivation layer window figure corresponding to pressure welding pad carries out etching processing, not only can remove the titanium nitride metal layer of the laser fuse the superiors, and can not etched away in passivation layer window figure by the dielectric layer that laser fuse covers, thus make underlay substrate exposed.As shown in Figure 7, traditional integrated circuit comprising laser fuse, when laser trimming, splashing is there will be by the metal fuse that laser beam fuses, the metallic residue that a part is splashed has dropped on the inside of integrated circuit, the metallic residue that a part is splashed has dropped on the substrate surface in the passivation layer window of laser fuse, and this will cause integrated circuit short circuit, and after making to trim, the qualification rate of integrated circuit declines.
Therefore, after the integrated circuit comprising laser fuse of conventional method manufacture carries out trimming process, because the metallic residue of splashing has dropped on the inside of integrated circuit, and the substrate surface in the passivation layer window of laser fuse, after causing trimming process, integrated circuit qualification rate is lower.
Summary of the invention
The embodiment of the present invention provides a kind of integrated circuit and the manufacture method thereof that comprise laser fuse, to solve after the integrated circuit comprising laser fuse in prior art carries out trimming process, the metallic residue of splashing drops on the inside of integrated circuit, and the substrate surface in the passivation layer window of laser fuse, the problem that after causing trimming process, integrated circuit qualification rate is lower.
Embodiments provide a kind of manufacture method comprising the integrated circuit of laser fuse, the method comprises:
Deposit passivation layer on the integrated circuit semi-finished product comprising pressure welding pad and laser fuse;
At the surface-coated photoresist of described passivation layer;
Removed the photoresist of the first predeterminable area by graphical treatment technique, described first predeterminable area is positioned at the region at described pressure welding pad place;
Removed the totally inactivating layer of the first predeterminable area by etching technics, form the first passivation layer window;
Removed the photoresist of the second predeterminable area by graphical treatment technique, described second predeterminable area is positioned at the region at described laser fuse place;
Removed the partial deactivation layer of the second predeterminable area by etching technics, form the second passivation layer window;
Remove the residue photoresist covered in described passivation layer surface, form the integrated circuit comprising pressure welding pad and laser fuse.
In above-described embodiment, owing to etching respectively passivation layer window corresponding to pressure welding pad and passivation layer window corresponding to laser fuse, avoid the passivation layer window corresponding to pressure welding pad when carrying out over etching, dielectric layer in the passivation layer window causing laser fuse corresponding is etched away, and then when causing trimming integrated circuit, the metallic residue of splashing drops on the problem on the exposed underlay substrate of integrated circuit.And etching technics eliminates the partial deactivation layer of the second predeterminable area in above-described embodiment, laser fuse is covered by remaining passivation layer, when carrying out laser trimming to integrated circuit, due to fuse, to be passivated layer coated, decreasing the splashing of fuse fuse metal when being fused by laser beam, improve the qualification rate of laser trimming.
The embodiment of the present invention comprises further, after described formation first passivation layer window, before being removed the photoresist of the second predeterminable area, comprising by graphical treatment technique:
Remove remaining photoresist on the integrated circuit semi-finished product after formation first passivation layer window;
Integrated circuit semi-finished product after described removal photoresist apply one deck photoresist again.
The described photoresist being removed the second predeterminable area by graphical treatment technique, being comprised:
The photoresist of half-finished second predeterminable area of integrated circuit of one deck photoresist is again applied described in being removed by graphical treatment technique.
In above-described embodiment, owing to removing remaining photoresist on integrated circuit semi-finished product after formation first passivation layer window, again apply one deck photoresist, the integrated circuit semi-finished product again applying one deck photoresist form the second passivation layer window, during owing to making the first passivation layer window, the second passivation layer window position is covered by photoresist, when therefore the first passivation layer window carries out over etching, can not impact the second passivation layer window, vice versa.
The photoresist that the embodiment of the present invention removes the second predeterminable area by graphical treatment technique comprises: after removing formation first passivation layer window by graphical treatment technique the photoresist of half-finished second predeterminable area of integrated circuit.
In above-described embodiment, after formation first passivation layer window, directly graphical treatment is carried out to remaining photoresist, remove the photoresist of the second predeterminable area, the second passivation layer window is formed, owing to making two passivation layer windows respectively, and when carrying out etching processing to the second passivation layer window by etching technics, can not impact the first passivation layer window, form the integrated circuit comprising laser fuse required in the embodiment of the present invention.
Embodiment of the present invention passivation layer comprises the first passivation layer and the second passivation layer further, and wherein the first passivation layer covers on the second passivation layer; The partial deactivation layer of described removal second predeterminable area, comprising: the thickness of the partial deactivation layer of the second predeterminable area of removal is not less than the thickness of described first passivation layer.
In above-described embodiment, the first passivation layer window is the passivation layer window that pressure welding pad is corresponding, and the passivation layer of the first passivation layer window is etched completely away, and can meet the requirement of integrated antenna package routing; Second passivation layer window is the passivation layer window that laser fuse is corresponding, first passivation layer is etched away, leave the obvious passivation layer window marking on the integrated, as long as the laser fuse of this passivation layer window stamp positions of laser beam irradiation with setting energy, just can make fuse failure.
Embodiments provide a kind of manufacture method comprising the integrated circuit of laser fuse, the method comprises:
Deposit passivation layer on the integrated circuit semi-finished product comprising pressure welding pad and laser fuse;
At the surface-coated photoresist of described passivation layer;
Removed the photoresist of the first predeterminable area by graphical treatment technique, described first predeterminable area is positioned at the region at described laser fuse place;
Removed the partial deactivation layer of the first predeterminable area by etching technics, form the first passivation layer window;
Remove the remaining photoresist of integrated circuit surface of semi-finished after formation first passivation layer window, the integrated circuit surface of semi-finished after described first passivation layer window of formation applies photoresist again;
Removed the photoresist again applying half-finished second predeterminable area of integrated circuit of photoresist by graphical treatment technique, described second predeterminable area is positioned at the region at described pressure welding pad place;
Removed the totally inactivating layer of the second predeterminable area by etching technics, form the second passivation layer window;
Remove the residue photoresist covered in described passivation layer surface, form the integrated circuit comprising pressure welding pad and laser fuse.
In above-described embodiment, owing to etching respectively passivation layer window corresponding to pressure welding pad and passivation layer window corresponding to laser fuse, avoid the passivation layer window corresponding to pressure welding pad when carrying out over etching, dielectric layer in the passivation layer window causing laser fuse corresponding is etched away, and then when causing trimming integrated circuit, the metallic residue of splashing drops on the problem on the exposed underlay substrate of integrated circuit.And etching technics eliminates the partial deactivation layer of the second predeterminable area in above-described embodiment, laser fuse is covered by remaining passivation layer, when carrying out laser trimming to integrated circuit, due to fuse, to be passivated layer coated, decreasing the splashing of fuse fuse metal when being fused by laser beam, improve the qualification rate of laser trimming.
Embodiment of the present invention passivation layer comprises the first passivation layer and the second passivation layer, and wherein the first passivation layer covers on the second passivation layer; The partial deactivation layer of described removal first predeterminable area, comprising: the thickness of the partial deactivation layer of the first predeterminable area of removal is not less than the thickness of described first passivation layer.
In above-described embodiment, the second passivation layer window is the passivation layer window that pressure welding pad is corresponding, and the passivation layer of the second passivation layer window is etched completely away, and can meet the requirement of integrated antenna package routing; First passivation layer window is the passivation layer window that laser fuse is corresponding, first passivation layer is etched away, leave the obvious passivation layer window marking on the integrated, as long as the laser fuse of this passivation layer window stamp positions of laser beam irradiation with setting energy, just can make fuse failure.
Embodiments provide a kind of integrated circuit comprising laser fuse, this integrated circuit comprises underlay substrate, dielectric layer, passivation layer, the first passivation layer window, the second passivation layer window, pressure welding pad and laser fuse;
Described dielectric layer covers on described underlay substrate, and described pressure welding pad and laser fuse are positioned on described dielectric layer;
Described first passivation layer window is positioned on described pressure welding pad, and described second passivation layer window is positioned at the region at described laser fuse place;
Described passivation layer covers the region outside described first passivation layer window;
Passivation layer thickness in described second passivation layer window is less than the passivation layer thickness in the region outside described second passivation layer window.
In above-described embodiment, laser fuse is wrapped by the passivation layer, and when carrying out laser trimming to integrated circuit, due to fuse, to be passivated layer coated, decreasing the splashing of fuse fuse metal when being fused by laser beam, improve the qualification rate of laser trimming.
In the embodiment of the present invention, passivation layer comprises the first passivation layer and the second passivation layer, and wherein the first passivation layer covers on the second passivation layer; Passivation layer thickness in described second passivation layer window is not more than the thickness of described second passivation layer.
In above-described embodiment, passivation layer thickness in second passivation layer window is not more than the thickness of described second passivation layer, leave the obvious passivation layer window marking on the integrated, as long as the laser fuse of this passivation layer window stamp positions of laser beam irradiation with setting energy, just can make fuse failure.
In the embodiment of the present invention, the size of the first passivation layer window is less than the size of described pressure welding pad, and the size of described second passivation layer window is greater than the size of described laser fuse.
Embodiments provide a kind of integrated circuit comprising laser fuse, this integrated circuit comprises underlay substrate, dielectric layer, passivation layer, the first passivation layer window, the second passivation layer window, pressure welding pad and laser fuse; Dielectric layer covers on underlay substrate, and pressure welding pad and laser fuse are positioned on dielectric layer; First passivation layer window is positioned on pressure welding pad, and the second passivation layer window is positioned at the region at laser fuse place; Passivation layer covers the region outside the first passivation layer window; Passivation layer thickness in second passivation layer window is less than the passivation layer thickness in the region outside the second passivation layer window.Because the passivation layer thickness in the second passivation layer window is not more than the thickness of the second passivation layer, leave the obvious second passivation layer window marking on the integrated, as long as the laser fuse of this passivation layer window stamp positions of laser beam irradiation with setting energy, just can make fuse failure.And laser fuse is wrapped by the passivation layer, when carrying out laser trimming to integrated circuit, due to fuse, to be passivated layer coated, decreases the splashing of fuse fuse metal when being fused by laser beam, and then improve the qualification rate of laser trimming.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method comprising laser fuse integrated circuit in background technology;
Fig. 2 is the half-finished schematic diagram of integrated circuit after forming pressure welding pad and laser fuse in background technology;
Fig. 3 is the half-finished schematic diagram of integrated circuit in background technology after deposit passivation layer;
Fig. 4 is the half-finished schematic diagram of integrated circuit after forming required photoresist graph window in background technology;
Fig. 5 is the half-finished schematic diagram of integrated circuit in background technology after etching processing;
Fig. 6 is the vertical view schematic diagram of passivation layer window in background technology;
Fig. 7 is the schematic diagram of the integrated circuit comprising laser fuse in background technology;
Fig. 8 is a kind of schematic diagram comprising the integrated circuit of laser fuse in the embodiment of the present invention;
Fig. 9 is a kind of schematic flow sheet comprising the manufacture method of the integrated circuit of laser fuse in the embodiment of the present invention;
Figure 10 is the half-finished schematic diagram of integrated circuit in the embodiment of the present invention after deposit passivation layer;
Figure 11 is the half-finished schematic diagram of integrated circuit after applying photoresist in the embodiment of the present invention;
Figure 12 is the half-finished schematic diagram of integrated circuit after the photoresist removing the first predeterminable area in the embodiment of the present invention;
Figure 13 is the half-finished schematic diagram of integrated circuit after forming the first passivation layer window in the embodiment of the present invention;
Figure 14 is the half-finished schematic diagram of integrated circuit after the photoresist removing the second predeterminable area in the embodiment of the present invention;
Figure 15 is the half-finished schematic diagram of integrated circuit after forming the second passivation layer window in the embodiment of the present invention;
Figure 16 is the schematic diagram of the integrated circuit comprising pressure welding pad and laser fuse in the embodiment of the present invention;
Figure 17 is that in the embodiment of the present invention, the first removes the half-finished schematic diagram of integrated circuit after the photoresist of the second predeterminable area;
Figure 18 is the schematic flow sheet that in the embodiment of the present invention, the first removes the manufacture method of integrated circuit corresponding to the photoresist method of the second predeterminable area;
Figure 19 is the schematic flow sheet that in the embodiment of the present invention, the second removes the manufacture method of integrated circuit corresponding to the photoresist method of the second predeterminable area;
Figure 20 is the another kind of schematic flow sheet comprising the manufacture method of the integrated circuit of laser fuse in the embodiment of the present invention;
Figure 21 is the half-finished schematic diagram of integrated circuit in the manufacture method of another kind of integrated circuit in the embodiment of the present invention after deposit passivation layer;
Figure 22 is the half-finished schematic diagram of integrated circuit after applying photoresist in the manufacture method of another kind of integrated circuit in the embodiment of the present invention;
Figure 23 is the half-finished schematic diagram of integrated circuit after the photoresist removing the first predeterminable area in the manufacture method of another kind of integrated circuit in the embodiment of the present invention;
Figure 24 is the half-finished schematic diagram of integrated circuit after forming the first passivation layer window in the manufacture method of another kind of integrated circuit in the embodiment of the present invention;
Figure 25 is the half-finished schematic diagram of integrated circuit after again applying photoresist in the manufacture method of another kind of integrated circuit in the embodiment of the present invention;
Figure 26 is the half-finished schematic diagram of integrated circuit after the photoresist removing the second predeterminable area in the manufacture method of another kind of integrated circuit in the embodiment of the present invention;
Figure 27 is the half-finished schematic diagram of integrated circuit after forming the second passivation layer window in the manufacture method of another kind of integrated circuit in the embodiment of the present invention;
Figure 28 is the schematic flow sheet of the another kind of manufacture method of the integrated circuit comprising laser fuse in the embodiment of the present invention.
Embodiment
Embodiments provide a kind of integrated circuit and the manufacture method thereof that comprise laser fuse, the passivation layer window that in this integrated circuit, laser fuse is corresponding comprises certain thickness passivation layer, and the thickness of the passivation layer of passivation layer window corresponding to laser fuse is less than the thickness of the passivation layer in the region beyond passivation layer window corresponding to laser fuse; When trimming process to the integrated circuit comprising laser fuse, due to fuse, to be passivated layer coated, decreases the splashing of fuse fuse metal when being fused by laser beam, and then improve the qualification rate of laser trimming.
Below in conjunction with Figure of description, the embodiment of the present invention is described further.
As shown in Figure 8, for the integrated circuit comprising laser fuse a kind of in the embodiment of the present invention, this integrated circuit comprises: underlay substrate 801, dielectric layer 802, passivation layer 803, the first passivation layer window 804, second passivation layer window 805, pressure welding pad 806 and laser fuse 807;
Dielectric layer 802 covers on underlay substrate 801, and pressure welding pad 806 and laser fuse 807 are positioned on dielectric layer 802; First passivation layer window 804 is positioned on pressure welding pad 806, and the second passivation layer window 805 is positioned at the region at laser fuse 807 place; Passivation layer 803 covers the region outside the first passivation layer window 804; The thickness of the passivation layer in the second passivation layer window 805 is less than the passivation layer thickness in the region outside the second passivation layer window.
Wherein passivation layer at least comprises the Inorganic Non-metallic Materials of one deck, and when passivation layer is one deck Inorganic Non-metallic Materials, the passivation layer thickness of the second passivation layer window is less than the thickness of Inorganic Non-metallic Materials layer; When passivation layer comprises multilayer Inorganic Non-metallic Materials, the passivation layer thickness of the second passivation layer window is less than the thickness of multilayer Inorganic Non-metallic Materials; Preferably, passivation layer comprises the first passivation layer and the second passivation layer, and wherein the first passivation layer covers on the second passivation layer; And the passivation layer thickness in the second passivation layer window is not more than the thickness of the second passivation layer.As: the first passivation layer is silicon nitride layer, and the second passivation layer is silicon oxide layer, and silicon nitride layer covers on silicon oxide layer, then the passivation layer thickness of the second passivation layer window is not more than the thickness of silicon oxide layer.
Passivation layer thickness in the embodiment of the present invention in the second passivation layer window is not more than the thickness except the passivation layer of second other positions of passivation layer window on integrated circuit, second passivation layer window leaves the obvious passivation layer window marking on the integrated, as long as the laser fuse of this passivation layer window stamp positions of laser beam irradiation with setting energy, just can make fuse failure.And because laser fuse is wrapped by the passivation layer, when carrying out laser trimming to integrated circuit, decreasing the splashing of fuse fuse metal when being fused by laser beam, improve the qualification rate of laser trimming.
Preferably, the size of the first passivation layer window 804 is less than the size of pressure welding pad 806, and the size of the second passivation layer window 805 is greater than the size of laser fuse 807.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of manufacture method comprising the integrated circuit of laser fuse, the principle of dealing with problems due to the manufacture method of this integrated circuit and the embodiment of the present invention be a kind of, and to comprise the integrated circuit of laser fuse similar, therefore the enforcement of the manufacture method of this integrated circuit see the enforcement of device, can repeat part and repeats no more.
As shown in Figure 9, be the manufacture method comprising the integrated circuit of laser fuse a kind of in the embodiment of the present invention, the method comprises:
Step 901: deposit passivation layer on the integrated circuit semi-finished product comprising pressure welding pad and laser fuse; Be the half-finished schematic diagram of integrated circuit after deposit passivation layer as shown in Figure 10, wherein 1001 is underlay substrate, and 1002 is dielectric layer, and 1003 is pressure welding pad, and 1004 is laser fuse, and 1005 is passivation layer;
Step 902: at the surface-coated photoresist of the half-finished passivation layer of integrated circuit; As shown in figure 11, be the half-finished schematic diagram of integrated circuit after coating photoresist, wherein 1101 is photoresist;
Step 903: the photoresist being removed the first predeterminable area by graphical treatment technique, the first predeterminable area is positioned at the region at pressure welding pad place; As shown in figure 12, for remove the first predeterminable area photoresist after the half-finished schematic diagram of integrated circuit;
Step 904: the totally inactivating layer being removed the first predeterminable area by etching technics, forms the first passivation layer window; As shown in figure 13, for forming the half-finished schematic diagram of integrated circuit after the first passivation layer window, wherein 1301 is the first passivation layer window;
Step 905: the photoresist being removed the second predeterminable area by graphical treatment technique, the second predeterminable area is positioned at the region at laser fuse place; As shown in figure 14, for remove the second predeterminable area photoresist after the half-finished schematic diagram of integrated circuit;
Step 906: the partial deactivation layer being removed the second predeterminable area by etching technics, forms the second passivation layer window; As shown in figure 15, for forming the half-finished schematic diagram of integrated circuit after the second passivation layer window, wherein 1501 is the second passivation layer window;
Step 907: remove the residue photoresist covered in passivation layer surface, forms the integrated circuit comprising pressure welding pad and laser fuse; As shown in figure 16, for comprising the schematic diagram of the integrated circuit of pressure welding pad and laser fuse.
Wherein, the thickness of the passivation layer of deposit in step 901, the composition material according to passivation layer is determined, the thickness of the passivation layer that different materials is formed is different.As: when passivation layer comprises silicon oxide layer and silicon nitride layer, the thickness of silicon oxide layer is about 2000 dust ~ 10000 dusts, and the thickness of silicon nitride layer is also about 2000 dust ~ 10000 dusts, and silicon nitride layer covers on silicon oxide layer.
Pressure welding pad and laser fuse are mostly superposed by more metal layers and are formed, thickness is about 5000 dust ~ 40000 dusts, wherein the metal level of the superiors is titanium nitride metal layer, because the fusing point of titanium nitride is higher, and stable chemical nature, the qualification rate of " routing " technique of integrated antenna package is easily caused to decline, therefore in step 904, when being positioned at the totally inactivating layer of first predeterminable area in the region at pressure welding pad place by etching technics removal, over etching technique is adopted to remove the totally inactivating layer of the first predeterminable area, and first titanium nitride layer on pressure welding pad surface of predeterminable area.Preferably, dry etching is adopted to remove passivation layer and titanium nitride layer.As: the gross thickness of passivation layer is 10000 dusts, and the etch amount of setting etching technics is 30000 dusts, to remove the totally inactivating layer of the first predeterminable area, and the titanium nitride layer on the pressure welding pad surface of the first predeterminable area.
Removed the photoresist of the second predeterminable area in step 905 by graphical treatment technique, comprise two kinds of situations, be introduced respectively below:
The first situation: the photoresist half-finished photoresist of integrated circuit after formation first passivation layer window directly being removed the second predeterminable area by graphical treatment technique, specifically comprises:
Exposure imaging process is carried out to the half-finished photoresist of integrated circuit after formation first passivation layer window, removes the photoresist of the second predeterminable area, then removed the partial deactivation layer of the second predeterminable area by etching technics.
Adopt the photoresist half-finished photoresist of integrated circuit after formation first passivation layer window directly being removed the second predeterminable area by graphical treatment technique, form the first predeterminable area and the second predeterminable area respectively, and respectively etching processing is carried out to the passivation layer of the first predeterminable area and the second predeterminable area, avoid when over etching process is carried out to the passivation layer in the first predeterminable area, cause the passivation layer of the second predeterminable area and dielectric layer to be also etched away, and then cause substrate exposed.After the titanium nitride layer on pressure welding pad surface corresponding to the first passivation layer window is etched away, exposed is Al-alloy metal layer, less on the impact of Al-alloy metal layer during etching processing, when therefore etching processing being carried out to the passivation layer in the second predeterminable area, impact less to the first passivation layer window formed.Be the half-finished schematic diagram of integrated circuit after the half-finished photoresist of integrated circuit in the embodiment of the present invention after formation first passivation layer window directly removes the photoresist of the second predeterminable area by graphical treatment technique as shown in figure 17, wherein 1701 is underlay substrate, 1702 is dielectric layer, 1704 is pressure welding pad, 1706 is laser fuse, and 1703 is passivation layer, and 1706 is photoresist, 1707 is the first passivation layer window, and 1708 is the second predeterminable area.
The second situation: after forming the first passivation layer window, removes remaining photoresist on integrated circuit semi-finished product, again applies one deck photoresist, by graphical treatment, removes the photoresist of the second predeterminable area; The partial deactivation layer of the second predeterminable area is removed by etching technics.
During owing to being removed the partial deactivation layer of the second predeterminable area by etching technics, on integrated circuit semi-finished product, the first passivation layer window is covered by photoresist, when therefore removing the partial deactivation layer of the second predeterminable area, can not the pressure welding pad in the first passivation layer window be impacted.As shown in figure 15, after again applying one deck photoresist in the embodiment of the present invention, the half-finished schematic diagram of integrated circuit after the photoresist of the second predeterminable area is removed.
Removed the partial deactivation layer of the second predeterminable area in step 906 by etching technics, specifically comprise: when passivation layer is made up of one deck Inorganic Non-metallic Materials, remove the passivation layer of setting thickness, leave the obvious passivation layer window marking on the integrated; When passivation layer is made up of multilayer Inorganic Non-metallic Materials, remove at least one deck Inorganic Non-metallic Materials layer, leave the obvious passivation layer window marking on the integrated.As: passivation layer comprises passivation layers, first passivation layer is silicon nitride layer, and the second passivation layer is silicon oxide layer, and silicon nitride layer covers on silicon oxide layer, remove whole silicon nitride layer by etching technics, or remove the silicon oxide layer of whole silicon nitride layer and segment thickness by etching technics; Such as: the thickness of silicon nitride layer and silicon oxide layer is 6000 dusts, the thickness of the passivation layer removed by etching technics is 6000 dusts, then now the thickness of remaining passivation layer is the thickness of silicon oxide layer, and the passivation layer thickness of the second passivation layer window is 6000 dusts; If the thickness of the passivation layer removed by etching technics is 7000 dusts, now the thickness of remaining passivation layer is less than the thickness of silicon oxide layer, and the passivation layer thickness of the second passivation layer window is 5000 dusts.
As shown in figure 18, for in the embodiment of the present invention, the first removes the manufacture method of integrated circuit corresponding to the photoresist method of the second predeterminable area, wherein passivation layer comprises two-layer, silicon oxide layer and silicon nitride layer, the manufacture method of the integrated circuit of the passivation layer of other types is similar with it, does not repeat them here.
Step 1801: form dielectric layer on underlay substrate;
Step 1802: form pressure welding pad and laser fuse on dielectric layer;
Step 1803: the integrated circuit semi-finished product after forming pressure welding pad and laser fuse first deposit one deck silica, then deposits one deck silicon nitride, forms passivation layer;
Step 1804: apply one deck photoresist on the integrated circuit semi-finished product forming passivation layer;
Step 1805: carry out graphical treatment to the integrated circuit semi-finished product of coating photoresist, remove the photoresist in the first predeterminable area, wherein the first predeterminable area is positioned at the region at pressure welding pad place;
Step 1806: the totally inactivating layer being removed the first predeterminable area by etching technics, forms the first passivation layer window;
Step 1807: in the integrated circuit surface of semi-finished of formation first passivation layer window, removed the photoresist of the second predeterminable area by graphical treatment technique, wherein the second predeterminable area is positioned at the region at laser fuse place;
Step 1808: removed the silicon nitride layer in the passivation layer of the second predeterminable area by etching technics, forms the second passivation layer window;
Step 1809: remove the residue photoresist covered in passivation layer surface, forms the integrated circuit comprising pressure welding pad and laser fuse.
As shown in figure 19, for the second in the embodiment of the present invention removes the manufacture method of integrated circuit corresponding to the photoresist method of the second predeterminable area, wherein passivation layer comprises two-layer, silicon oxide layer and silicon nitride layer, the manufacture method of the integrated circuit of the passivation layer of other types is similar with it, does not repeat them here.
Step 1901: form dielectric layer on underlay substrate;
Step 1902: form pressure welding pad and laser fuse on dielectric layer;
Step 1903: the integrated circuit semi-finished product after forming pressure welding pad and laser fuse first deposit one deck silica, then deposits one deck silicon nitride, forms passivation layer;
Step 1904: apply one deck photoresist on the integrated circuit semi-finished product forming passivation layer;
Step 1905: carry out graphical treatment to the integrated circuit semi-finished product of coating photoresist, remove the photoresist in the first predeterminable area, wherein the first predeterminable area is positioned at the region at pressure welding pad place;
Step 1906: the totally inactivating layer being removed the first predeterminable area by etching technics, forms the first passivation layer window;
Step 1907: remove remaining photoresist on integrated circuit semi-finished product;
Step 1908: the integrated circuit semi-finished product after removing photoresist apply one deck photoresist again;
Step 1909: again applying the integrated circuit surface of semi-finished of one deck photoresist, removed the photoresist of the second predeterminable area by graphical treatment technique, wherein the second predeterminable area is positioned at the region at laser fuse place;
Step 1910: the silicon oxide layer being removed silicon nitride layer in the passivation layer of the second predeterminable area and segment thickness by etching technics, forms the second passivation layer window;
Step 1911: remove the residue photoresist covered in passivation layer surface, forms the integrated circuit comprising pressure welding pad and laser fuse.
As shown in figure 20, the embodiment of the present invention additionally provides the manufacture method that another kind comprises the integrated circuit of laser fuse, and the method comprises:
Step 2001: deposit passivation layer on the integrated circuit semi-finished product comprising pressure welding pad and laser fuse; Be the half-finished schematic diagram of integrated circuit after deposit passivation layer as shown in figure 21, wherein 2101 is underlay substrate, and 2102 is dielectric layer, and 2103 is pressure welding pad, and 2104 is laser fuse, and 2105 is passivation layer;
Step 2002: at the surface-coated photoresist of the passivation layer of deposit; As shown in figure 22, be the half-finished schematic diagram of integrated circuit after coating photoresist, wherein 2201 is photoresist;
Step 2003: the photoresist being removed the first predeterminable area by graphical treatment technique, wherein the first predeterminable area is positioned at the region at laser fuse place; As shown in figure 23, for remove the first predeterminable area photoresist after the half-finished schematic diagram of integrated circuit;
Step 2004: the partial deactivation layer being removed the first predeterminable area by etching technics, forms the first passivation layer window; As shown in figure 24, for forming the half-finished schematic diagram of integrated circuit after the first passivation layer window, wherein 2401 is the first passivation layer window;
Step 2005: remove the remaining photoresist of integrated circuit surface of semi-finished after formation first passivation layer window, the integrated circuit surface of semi-finished after formation first passivation layer window applies photoresist again; As shown in figure 25, for again applying the half-finished schematic diagram of integrated circuit after photoresist 2501;
Step 2006: removed the photoresist again applying half-finished second predeterminable area of integrated circuit of photoresist by graphical treatment technique, wherein the second predeterminable area is positioned at the region at pressure welding pad place; As shown in figure 26, for remove the second predeterminable area photoresist after the half-finished schematic diagram of integrated circuit;
Step 2007: the totally inactivating layer being removed the second predeterminable area by etching technics, forms the second passivation layer window; As shown in figure 27, for forming the half-finished schematic diagram of integrated circuit after the second passivation layer window, wherein 2701 is the second passivation layer window;
Step 2008: remove the residue photoresist covered in passivation layer surface, forms the integrated circuit comprising pressure welding pad and laser fuse; As shown in figure 16, for comprising the schematic diagram of the integrated circuit of pressure welding pad and laser fuse.
Wherein, the thickness of the passivation layer of deposit in step 2001, the composition material according to passivation layer is determined, the thickness of the passivation layer that different materials is formed is different.As: when passivation layer comprises silicon oxide layer and silicon nitride layer, the thickness of silicon oxide layer is about 2000 dust ~ 10000 dusts, and the thickness of silicon nitride layer is also about 2000 dust ~ 10000 dusts, and silicon nitride layer covers on silicon oxide layer.
Removed the partial deactivation layer of the first predeterminable area in step 2004 by etching technics, specifically comprise: when passivation layer is made up of one deck Inorganic Non-metallic Materials, remove the passivation layer of setting thickness, leave the obvious passivation layer window marking on the integrated; When passivation layer is made up of multilayer Inorganic Non-metallic Materials, remove at least one deck Inorganic Non-metallic Materials layer, leave the obvious passivation layer window marking on the integrated.As: passivation layer comprises passivation layers, first passivation layer is silicon nitride layer, second passivation layer is silicon oxide layer, silicon nitride layer covers on silicon oxide layer, removed whole silicon nitride layers of the first predeterminable area by etching technics, or remove whole silicon nitride layer of the first predeterminable area and the silicon oxide layer of segment thickness by etching technics;
Pressure welding pad and laser fuse are mostly superposed by more metal layers and are formed, thickness is about 5000 dust ~ 40000 dusts, wherein the metal level of the superiors is titanium nitride metal layer, because the fusing point of titanium nitride is higher, and stable chemical nature, the qualification rate of " routing " technique of integrated antenna package is easily caused to decline, therefore in step 2006, when being positioned at the totally inactivating layer of second predeterminable area in the region at pressure welding pad place by etching technics removal, over etching technique is adopted to remove the totally inactivating layer of the second predeterminable area, and second titanium nitride layer on pressure welding pad surface of predeterminable area.Preferably, dry etching is adopted to remove passivation layer and titanium nitride layer.As: the gross thickness of passivation layer is 10000 dusts, and the etch amount of setting etching technics is 30000 dusts, to remove the totally inactivating layer of the second predeterminable area, and the titanium nitride layer on the pressure welding pad surface of the second predeterminable area.
And the totally inactivating layer of the second predeterminable area is removed in step 2007 by etching technics, because the first passivation layer window is covered by photoresist, when therefore the passivation layer in the second predeterminable area being etched, can not impact the residue passivation layer in the first passivation layer window and laser fuse.
As shown in figure 28, for comprising the schematic diagram of the another kind of manufacture method of the integrated circuit of laser fuse in the embodiment of the present invention, wherein passivation layer comprises two-layer, silicon oxide layer and silicon nitride layer, the manufacture method of the integrated circuit of the passivation layer of other types is similar with it, does not repeat them here.The method comprises:
Step 2801: form dielectric layer on underlay substrate;
Step 2802: form pressure welding pad and laser fuse on dielectric layer;
Step 2803: the integrated circuit semi-finished product after forming pressure welding pad and laser fuse first deposit one deck silica, then deposits one deck silicon nitride, forms passivation layer;
Step 2804: apply one deck photoresist on the integrated circuit semi-finished product forming passivation layer;
Step 2805: carry out graphical treatment to the integrated circuit semi-finished product of coating photoresist, remove the photoresist in the first predeterminable area, wherein the first predeterminable area is positioned at the region at laser fuse place;
Step 2806: remove whole silicon nitride layer of the first predeterminable area and the silicon oxide layer of segment thickness by etching technics, form the first passivation layer window;
Step 2807: remove remaining photoresist on integrated circuit semi-finished product;
Step 2808: the integrated circuit semi-finished product after removing photoresist apply one deck photoresist again;
Step 2809: again applying the integrated circuit surface of semi-finished of one deck photoresist, removed the photoresist of the second predeterminable area by graphical treatment technique, wherein the second predeterminable area is positioned at the region at pressure welding pad place;
Step 2810: the totally inactivating layer being removed the second predeterminable area by etching technics, forms the second passivation layer window;
Step 2811: remove the residue photoresist covered in passivation layer surface, forms the integrated circuit comprising pressure welding pad and laser fuse.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. comprise a manufacture method for the integrated circuit of laser fuse, it is characterized in that, the method comprises:
Deposit passivation layer on the integrated circuit semi-finished product comprising pressure welding pad and laser fuse;
At the surface-coated photoresist of described passivation layer;
Removed the photoresist of the first predeterminable area by graphical treatment technique, described first predeterminable area is positioned at the region at described pressure welding pad place;
Removed the totally inactivating layer of the first predeterminable area by etching technics, form the first passivation layer window;
Removed the photoresist of the second predeterminable area by graphical treatment technique, described second predeterminable area is positioned at the region at described laser fuse place;
Removed the partial deactivation layer of the second predeterminable area by etching technics, form the second passivation layer window;
Remove the residue photoresist covered in described passivation layer surface, form the integrated circuit comprising pressure welding pad and laser fuse.
2. the method for claim 1, is characterized in that, after described formation first passivation layer window, before being removed the photoresist of the second predeterminable area, comprising by graphical treatment technique:
Remove remaining photoresist on the integrated circuit semi-finished product after formation first passivation layer window;
Integrated circuit semi-finished product after described removal photoresist apply one deck photoresist again.
3. method as claimed in claim 2, it is characterized in that, the described photoresist being removed the second predeterminable area by graphical treatment technique, being comprised:
The photoresist of half-finished second predeterminable area of integrated circuit of one deck photoresist is again applied described in being removed by graphical treatment technique.
4. the method for claim 1, is characterized in that, the described photoresist being removed the second predeterminable area by graphical treatment technique, being comprised:
After removing formation first passivation layer window by graphical treatment technique the photoresist of half-finished second predeterminable area of integrated circuit.
5. the method for claim 1, is characterized in that, described passivation layer comprises the first passivation layer and the second passivation layer, and wherein the first passivation layer covers on the second passivation layer;
The partial deactivation layer of described removal second predeterminable area, comprising:
The thickness of the partial deactivation layer of the second predeterminable area removed is not less than the thickness of described first passivation layer.
6. comprise a manufacture method for the integrated circuit of laser fuse, it is characterized in that, the method comprises:
Deposit passivation layer on the integrated circuit semi-finished product comprising pressure welding pad and laser fuse;
At the surface-coated photoresist of described passivation layer;
Removed the photoresist of the first predeterminable area by graphical treatment technique, described first predeterminable area is positioned at the region at described laser fuse place;
Removed the partial deactivation layer of the first predeterminable area by etching technics, form the first passivation layer window;
Remove the remaining photoresist of integrated circuit surface of semi-finished after formation first passivation layer window, the integrated circuit surface of semi-finished after described first passivation layer window of formation applies photoresist again;
Removed the photoresist again applying half-finished second predeterminable area of integrated circuit of photoresist by graphical treatment technique, described second predeterminable area is positioned at the region at described pressure welding pad place;
Removed the totally inactivating layer of the second predeterminable area by etching technics, form the second passivation layer window;
Remove the residue photoresist covered in described passivation layer surface, form the integrated circuit comprising pressure welding pad and laser fuse.
7. method as claimed in claim 6, it is characterized in that, described passivation layer comprises the first passivation layer and the second passivation layer, and wherein the first passivation layer covers on the second passivation layer;
The partial deactivation layer of described removal first predeterminable area, comprising:
The thickness of the partial deactivation layer of the first predeterminable area removed is not less than the thickness of described first passivation layer.
8. comprise an integrated circuit for laser fuse, it is characterized in that, this integrated circuit comprises underlay substrate, dielectric layer, passivation layer, the first passivation layer window, the second passivation layer window, pressure welding pad and laser fuse;
Described dielectric layer covers on described underlay substrate, and described pressure welding pad and laser fuse are positioned on described dielectric layer;
Described first passivation layer window is positioned on described pressure welding pad, and described second passivation layer window is positioned at the region at described laser fuse place;
Described passivation layer covers the region outside described first passivation layer window;
Passivation layer thickness in described second passivation layer window is less than the passivation layer thickness in the region outside described second passivation layer window.
9. integrated circuit as claimed in claim 8, it is characterized in that, described passivation layer comprises the first passivation layer and the second passivation layer, and wherein the first passivation layer covers on the second passivation layer;
Passivation layer thickness in described second passivation layer window is not more than the thickness of described second passivation layer.
10. integrated circuit as claimed in claim 8, it is characterized in that, the size of described first passivation layer window is less than the size of described pressure welding pad, and the size of described second passivation layer window is greater than the size of described laser fuse.
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| CN201310516555.7A CN104576603A (en) | 2013-10-28 | 2013-10-28 | Integrated circuit including laser fuse wire and manufacturing method thereof |
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| CN201310516555.7A CN104576603A (en) | 2013-10-28 | 2013-10-28 | Integrated circuit including laser fuse wire and manufacturing method thereof |
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| CN106876326A (en) * | 2017-02-14 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Integrated circuit with laser fuse and forming method thereof |
| CN108417558A (en) * | 2018-05-10 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | Fuse-wires structure and forming method thereof |
| CN108878404A (en) * | 2018-06-29 | 2018-11-23 | 上海华虹宏力半导体制造有限公司 | Chip Internal fuse structure |
| CN109830459A (en) * | 2019-01-28 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of forming method of fuse-wires structure |
| CN109887901A (en) * | 2019-02-27 | 2019-06-14 | 上海华虹宏力半导体制造有限公司 | A method of avoid metal fuse by over etching |
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Application publication date: 20150429 |