CN104659024A - Integrated circuit packaging method - Google Patents
Integrated circuit packaging method Download PDFInfo
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- CN104659024A CN104659024A CN201510080770.6A CN201510080770A CN104659024A CN 104659024 A CN104659024 A CN 104659024A CN 201510080770 A CN201510080770 A CN 201510080770A CN 104659024 A CN104659024 A CN 104659024A
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- metal
- passivation layer
- integrated circuit
- packing
- deposit
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Abstract
The invention discloses an integrated circuit packaging method which comprises the following steps: step 1, thinner top metal is deposited, and a passivation layer PAD window is defined and opened through photoetching after the passivation layer is formed; step 2, a metal layer is deposited again; and step 3, metal except the PAD window on the passivation layer is removed. The metal strength in a PAD area is reinforced selectively, and the metal on other wired areas is kept thinner, so that the problem of cracking of metal in the PAD area due to packing wire bonding stress is solved under the condition that the wiring density is not influenced.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, refer to a kind of method for packing of integrated circuit especially.
Background technology
In current technique, integrated circuit (IC)-components, when encapsulating, connects integrated circuit PAD metal and housing metal pins by gold thread.During packaging and routing, metal wire has larger action of compressive stress on the metal level at the PAD place of chip.As shown in Figure 1, if metal level is thinner, very likely when packaging and routing, stress makes metal level split, and time serious, the level below metal level can be made also to split, affect properties of product.
For avoiding metal to split, method general is at present the thickness increasing metal, and such as the current metal layer thickness of BCD700V technique adopts 1.5 μm.But after increase metal thickness, just need thicker photoresist to stop when metal etch, photoresist is thicker, and the resolution of its photoetching, etching technics is poorer, cause thicker metal live width and spacing needs very large.After metal live width and spacing increase, wiring density will reduce greatly, thus reduce integrated level, add step line complexity.Such as current BCD700V technique 1.5 μm of top-level metallic characteristic size rules are decided to be 2.5 μm of live widths and 2.0 μm of wire distribution distances, and size is larger.Keep certain wiring density, additionally need to increase metal and through hole level toward contact, even need the metal level of increase extra 3rd layer or the 4th layer, add process costs.
Summary of the invention
Technical problem to be solved by this invention is the method for packing providing a kind of integrated circuit, solves the problem that PAD district metal stresses causes splitting.
For solving the problem, the method for packing of integrated circuit of the present invention, comprises:
The first step, top-level metallic deposit, and open passivation layer PAD window by lithographic definition after the passivation layer is formed;
Second step, then deposit layer of metal;
3rd step, removes the metal beyond PAD window on passivation layer.
Further, in the described first step, the thickness of top-level metallic deposit is 0.2 ~ 2.0 μm.
Further, the metal of deposit in described second step is aluminium/copper, or is copper, and the thickness of deposit is 0.5 ~ 5.0 μm.
Further, in described 3rd step, the removal of metal uses and anti-carves and add CMP, or photoetching and etching technics.
Further, if use photoetching to add etching technics, adopt the identical mask plate of passivation layer to form the contrary photoresist of window features with passivation layer, if the positive photoetching rubber used when namely the first step opens passivation layer PAD window, then use negative photoresist when the 3rd step removes metal; Or reuse independent mask plate.
Described method for packing carries out after passivation layer completes, and can complete, or complete in chip packaging factory at chip manufacturing factory.
Integrated circuit packaging method of the present invention, thicker metal level is realized selectively in packaging and routing district (PAD district), other regions keep thinner metal layer thickness, do not affect the wiring density of circuit, solve the metal problems of crack that packaging and routing causes.
Accompanying drawing explanation
Fig. 1 is traditional integrated antenna package cutaway view.
Fig. 2 ~ 4 are present invention process step schematic diagrames.
Fig. 5 is present invention process flow chart.
Description of reference numerals
1 is substrate, and 2 is extensions, and 3 is P traps, and 4 is N traps, and 5 is passivation layers, and 6 is top-level metallics, and 7 is metals.
Embodiment
Integrated circuit packaging method of the present invention, comprises following steps:
The first step, the top-level metallic of deposit layer on silicon chip, thickness is 0.2 ~ 2.0 μm, and opens passivation layer PAD window by lithographic definition after the passivation layer is formed.As shown in Figure 2.
Second step, re-use the metal that CVD mode deposit one deck is thicker, thickness is 0.5 ~ 5.0 μm, and material is aluminium/copper, or is copper, or is other materials.As shown in Figure 3.
3rd step, removes the metal beyond PAD window on passivation layer.Remove technique and can add CMP for anti-carving, or photoetching and etching technics.If use photoetching to add etching technics, adopt the identical mask plate of passivation layer to form the contrary photoresist of window features with passivation layer, if the positive photoetching rubber used when namely the first step opens passivation layer PAD window, then use negative photoresist when the 3rd step removes metal; If the negative photoresist that the first step uses when opening passivation layer PAD window, then use positive photoetching rubber when the 3rd step removes metal.Or reuse independent mask plate.As shown in Figure 4, the PAD district metal thickness finally formed, higher than other wiring region, enhances PAD district intensity, is unlikely to the problem Er Shi PAD district metal breakage due to stress when packaging and routing while keeping higher wiring density to improve integrated level.Present invention process flow process can be carry out after whole chip technology and passivation layer complete.Can complete at chip manufacturing factory, also can encapsulate factory in chip testing and complete.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a method for packing for integrated circuit, is characterized in that: comprise following steps:
The first step, top-level metallic deposit, and open passivation layer PAD window by lithographic definition after the passivation layer is formed;
Second step, then deposit layer of metal;
3rd step, removes the metal beyond PAD window on passivation layer.
2. the method for packing of integrated circuit as claimed in claim 1, it is characterized in that: the described first step, the thickness of top-level metallic deposit is 0.2 ~ 2.0 μm.
3. the method for packing of integrated circuit as claimed in claim 1, it is characterized in that: described second step, the metal of deposit is aluminium/copper, or is copper; The metal thickness of deposit is 0.5 ~ 5.0 μm.
4. the method for packing of integrated circuit as claimed in claim 1, is characterized in that: described 3rd step, and the removal of described metal uses to anti-carve and adds CMP, or photoetching and etching technics.
5. the method for packing of integrated circuit as claimed in claim 4, it is characterized in that: if use photoetching to add etching technics, the identical mask plate of passivation layer is adopted to form the contrary photoresist of window features with passivation layer, the positive photoetching rubber used when namely if the first step opens passivation layer PAD window, then use negative photoresist when the 3rd step removes metal; Or reuse independent mask plate.
6. the method for packing of integrated circuit as claimed in claim 1, is characterized in that: described method for packing carries out after passivation layer completes, and can complete, or complete in chip packaging factory at chip manufacturing factory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510080770.6A CN104659024A (en) | 2015-02-15 | 2015-02-15 | Integrated circuit packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510080770.6A CN104659024A (en) | 2015-02-15 | 2015-02-15 | Integrated circuit packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104659024A true CN104659024A (en) | 2015-05-27 |
Family
ID=53249970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510080770.6A Pending CN104659024A (en) | 2015-02-15 | 2015-02-15 | Integrated circuit packaging method |
Country Status (1)
| Country | Link |
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| CN (1) | CN104659024A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511350A (en) * | 2018-05-14 | 2018-09-07 | 深圳市欧科力科技有限公司 | A kind of packaging method and power device of power device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044457A (en) * | 2010-01-28 | 2011-05-04 | 中颖电子股份有限公司 | Method for manufacturing metal bonding pad and corresponding metal bonding pad structure |
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
-
2015
- 2015-02-15 CN CN201510080770.6A patent/CN104659024A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044457A (en) * | 2010-01-28 | 2011-05-04 | 中颖电子股份有限公司 | Method for manufacturing metal bonding pad and corresponding metal bonding pad structure |
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511350A (en) * | 2018-05-14 | 2018-09-07 | 深圳市欧科力科技有限公司 | A kind of packaging method and power device of power device |
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Application publication date: 20150527 |