CN109037160A - Semiconductor device packages - Google Patents

Semiconductor device packages Download PDF

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Publication number
CN109037160A
CN109037160A CN201810154963.5A CN201810154963A CN109037160A CN 109037160 A CN109037160 A CN 109037160A CN 201810154963 A CN201810154963 A CN 201810154963A CN 109037160 A CN109037160 A CN 109037160A
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CN
China
Prior art keywords
support membrane
substrate
insulating layer
interconnection structure
semiconductor device
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Application number
CN201810154963.5A
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Chinese (zh)
Inventor
陈建桦
陈明宏
施旭强
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN109037160A publication Critical patent/CN109037160A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Semiconductor device packages include substrate, the first insulating layer, support membrane and interconnection structure.The substrate has the first side wall, first surface and the second surface opposite with the first surface.First insulating layer is on the first surface of the substrate and has second sidewall.First insulating layer has first surface and adjacent to the substrate and the second surface opposite with the first surface of first insulating layer.The support membrane is on the second surface of the substrate and has third side wall.The support membrane has the first surface and the second surface opposite with the first surface of the support membrane adjacent to the substrate.The interconnection structure extends to the second surface of the support membrane by first insulating layer and the support membrane from the first surface of first insulating layer.The interconnection structure covers first, second and third side wall.

Description

Semiconductor device packages
Technical field
The present invention relates to a kind of semiconductor device packages and a kind of methods for manufacturing semiconductor device packages.Specifically, The present invention relates to a kind of semiconductor device packages, comprising wearing glass through-hole (TGV) for electric interconnection.
Background technique
The integrating passive device (IPD) of semiconductor device packages may include wearing glass through-hole (TGV) for electric interconnection. Drilling technique is for forming TGV in the glass substrate of relatively thick (for example, greater than about 300 microns (μm)).Support/protective film (for example, aginomoto accumulating film (ABF)) can be used for handling the glass substrate of relatively thin (for example, being less than about 300 μm).In such feelings Under condition, ABF film can be coated to the two sides of glass substrate and can execute drilling operation twice on substrate to form TGV.However, Drilling operation can damage glass substrate, especially relatively thin glass substrate.In addition, the flatness of ABF is not good enough, and may Negatively affect subsequent process (for example, the process for forming capacitor).
Summary of the invention
In one or more embodiments, semiconductor device packages include substrate, the first insulating layer, support membrane and mutually connection Structure.The substrate has the first side wall, first surface and the second surface opposite with the first surface.First insulating layer On the first surface in the substrate and there is second sidewall.First insulating layer has first surface and neighbouring In the substrate and the second surface opposite with the first surface of first insulating layer.The support membrane is in the lining On the second surface at bottom and there is third side wall.The support membrane have adjacent to the substrate first surface and with The opposite second surface of the first surface of the support membrane.The interconnection structure passes through first insulating layer and the branch Support film extends to the second surface of the support membrane from the first surface of first insulating layer.The interconnection structure Cover first, second and third side wall.
In one or more embodiments, semiconductor device packages include substrate, the first support film, the second support membrane and interconnection Structure.The substrate has the first side wall, first surface and the second surface opposite with the first surface.First support Film is on the second surface of the substrate and has bottom surface and second sidewall.Second support membrane is in institute It states on the first surface of substrate and there is top surface and third side wall.The interconnection structure is supported by described first Film and second support membrane extend to the bottom surface of first support membrane from the top surface of second support membrane.Institute It states interconnection structure and covers first, second and third side wall.
In one or more embodiments, the method for manufacturing semiconductor device packages includes to provide substrate, the substrate With side wall, first surface and the second surface opposite with the first surface；Support membrane is placed in described in the substrate On second surface；First insulating layer is placed on the first surface of the substrate；Formation penetrates the substrate, described The through-hole of one insulating layer and the support membrane, wherein the through-hole is by the side wall of the substrate, first insulating layer The side wall of side wall and the support membrane is limited or is defined；And placement covers the substrate, first insulating layer and the support The interconnection structure of the side wall of film.
In one or more embodiments, the method for manufacturing semiconductor device packages includes to provide substrate, the substrate With side wall, first surface and the second surface opposite with the first surface；First support membrane is placed in the substrate On the second surface；Second support membrane is placed on the first surface of the substrate；Formation penetrates the substrate, institute State the through-hole of the first support membrane and second support membrane, wherein the through-hole by the substrate the side wall, described first The side wall of the side wall of support membrane and second support membrane is limited or is defined；And placement covers the substrate, first support The interconnection structure of the side wall of film and second support membrane.
Detailed description of the invention
Fig. 1 is the sectional view of semiconductor device packages according to some embodiments of the present invention.
Fig. 2A is the sectional view of semiconductor device packages according to some embodiments of the present invention.
Fig. 2 B is the sectional view of semiconductor device packages according to some embodiments of the present invention.
Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D, Fig. 3 E, Fig. 3 F and Fig. 3 G illustrate manufacture figure according to some embodiments of the present invention The method of 1 semiconductor device packages.
Fig. 4 A, Fig. 4 B, Fig. 4 C, Fig. 4 D, Fig. 4 E, Fig. 4 F and Fig. 4 G illustrate that manufacture according to some embodiments of the present invention is another The method of semiconductor device encapsulation.
Fig. 5 A, Fig. 5 B, Fig. 5 C, Fig. 5 D, Fig. 5 E, Fig. 5 F, Fig. 5 G and Fig. 5 H illustrate according to some embodiments of the present invention The method for manufacturing the semiconductor device packages of Fig. 2A and Fig. 2 B.
Same or similar element is indicated using common reference numerals through schema and detailed description.The embodiment of the present invention By from obtained in conjunction with attached drawing it is described in detail below in become more apparent from.
Specific embodiment
Description is for providing the technology of the device with reduced package size in the present invention.Specifically, the present invention relates to And a kind of semiconductor device package, comprising wearing glass through-hole (TGV) structure for the improved of electric interconnection.
Unless specified otherwise herein, otherwise for example "upper", "lower", " upward ", "left", "right", " downward ", " top ", " bottom ", The spatial descriptions such as " vertical ", "horizontal", " side ", " being higher than ", " being lower than ", " top ", " top ", " lower section " are relative to schema Shown in orientation instruction.It should be understood that spatial description used herein is and institute herein for purposes of illustration The actual implementation scheme of the structure of description can by it is any orientation or in a manner of be spatially arranged, restrictive condition be reality of the invention The advantages of applying is will not therefore to arrange and have deviation.
Fig. 1 is the sectional view of semiconductor device packages 1 according to some embodiments of the present invention.Semiconductor device packages 1 Comprising substrate 10, passive block layer 30, insulating layer 40 and 50, support membrane 42, interconnection structure 80 and 83, conducting connecting part 78, and Patterned conductive layer 82,84 and 88.Insulating layer 40 may include passivation layer 40, in addition the passivation layer is also supporting layer.
In one or more embodiments, substrate 10 includes glass, silicon, silica (SiO2), or combinations thereof.One or more In a embodiment, the thickness of substrate 10 is in the range of about 100 microns (μm) to about 200 μm.In one or more embodiments, it serves as a contrast The thickness at bottom 10 is less than about 300 μm.In some embodiments, substrate 10 is glass substrate and due to more according to the present invention The manufacturing process of embodiment, for rms surface roughness, the surface roughness of the glass substrate is less than about 1 μm, example It is such as from about 900 nanometers (nm) or smaller, or about 800nm or smaller.Substrate 10 has side wall 101s.Substrate 10 has top surface 101 and the surface 102 opposite with surface 101.
In one or more embodiments, substrate 10 may include be embedded in substrate 10 one or more active blocks (for example, Integrated circuit (IC)), and/or one or more active blocks being placed on substrate 10.In one or more embodiments, substrate 10 It may include one or more passive blocks being placed on substrate 10 (for example, passive block layer 30 as shown in Figure 1).Patterning Conductive layer 82 and 84 and insulating layer 40 form passive block layer 30.Passive block layer 30 may include capacitor 30.Passive block Layer 30 is connected to interconnection structure 80 by interconnection structure 83.For example, patterned conductive layer 82,84 and 88 may include copper (Cu) or other metals or metal alloy or other conductive materials.Patterned conductive layer 82,84 and 88 may include allowing in shape It is for metal-insulator at the seed layer or patterned conductive layer 82 and 84 that are electroplated during patterned conductive layer 82,84 and 88 The structure of body-metal (MIM).Patterned conductive layer 82 and 84 can be handled or be disposed by sputtering process.
Insulating layer 40 is placed on the surface 101 of substrate 10.Insulating layer 40 has top surface 401 and adjacent to substrate 10 And the surface 402 opposite with top surface 401.Insulating layer 40 has side wall 401s.In some embodiments, insulating layer 40 includes Suitable insulating materials.For example, insulating layer 40 may include silicon nitride (SiNx) film；However, can additionally or alternatively use Other suitable materials.In one or more embodiments, the thickness of insulating layer 40 is in the range of about 8 μm to about 10 μm.Support Film 42 is placed on the surface 102 of substrate 10.Support membrane 42 has side wall 421s.Support membrane 42 has the table adjacent to substrate 10 Face 421 and the surface 422 opposite with the surface 421 of support membrane 42.Support membrane 42 may include polymer material；In addition however, can be Or alternatively use other suitable materials.Insulating layer 40 has top surface 401, and interconnection structure 80 covers insulating layer 40 Top surface 401.Support membrane 42 has bottom surface 422, and interconnection structure 80 covers the bottom surface of support membrane 42 422.Interconnection structure 80 extends to the surface of support membrane 42 by insulating layer 40 and support membrane 42 from the surface of insulating layer 40 401 422.Interconnection structure 80 covers side wall 101s, 401s and 421s.Interconnection structure 80 on the two sides of substrate 10 can pass through single electricity Plating is formed or placement, and the process can be simplified.
Interconnection structure 80 extends to the surface of substrate 10 by insulating layer 40 and support membrane 42 from the surface of substrate 10 101 102.Interconnection structure 80 covers side wall 101s, 401s and 421s.Interconnection structure 80 is connected to patterning by interconnection structure 83 and leads Electric layer 82.For example, interconnection structure 80 and 83 may include copper or other metals or metal alloy or other conductive materials. Interconnection structure 80 and 83 may include the seed layer for allowing to be electroplated during forming interconnection structure 80 and 83.
Insulating layer 50 penetrates substrate 10, insulating layer 40 and support membrane 42.Insulating layer 50 covers interconnection structure 80, insulating layer 40 Top surface 401 a part and support membrane 42 bottom surface 422 a part.In some embodiments, insulating layer 50 Material may differ from the material of insulating layer 40.Insulating layer 50 may include aginomoto accumulating film (ABF)；However, can in addition or replace Generation ground uses other suitable materials.In some embodiments, it can remove the ABF on the top surface 101 of substrate 10 to promote The formation (for example, for purpose of more preferably flatness) of integrating passive device IPD.
Conducting connecting part 78 is connected to patterned conductive layer 88.Conducting connecting part 78 may include solder ball.In some implementations In example, the insulating materials of insulating layer 40 may differ from the insulating materials of support membrane 42.Insulating layer 50 is filled into through-hole 811. Insulating layer 50 is surrounded by interconnection structure 80.Through-hole 70 penetrates substrate 10, insulating layer 40 and support membrane 42.In some embodiments, Through-hole 70 is by sandblast technology, rather than drilling technique is formed.In the manufacturing process by replacing drilling technique with sandblast technology Period can avoid relatively thin (for example, glass) substrate 10 of damage.
Fig. 2A is the sectional view of semiconductor device packages 2 according to some embodiments of the present invention.Semiconductor device packages 2 Similar to the semiconductor device packages 1 of Fig. 1, and the component of identical number is no longer described relative to Fig. 2A.Semiconductor device envelope It fills 2 and includes substrate 10,30 (not shown) of passive block layer, insulating layer 50, support membrane 42 and 44, interconnection structure 80, conductive connection Part 78 and patterned conductive layer 88.
In one or more embodiments, substrate 10 includes glass, silicon, silica (SiO2), or combinations thereof.One or more In a embodiment, the thickness of substrate 10 is in the range of about 100 μm to about 200 μm.In one or more embodiments, substrate 10 Thickness is less than about 300 μm.In some embodiments, substrate 10 is glass substrate and due to according to some embodiments of the present invention Manufacturing process, for rms surface roughness, the surface roughness of the glass substrate is less than about 1 μm, for example, about 900nm or smaller, or about 800nm or smaller.Substrate 10 has side wall 101s.Substrate 10 has top surface 101 and and surface 101 opposite surfaces 102.
In one or more embodiments, substrate 10 may include be embedded in substrate 10 one or more active blocks (for example, ), and/or one or more active blocks for being placed on substrate 10 IC.In one or more embodiments, substrate 10 may include placement In the passive block layer 30 on substrate 10.For example, patterned conductive layer 88 may include that copper or other metals or metal close Gold or other conductive materials.Patterned conductive layer 88 may include the crystal seed for allowing to be electroplated during forming patterned conductive layer 88 Layer.Passive block layer 30 is connected to interconnection structure 80.
Support membrane 42 is placed on the surface 102 of substrate 10.Support membrane 42 has side wall 421s.Support membrane 42 has neighbouring In the surface of substrate 10 421 and the surface 422 opposite with the surface 421 of support membrane 42.Support membrane 42 may include polymer material； However, other suitable materials can be used additionally or alternatively.Support membrane 44 is placed on the surface 101 of substrate 10.Support membrane 44 have side wall 441s.Support membrane 44 has surface 441 and adjacent to substrate 10 and the table opposite with the surface of support membrane 44 441 Face 442.Support membrane 44 may include polymer material；However, other suitable materials can be used additionally or alternatively.In some realities It applies in example, the insulating materials of support membrane 42 and support membrane 44 is identical.
Interconnection structure 80 extends to support membrane 42 from the top surface 441 of support membrane 44 by support membrane 42 and support membrane 44 Bottom surface 422.Interconnection structure 80 covers side wall 101s, 421s and 441s.The top of the covering support membrane 44 of interconnection structure 80 The bottom surface 422 of surface 441 and support membrane 42.
A part of insulating layer 50 penetrates substrate 10, support membrane 42 and support membrane 44.The covering of insulating layer 50 interconnection structure 80, A part of the bottom surface 422 of a part and support membrane 42 of the top surface 441 of support membrane 44.In some embodiments, The material of insulating layer 50 may differ from the material of insulating layer 40.Insulating layer 50 may include ABF；However, can additionally or alternatively make With other suitable materials.Interconnection structure 80 includes or defines through-hole 811.Insulating layer 50 is filled into through-hole 811.Insulating layer Therefore 50 a part is surrounded by interconnection structure 80.Through-hole 70 penetrates substrate 10 and support membrane 42 and 44.In some embodiments, Through-hole 70 is by sandblast technology, rather than drilling technique is formed.
Fig. 2 B is the sectional view of semiconductor device packages 3 according to some embodiments of the present invention.Semiconductor device packages 3 Similar to the semiconductor device packages 2 of Fig. 2A, and the component of identical number is no longer described relative to Fig. 2 B.In fig. 2b, mutually Link structure 80 and does not include through-hole 811.Insulating layer 50 covers the surface of interconnection structure 80, and is not surrounded by interconnection structure 80.
Fig. 3 A to 3G illustrates the method for the semiconductor device packages 1 of manufacture Fig. 1 in accordance with some embodiments.With reference to Fig. 3 A, Substrate 10 is provided.Substrate 10 has top surface 101 and the surface 102 opposite with surface 101.Substrate 10 include glass, silicon, SiO2, or combinations thereof.In some embodiments, substrate 10 is made of glass material, and the thickness of substrate 10 is less than about 300 μ m.Support membrane 42 is placed on the surface 102 of substrate 10.Support membrane 42 may include polymer material；However, can be additionally or alternatively Ground uses other suitable materials.
With reference to Fig. 3 B, patterned conductive layer 82 is placed on the top surface 101 of substrate 10.With reference to Fig. 3 C, insulating layer 40 First layer be placed on the surface 101 of substrate 10.For example, the material of insulating layer 40 may include SiNxFilm；However, can be another Other suitable materials are used outside or alternatively.Patterned conductive layer 84 is placed on the first layer of insulating layer 40.Patterning is led Electric layer 82 and 84 and insulating layer 40 form passive block layer 30.Passive block layer 30 may include capacitor 30.For example, scheme Case conductive layer 82 and 84 may include copper or other metals or metal alloy or other conductive materials.Patterned conductive layer 82 And 84 may include allow formed patterned conductive layer 82 and 84 during be electroplated seed layer；Or patterned conductive layer 82 and 84 is Structure for MIM.Patterned conductive layer 82 and 84 can be handled by sputtering process.
With reference to Fig. 3 D, the second layer of insulating layer 40 is placed on the first layer of insulating layer 40.Through-hole 411 and 412 is formed in In insulating layer 40.With reference to Fig. 3 E, in some embodiments, substrate 10, insulating layer 40 and support membrane 42 are removed by sandblast technology A part to form through-hole 70.Through-hole 70 penetrates substrate 10, insulating layer 40 and support membrane 42.In some embodiments, through-hole 70 by sandblast technology, rather than drilling technique is formed.During the manufacturing process by replacing drilling technique with sandblast technology, It can avoid relatively thin (for example, glass) substrate 10 of damage.Through-hole 70 includes the side wall of the side wall 101s of substrate 10, insulating layer 40 The side wall 421s of 401s and support membrane 42.Due to use single drill or sandblasting, formed IPD (such as passive block layer 30) it Form through-hole (for example, TGV) 70 afterwards to improve technique.
With reference to Fig. 3 F, interconnection structure 83 is disposed to the patterned conductive layer 82 of covering exposure.Interconnection structure 80 is through disposing To cover the side wall 101s, the side wall 401s of insulating layer 40 and the side wall 421s of support membrane 42 of substrate 10.Interconnection structure 80 also covers A part of the bottom surface 422 on the surface 401 and support membrane 42 of lid insulating layer 40.Conductive structure on the two sides of substrate 10 (for example, interconnection structure 80) can be electroplated to be formed or be disposed by single, and the process can be simplified.Patterned conductive layer 88 are placed on the surface 401 of insulating layer 40.For example, patterned conductive layer 88 and interconnection structure 83 may include copper or its Its metal or metal alloy or other conductive materials.Patterned conductive layer 88 and interconnection structure 83 may include allowing in formation figure The seed layer being electroplated during case conductive layer 88 and interconnection structure 83.
With reference to Fig. 3 G, insulating layer 50 be disposed to covering interconnection structure 80, insulating layer 40 top surface 401 a part And a part of the bottom surface 422 of support membrane 42.Insulating layer 50 is filled in through-hole 811.Insulating layer 50 may include ABF； However, other suitable materials can be used additionally or alternatively.Conducting connecting part 78 is disposed to be connected to patterned conductive layer 88.Conducting connecting part 78 may include solder ball.Next, obtaining the semiconductor device packages 1 of Fig. 1.
Fig. 4 A to 4G illustrates the method for another semiconductor device packages 4 of manufacture according to some embodiments of the present invention.Ginseng Fig. 4 A is examined, substrate 10 is provided.Substrate 10 has top surface 101 and the surface 102 opposite with surface 101.Substrate 10 includes glass Glass, silicon, SiO2, or combinations thereof.In some embodiments, substrate 10 is made of glass material, and the thickness of substrate 10 is less than About 300 μm.Support membrane 42 is placed on the surface 102 of substrate 10.Support membrane 44 is placed on the surface 101 of substrate 10.Support Film 42 and 44 may include polymer material；However, other suitable materials can be used additionally or alternatively.
With reference to Fig. 4 B, patterned conductive layer 82 is placed on the surface 441 of support membrane 44.With reference to Fig. 4 C, insulating layer 40 First layer is placed on the surface 441 of support membrane 44.For example, the material of insulating layer 40 may include SiNxFilm；However, can be another Other suitable materials are used outside or alternatively.Patterned conductive layer 84 is placed on the first layer of insulating layer 40.Patterning is led Electric layer 82 and 84 and insulating layer 40 form passive block layer 30.Passive block layer 30 may include capacitor 30.For example, scheme Case conductive layer 82 and 84 may include copper or other metals or metal alloy or other conductive materials.Patterned conductive layer 82 And 84 may include allow formed patterned conductive layer 82 and 84 during be electroplated seed layer；Or patterned conductive layer 82 and 84 is Structure for MIM.Patterned conductive layer 82 and 84 can be handled by sputtering process.
With reference to Fig. 4 D, the second layer of insulating layer 40 is placed on the first layer of insulating layer 40.Through-hole 411 and 412 is formed in In insulating layer 40.With reference to Fig. 4 E, in some embodiments, one of substrate 10 and support membrane 42 and 44 is removed by sandblast technology Divide to form through-hole 70.In some embodiments, through-hole 70 penetrates substrate 10 and support membrane 42 and 44.In some embodiments, Through-hole 70 is by sandblast technology, rather than drilling technique is formed.In the manufacturing process by replacing drilling technique with sandblast technology Period can avoid relatively thin (for example, glass) substrate 10 of damage.Through-hole 70 includes side wall 101s, the insulating layer 40 of substrate 10 Side wall 401s, the side wall 441s of support membrane 44 and the side wall 421s of support membrane 42.
With reference to Fig. 4 F, interconnection structure 83 is disposed to the patterned conductive layer 82 of covering exposure.Interconnection structure 80 is through disposing To cover the side wall 101s of substrate 10, the side wall 401s of insulating layer 40, the side wall 441s of support membrane 44 and the side wall of support membrane 42 421s.Interconnection structure 80 also covers a part on the surface 401 of insulating layer 40 and the bottom surface 422 of support membrane 42.Patterning Conductive layer 88 is placed on the surface 401 of insulating layer 40.For example, patterned conductive layer 88 and interconnection structure 83 may include Copper or other metals or metal alloy or other conductive materials.Patterned conductive layer 88 and interconnection structure 83 may include allowing The seed layer being electroplated during forming patterned conductive layer 88 and interconnection structure 83.
With reference to Fig. 4 G, insulating layer 50 be disposed to covering interconnection structure 80, insulating layer 40 top surface 401 a part And a part of the bottom surface 422 of support membrane 42.Insulating layer 50 is filled in through-hole 811.Insulating layer 50 may include ABF； However, other suitable materials can be used additionally or alternatively.Conducting connecting part 78 is disposed to be connected to patterned conductive layer 88.Conducting connecting part 78 may include solder ball.Next, obtaining the semiconductor device packages 4 of Fig. 4 G.
Fig. 5 A, Fig. 5 B, Fig. 5 C, Fig. 5 D, Fig. 5 E, Fig. 5 F, Fig. 5 G and Fig. 5 H illustrate according to some embodiments of the present invention The method for manufacturing the semiconductor device packages 2 of Fig. 2A and the semiconductor device packages 3 of Fig. 2 B.With reference to Fig. 5 A, substrate 10 is provided.Lining Bottom 10 has top surface 101 and the surface 102 opposite with surface 101.Substrate 10 includes glass, silicon, SiO2, or combinations thereof. In some embodiments, substrate 10 is made of glass material, and the thickness of substrate 10 is less than about 300 μm.
With reference to Fig. 5 B, support membrane 42 is placed on the surface 102 of substrate 10, and support membrane 44 is placed in the table of substrate 10 On face 101.Support membrane 42 and 44 may include polymer material；However, other suitable materials can be used additionally or alternatively.Branch Supportting film 42 has surface 421 and the surface 422 opposite with surface 421.Support membrane 44 is opposite with surface 441 and with surface 441 Surface 442.
With reference to Fig. 5 C, in some embodiments, a part of substrate 10 and support membrane 42 and 44 is removed by sandblast technology To form through-hole 70.Through-hole 70 penetrates substrate 10 and support membrane 42 and 44.In some embodiments, through-hole 70 passes through sandblasting skill Art, rather than drilling technique is formed.Through-hole 70 includes the side wall 441s and support membrane 42 of the side wall 101s of substrate 10, support membrane 44 Side wall 421s.
With reference to Fig. 5 D, interconnection structure 80' is placed on the surface 441 of support membrane 44 and the surface 422 of support membrane 42.Interconnection Structure 80' also covers the side wall 421s of the side wall 101s of substrate 10, the side wall 441s of support membrane 44 and support membrane 42.Interconnection structure 80' may include seed layer.In some embodiments, interconnection structure 80' may include, for example, titanium-copper (Ti-Cu) alloy or another Suitable metal or metal alloy, or combinations thereof.
With reference to Fig. 5 E, a part of interconnection structure 80' is removed.Patterning photoresist layer 74 is placed in the surface of support membrane 44 In a part on the surface 422 of 441 a part and support membrane 42.In some embodiments, patterning photoresist layer 74 may include Positive photoresist, or can be formed by positive photoresist.
With reference to Fig. 5 F, increase the thickness of interconnection structure 80' by plating.After plating, interconnection structure 80 is obtained.Interconnection Structure 80 includes or defines through-hole 811.For example, interconnection structure 80 may include copper or other metals or metal alloy, or Other conductive materials.Interconnection structure 80 covers the top surface 441 of support membrane 44 and covers the bottom surface of support membrane 42 422。
With reference to Fig. 5 G, insulating layer 50 is filled in through-hole 811 and covers the top table of interconnection structure 80, support membrane 44 A part of the bottom surface 422 of a part and support membrane 42 in face 441.In some embodiments, insulating layer 50 may include ABF；However, other suitable materials can be used additionally or alternatively.Next, conducting connecting part 78 is placed in interconnection structure 80 On to obtain the semiconductor device packages 2 of Fig. 2A.
Fig. 5 H is referred to after the step in Fig. 5 F, if the through-hole 811 in Fig. 5 F is filled up completely by plating, Through-hole is not present in interconnection structure 80.Next, conducting connecting part 78 is placed on interconnection structure 80 to obtain partly leading for Fig. 2 B Body device encapsulation 3.
As used herein, term " substantially ", " substantially ", " essence " and " about " is for describing and explaining small change Change.When being used in combination with event or situation, the term can refer to the example that event or situation accurately occur and event or feelings The example that condition pole approximatively occurs.For example, when combination numerical value in use, term can refer to ± 10% less than or equal to numerical value Variation, for example, be less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, be less than or equal to ± 2%, Less than or equal to ± 1%, it is less than or equal to ± 0.5%, is less than or equal to ± 0.1% or is less than or equal to ± 0.05%.Cause This, the term with reference to two values " roughly equal " can refer to the ratio of two values between 0.9 and 1.1 and include 0.9 and 1.1.
In addition, sometimes herein with range format presentation amount, ratio and other numerical value.It should be understood that this range format is It uses, and should neatly understand in order to convenient and succinct, not only comprising being expressly specified as the numerical value of range limit, but also wrap Containing all individual numbers or the subrange being covered by within the scope of that, as explicitly specifying each numerical value and subrange.
If displacement between two surfaces is no more than 0.5 μm, is no more than 1 μm, is no more than 5 μm, being no more than 10 μm or not More than 15 μm, then it is assumed that the two surfaces or side are alignment.In the description of some embodiments, it is provided in another group The component of part "upper" can cover previous component directly on latter component (for example, with latter assemblies physical contact) the case where, with And one or more intermediate modules between previous component and latter component the case where.
Although having referred to the particular embodiment of the present invention describes and illustrate the present invention, these descriptions and explanation are not intended to limit The present invention.It will be understood by those skilled in the art that true essence of the invention as defined by the appended claims can not departed from In the case where mind and range, it is variously modified and replaces equivalent.The diagram may be not necessarily drawn to scale.Due to manufacture Technique and tolerance, the present invention in art recurring and physical device between difference may be present.The sheet of not certain illustrated may be present The other embodiments of invention.This specification and schema should be considered as illustrative and not restrictive.It can modify, so that special Shape, material, material composition, method or the technique of pledging love are suitable for target of the invention, spirit and scope.All such modifications are set Within the scope of the appended claims.Although method disclosed herein has referred to the specific operation being performed in a specific order Described, it should be appreciated that can combine, segment or resequence in the case where not departing from teachings of the present invention these operation with Form equivalent method.Therefore, unless special instructions herein, the order otherwise operated and grouping and the limitation of non-present invention.

Claims (20)

1. a kind of semiconductor device packages comprising:
Substrate, the substrate have the first side wall, first surface and the second surface opposite with the first surface；
First insulating layer, first insulating layer are on the first surface of the substrate and have second sidewall, Described in the first insulating layer have first surface and the first surface adjacent to the substrate and with first insulating layer Opposite second surface；
Support membrane, the support membrane is on the second surface of the substrate and has third side wall, wherein the branch Film is supportted with the first surface and the second surface opposite with the first surface of the support membrane adjacent to the substrate；And
Interconnection structure, the interconnection structure is by first insulating layer and the support membrane from described in first insulating layer First surface extends to the second surface of the support membrane, and the interconnection structure covers first, second and third side Wall.
2. semiconductor device packages according to claim 1, wherein the first surface of first insulating layer is top Portion surface and the interconnection structure cover the top surface of first insulating layer, and described the second of the support membrane Surface is the bottom surface that bottom surface and the interconnection structure cover the support membrane.
3. semiconductor device packages according to claim 2 further comprise penetrating the substrate, first insulation The second insulating layer of layer and the support membrane, wherein the second insulating layer covers the interconnection structure, first insulating layer The top surface a part and the support membrane the bottom surface a part.
4. semiconductor device packages according to claim 1 further comprise be placed in the substrate described first On surface and it is connected to the passive block layer of the interconnection structure.
5. semiconductor device packages according to claim 1, wherein the substrate includes glass material.
6. semiconductor device packages according to claim 1, wherein the thickness of the substrate is less than about 300 microns (μm).
7. semiconductor device packages according to claim 1, wherein first insulating layer include the first insulating materials and The support membrane includes the second insulating materials, and first insulating materials is different from second insulating materials.
8. a kind of semiconductor device packages comprising:
Substrate, the substrate have the first side wall, first surface and the second surface opposite with the first surface；
First support membrane, first support membrane are on the second surface of the substrate and have bottom surface and the Two side walls；
Second support membrane, second support membrane are on the first surface of the substrate and have top surface and the Three side walls；And
Interconnection structure, the interconnection structure pass through first support membrane and second support membrane from second support membrane The top surface extends to the bottom surface of first support membrane, the interconnection structure covering described first, second And third side wall.
9. semiconductor device packages according to claim 8, wherein the interconnection structure covers second support membrane The bottom surface of the top surface and first support membrane.
10. semiconductor device packages according to claim 9 further comprise the institute for being placed in second support membrane State on top surface and be connected to the passive block layer of the interconnection structure.
11. semiconductor device packages according to claim 9 further comprise insulating layer, wherein the insulating layer A part penetrates the substrate, first support membrane and second support membrane, wherein the insulating layer covers the interconnection One of the top surface of structure, a part of the bottom surface of first support membrane and second support membrane Point.
12. semiconductor device packages according to claim 11, wherein the part of the insulating layer is by the interconnection Structure is surrounded.
13. semiconductor device packages according to claim 8, wherein the substrate includes glass material.
14. semiconductor device packages according to claim 8, wherein the thickness of the substrate is less than about 300 μm.
15. semiconductor device packages according to claim 8, wherein first support membrane and the second support membrane packet Include same dielectric material.
16. a kind of method for manufacturing semiconductor device packages comprising:
Substrate is provided, the substrate has side wall, first surface and the second surface opposite with the first surface；
Support membrane is placed on the second surface of the substrate；
First insulating layer is placed on the first surface of the substrate；
The through-hole for penetrating the substrate, first insulating layer and the support membrane is formed, wherein the through-hole is by the substrate The side wall, the side wall of first insulating layer and the side wall of the support membrane define；And
Placement covers the interconnection structure of the side wall of the substrate, first insulating layer and the support membrane.
17. according to the method for claim 16, wherein first insulating layer has top surface and the interconnection structure The top surface of first insulating layer is covered, and the support membrane has bottom surface and the interconnection structure covers The bottom surface of the support membrane.
18. further comprising according to the method for claim 16, that passive block layer is placed in described in the substrate On first surface, wherein the passive block layer is connected to the interconnection structure.
19. according to the method for claim 16, wherein the substrate includes glass material.
20. according to the method for claim 16, wherein the thickness of the substrate is less than about 300 μm.
CN201810154963.5A 2017-06-08 2018-02-23 Semiconductor device packages Pending CN109037160A (en)

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