CN115207203B - Method for realizing steep side wall of laminated etching in aluminum-based superconducting circuit - Google Patents
Method for realizing steep side wall of laminated etching in aluminum-based superconducting circuit Download PDFInfo
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 85
- 238000005530 etching Methods 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 56
- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000000059 patterning Methods 0.000 claims abstract description 13
- 238000003475 lamination Methods 0.000 claims abstract description 11
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims description 12
- 239000000126 substance Substances 0.000 claims description 11
- 238000010884 ion-beam technique Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- 230000000704 physical effect Effects 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- 239000002184 metal Substances 0.000 abstract description 14
- 229910052755 nonmetal Inorganic materials 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 184
- 238000010586 diagram Methods 0.000 description 9
- 239000010408 film Substances 0.000 description 9
- 239000007789 gas Substances 0.000 description 7
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 125000000896 monocarboxylic acid group Chemical group 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
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- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
The invention provides a method for realizing the steep side wall of laminated etching in an aluminum-based superconducting circuit, which comprises the following steps: patterning a photoresist; (2) Etching the aluminum metal layer exposed by the opening, wherein the opening exposes the dielectric layer; (3) Depositing a silicon oxide layer on the upper surface of the photoresist layer, the side wall of the opening and the bottom surface of the opening by adopting an atomic layer deposition method; (4) Etching the silicon oxide layers on the upper surface of the photoresist layer and the bottom surface of the opening in the step (3); (5) Etching the silicon oxide layer on the side wall of the opening and the dielectric layer exposed by the opening; (6) And (5) repeating the step (3), the step (4), the step (2) and the step (5) in sequence until the aluminum metal layer and the dielectric layer exposed by the opening are etched to expose the substrate, and finally removing the photoresist layer. The method of the invention can solve the problem of steps in the etching of metal and nonmetal lamination in the aluminum-based superconducting circuit and realize the steep sidewall.
Description
Technical Field
The invention belongs to the technical field of laminated etching of a superconducting circuit, and relates to a method for realizing steep side wall etching of laminated etching in an aluminum-based superconducting circuit.
Background
In the process of preparing the multilayer metal wiring of the aluminum-based superconducting circuit, a complicated film structure in which 3 or more pairs of metal layers and dielectric layers are overlapped in the vertical direction may be faced, in which metal Al and dielectric silicon oxide (e.g., siO) are involved 2 Etc.) and the like. In the process of etching the metal layer or the dielectric layer by adopting a dry etching mode in the previous step, the photoresist transversely retreats to two sides faster, so that the photoresist cannot play a role of protection when a next film layer is etched, a plurality of steps are finally formed after the etching, and the performance of a device can be influenced if the steps formed after the etching are too large, therefore, the ideal state after the etching is that all the metal layers and the dielectric layers are steep and downward, namely the side wall steepness of the laminated etching is realized, taking a laminated structure taking the vertical direction as the overlapped 3 pairs of the metal layers and the dielectric layers as an example, the structural schematic diagram before the etching and the ideal structural diagram after the etching are respectively shown in figures 1 and 2, and in the field, the structure schematic diagram before the etching and the ideal structural diagram after the etching are also shown in figures 1 and 2There is no relevant technical means to achieve this effect.
Accordingly, it is desirable in the art to provide a method for achieving sidewall steepness of stack etching in an aluminum-based superconducting circuit.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a method for realizing the steepness of the side wall of the laminated etching in the aluminum-based superconducting circuit. The method of the invention can solve the problem of steps in the etching of metal and nonmetal lamination in the aluminum-based superconducting circuit and realize the steep sidewall.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a method for implementing steepness of a side wall etched by a lamination in an aluminum-based superconducting circuit, where the method for implementing steepness of a side wall etched by a lamination in an aluminum-based superconducting circuit includes the following steps:
(1) Patterning photoresist:
providing a substrate, and forming a laminated structure comprising a plurality of layers of aluminum metal layers and a plurality of layers of dielectric layers on one side of the substrate, wherein the aluminum metal layers and the dielectric layers are alternately arranged, and in the laminated structure, the dielectric layer is closest to the substrate, and the aluminum metal layer is farthest from the substrate;
forming a photoresist layer on one side of the laminated structure far away from the substrate, and patterning the photoresist layer; the patterned photoresist layer comprises at least one opening;
(2) Etching the aluminum metal layer exposed from the opening in the step (1), wherein the dielectric layer is exposed from the opening;
(3) Depositing a silicon oxide layer on the upper surface of the photoresist layer, the side wall of the opening and the bottom surface of the opening by adopting an Atomic Layer Deposition (ALD);
(4) Etching the silicon oxide layers on the upper surface of the photoresist layer and the bottom surface of the opening in the step (3);
(5) Etching the silicon oxide layer on the side wall of the opening and the dielectric layer exposed by the opening;
(6) And (5) repeating the step (3), the step (4), the step (2) and the step (5) in sequence until the aluminum metal layer and the dielectric layer exposed by the opening are etched to expose the substrate, and finally removing the photoresist layer.
According to the invention, the silicon oxide layers are deposited on the upper surface of the photoresist layer, the side wall of the opening and the bottom surface of the opening through the ALD technology, and the silicon oxide layers on the upper surface of the photoresist layer and the bottom surface of the opening are etched, and the thin silicon oxide protective layer is formed on the side wall of the opening.
It should be noted that the shape of the opening in step (1) is not limited in the present invention, and may be, for example, a rectangle, a circle, or other irregular shapes.
Preferably, the aluminum metal layers of step (1) are at least 3 (e.g., 3, 4, 5, or 6, etc.) aluminum metal layers, and the dielectric layers of step (1) are at least 3 (e.g., 3, 4, 5, or 6, etc.) dielectric layers.
Preferably, the thickness of each of the aluminum metal layers in the multi-layer aluminum metal layer of step (1) is independently 0.5-2.0 μm, such as 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, 2.0 μm, or the like.
Preferably, the thickness of each of the plurality of dielectric layers in step (1) is independently 3.0-5.0 μm, such as 3.0 μm, 3.1 μm, 3.2 μm, 3.3 μm, 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm, 4.0 μm, 4.1 μm, 4.2 μm, 4.3 μm, 4.4 μm, 4.5 μm, 4.6 μm, 4.7 μm, 4.8 μm, 4.9 μm, or 5.0 μm.
Preferably, the dielectric layer in step (1) includes a silicon oxide layer, such as a silicon oxide layer or a silicon dioxide layer.
Preferably, the etching manner in step (2) includes wet etching. Wet processEtching is a chemical reaction process, which utilizes chemical reagents to react with the material to be etched to generate soluble substances or volatile substances. In the wet etching process, the etchant and the laminated structure exposed by the mask are subjected to chemical reaction, and then reaction products are removed. The etchant used in the wet etching in step (2) is not particularly limited, and for example, the etching solution can be obtained by mixing the following components in the ratio of 16 3 PO 4 、H 2 O、HNO 3 And CH 3 And etching the mixed solution consisting of COOH.
Preferably, the thickness of the silicon oxide layer in step (3) is 5.0-15.0 nm, such as 5.0 nm, 6.0 nm, 7.0 nm, 8.0 nm, 9.0 nm, 10.0 nm, 11.0 nm, 12.0 nm, 13.0 nm, 14.0 nm or 15.0 nm.
Preferably, the etching manner in step (4) includes Ion Beam Etching (IBE), for example, argon ion beam may be used for etching.
Preferably, the etching manner in step (5) includes dry etching, for example, CF may be used 4 、CHF 3 Or CH 2 F 2 And (5) carrying out dry etching by using fluorine-containing gas.
Preferably, the photoresist layer removed in step (6) can be removed by wet method using organic solvent such as N-methyl pyrrolidone (NMP), acetone, isopropanol, etc.
As a preferred technical scheme of the invention, the method for realizing the steepness of the side wall etched by the lamination in the aluminum-based superconducting circuit comprises the following steps of:
(1) Patterning photoresist:
providing a substrate, and forming a laminated structure comprising a plurality of layers of aluminum metal layers and a plurality of layers of dielectric layers on one side of the substrate, wherein the aluminum metal layers and the dielectric layers are alternately arranged, and in the laminated structure, the dielectric layer is closest to the substrate, and the aluminum metal layer is farthest from the substrate;
forming a photoresist layer on one side of the laminated structure far away from the substrate, and patterning the photoresist layer; the patterned photoresist layer comprises at least one opening;
(2) Adopting a wet etching mode to etch the aluminum metal layer exposed by the opening in the step (1), wherein the dielectric layer is exposed by the opening;
(3) Depositing a silicon oxide layer with the thickness of 5.0-15.0 nm on the upper surface of the photoresist layer, the side wall of the opening and the bottom surface of the opening by adopting an atomic layer deposition method;
(4) Etching the silicon oxide layers on the upper surface of the photoresist layer and the bottom surface of the opening in the step (3) by adopting an ion beam etching mode;
(5) Etching the silicon oxide layer on the side wall of the opening and the dielectric layer exposed by the opening by adopting a dry etching mode;
(6) And (6) repeating the step (3), the step (4), the step (2) and the step (5) in sequence in a circulating manner until the aluminum metal layer and the dielectric layer exposed by the opening are etched to expose the substrate, and finally removing the photoresist layer.
Compared with the prior art, the invention has the following beneficial effects:
according to the invention, the silicon oxide layers are deposited on the upper surface of the photoresist layer, the side wall of the opening and the bottom surface of the opening through the ALD technology, and the silicon oxide layers on the upper surface of the photoresist layer and the bottom surface of the opening are etched, and the thin silicon oxide protective layer is formed on the side wall of the opening.
Drawings
Fig. 1 is a schematic structural diagram of a laminated structure with 3 pairs of overlapped metal layers and dielectric layers in the vertical direction before etching.
Fig. 2 is a schematic diagram of an ideal structure after etching of a stacked structure with 3 pairs of overlapped metal layers and dielectric layers in the vertical direction.
Fig. 3 is a flow chart of etching a stack in an aluminum-based superconducting circuit provided in the prior art.
Fig. 4 is a FIB diagram of a laminated structure finally obtained by using a laminated etching method in an aluminum-based superconducting circuit provided in the prior art.
Fig. 5 is a flowchart of a method for implementing sidewall steepness of stack etching in an aluminum-based superconducting circuit according to an embodiment of the present invention.
Fig. 6 is a structural cross-sectional view corresponding to step S11 in the method for implementing the steepness of the etched sidewall of the stack in the aluminum-based superconducting circuit provided in fig. 5.
Fig. 7 is a structural cross-sectional view corresponding to step S12 in the method for implementing sidewall steepness of stack etching in the aluminum-based superconducting circuit provided in fig. 5.
Fig. 8 is a structural cross-sectional view corresponding to step S13 in the method for implementing sidewall steepness of stack etching in the aluminum-based superconducting circuit provided in fig. 5.
Fig. 9 is a cross-sectional view of the structure corresponding to step S14 in the method for implementing sidewall steepness of stack etching in the aluminum-based superconducting circuit provided in fig. 5.
Fig. 10 is a cross-sectional view of the structure corresponding to step S15 in the method for implementing sidewall steepness of stack etching in the aluminum-based superconducting circuit provided in fig. 5.
Fig. 11 is a cross-sectional view of the structure corresponding to step S16 in the method for implementing the steepness of the etched sidewall of the stack in the aluminum-based superconducting circuit provided in fig. 5.
Fig. 12 is a FIB diagram of a final laminated structure obtained by using a method for realizing the steepness of a side wall of laminated etching in an aluminum-based superconducting circuit according to an embodiment of the present invention.
Wherein, 1-substrate, 2-dielectric layer, 3-metal layer, 4-photoresist layer, T1-first pair of aluminum metal layer and dielectric layer, T2-second pair of aluminum metal layer and dielectric layer, 110-substrate, 210-SiO 2 The structure of the mask comprises a dielectric layer, 220-aluminum metal layer, 300-photoresist layer, 400-opening and 500-silicon oxide layer.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As background art, in the fabrication of multilayer metal wiring of an aluminum-based superconducting circuit, a complicated film structure in which 3 or more pairs of metal layers and dielectric layers are overlapped with respect to a vertical direction may be faced, in which metallic Al and dielectric silicon oxide (e.g., siO) are involved 2 Etc.) and the like. In the process of etching the metal layer or the dielectric layer by adopting a dry etching mode in the last step, the photoresist transversely and rapidly retreats towards two sides, so that the photoresist can not play a role of protection when a next film layer is etched, a plurality of steps can be finally formed after the etching is continued, and the performance of a device can be influenced if the steps formed after the etching are too large.
Fig. 3 is a flow chart of etching a stack in an aluminum-based superconducting circuit provided in the prior art, and referring to fig. 3, the method includes: s1, photoresist patterning: providing a substrate, and forming a layer including 2 aluminum metal layers and 2 dielectric layers (only 2 aluminum metal layers and 2 dielectric layers are given by way of example, wherein the dielectric layers are SiO) on one side of the substrate 2 Layer), the aluminum metal layers and the dielectric layers being alternately arranged, and in the laminated structure, the dielectric layer closest to the substrate and the aluminum metal layer farthest from the substrate; forming a photoresist layer on one side of the laminated structure far away from the substrate, and patterning the photoresist layer; the patterned photoresist layer includes at least one opening. S2, etching the aluminum metal layer exposed by the opening. And S3, etching the exposed dielectric layer of the opening. And S4, etching the aluminum metal layer exposed by the opening. And S5, etching the exposed dielectric layer of the opening. And S6, removing the photoresist layer. The FIB (focused ion beam) pattern of the finally obtained laminated structure by performing the laminated etching by using the method is shown in fig. 4, and it can be seen that the step formed after the etching is too large.
In view of this, an embodiment of the present invention provides a method for implementing steepness of a side wall etched in a lamination in an aluminum-based superconducting circuit, and fig. 5 is a flowchart of a method for implementing steepness of a side wall etched in a lamination in an aluminum-based superconducting circuit, where referring to fig. 5, the method includes:
s11, photoetchingGlue patterning: providing a substrate, and forming 3 aluminum metal layers (each layer is 1 mu m thick) and 3 dielectric layers (SiO) on one side of the substrate 2 Dielectric layers, each layer being 4 μm thick), the aluminum metal layers and the dielectric layers being alternately arranged, and in the laminated structure, the dielectric layer closest to the substrate and the aluminum metal layer farthest from the substrate are provided; forming a photoresist layer on one side of the laminated structure far away from the substrate, and patterning the photoresist layer; the patterned photoresist layer includes an opening.
In particular, the material of the substrate may comprise silicon. FIG. 6 is a cross-sectional view of the structure corresponding to step S11 in the method for realizing the steepness of the etched sidewall of the laminated layer in the aluminum-based superconducting circuit provided in FIG. 5, and referring to FIG. 6, a sidewall including 3 aluminum layers 220 and 3 SiO layers is formed on one side of the substrate 110 2 Laminated structure of dielectric layer 210, aluminum metal layer 220 and SiO 2 The dielectric layers 210 are alternately disposed. In the laminated structure, the aluminum metal layer 220 and SiO 2 The layers of the dielectric layer 210 are the same, and the layer closest to the substrate 110 is SiO 2 Dielectric layer 210, furthest from substrate 110 is aluminum metal layer 220, i.e., siO 2 Dielectric layer 210 is paired with aluminum metal layer 220. Forming a photoresist layer 300 on a side of the stacked structure away from the substrate 110, and patterning the photoresist layer 300, specifically, patterning the photoresist layer by exposing and developing the photoresist layer; the patterned photoresist layer includes an opening 400 having a rectangular shape.
And S12, etching the aluminum metal layer exposed from the opening in the S11 by adopting a wet etching mode, wherein the opening exposes the dielectric layer.
Specifically, fig. 7 is a cross-sectional view of the structure corresponding to step S12 in the method for implementing steepness of the side wall etched by the stack in the aluminum-based superconducting circuit provided in fig. 5, and referring to fig. 7, a wet etching method (an etchant is H1 3 PO 4 、H 2 O、HNO 3 And CH 3 COOH composition) of the aluminum layer 220 exposed through the opening in S11, the opening exposing SiO, is etched 2 A dielectric layer 210.
And S13, depositing a silicon oxide layer with the thickness of 10nm on the upper surface of the photoresist layer, the side wall of the opening and the bottom surface of the opening by adopting an atomic layer deposition method.
Specifically, fig. 8 is a cross-sectional view of the structure corresponding to step S13 in the method for implementing the steepness of the etched sidewall of the laminated layer in the aluminum-based superconducting circuit provided in fig. 5, and referring to fig. 8, a silicon oxide layer 500 with a thickness of 10nm is deposited on the upper surface of the photoresist layer 300, the sidewall of the opening 400, and the bottom surface of the opening 400 by using an atomic layer deposition method.
And S14, etching the silicon oxide layers on the upper surface of the photoresist layer and the bottom surface of the opening in the S13 in an ion beam etching mode.
Specifically, fig. 9 is a cross-sectional view of the structure corresponding to step S14 in the method for implementing the steepness of the etched sidewall of the laminated layer in the aluminum-based superconducting circuit provided in fig. 5, and referring to fig. 9, the silicon oxide layer 500 on the upper surface of the photoresist layer 300 and the bottom surface of the opening 400 in S13 is etched by ion beam etching (specifically, argon ion beam etching), so that the silicon oxide layer 500 is only remained on the sidewall of the opening 400.
And S15, etching the silicon oxide layer on the side wall of the opening and the dielectric layer exposed by the opening by adopting a dry etching mode.
Specifically, fig. 10 is a cross-sectional view of the structure corresponding to step S15 in the method for implementing steepness of the etched sidewall of the laminated layer in the aluminum-based superconducting circuit provided in fig. 5, and referring to fig. 10, a dry etching manner is adopted (specifically, CF may be adopted) 4 Gas) etches the silicon oxide layer on the side wall of the opening and the exposed dielectric layer of the opening, so that the aluminum metal layer is exposed out of the opening 400.
Dry etching is a technique of performing thin film etching using plasma. Taking plasma dry etching as an example, the process of plasma generation is simply understood as that a sample to be etched is put into etching equipment, and special gas such as CF is introduced into the etching equipment 4 The electrons continuously move under the action of the energy of the radio frequency power supply in the etching equipment to obtain energy to collide with the gas molecules, so that the gas molecules CF 4 Will be partially ionized and decomposed to microscopicThe process. In these processes CF 4 Will be converted from gas to plasma containing ions such as CF 3 + Free radicals such as F, etc. The ions in the film will be accelerated vertically downwards under the action of the radio frequency power supply to obtain kinetic energy to bombard the surface of the film to remove the film, which is a physical action, and the physical action mainly occurs in the vertical direction, so the film is called as anisotropy. The free radicals in the plasma have strong chemical activity, can fully perform chemical reaction with the film layer to generate gas to be discharged, and achieve the purpose of etching, namely the chemical action, because the chemical action is equivalent in all directions, the plasma is usually called as isotropy.
The dry etching method used by the invention is the combination of physical action and chemical action, and when the dielectric layer exposed by the opening is etched, the physical action and the chemical action act simultaneously in the vertical direction, so that the dielectric layer is removed; when the silicon oxide layer on the side wall of the opening is etched, the purpose of transverse etching is mainly achieved by utilizing chemical action, the silicon oxide layer on the side wall of the opening only grows to be about 10nm thick, and the silicon oxide layer can be removed through the chemical action. In addition, in order to remove the silicon oxide transversely in the process of etching the medium, the silicon oxide which is the same as the medium layer is specially selected as the protective layer, and is not selected randomly.
And S16, repeating S13, S14, S12 and S15 in sequence and circularly until the aluminum metal layer and the dielectric layer exposed by the opening are etched, exposing the substrate, and finally removing the photoresist layer.
Specifically, fig. 11 is a cross-sectional view of a structure corresponding to step S16 in the method for implementing steepness of a side wall etched in a lamination in an aluminum-based superconducting circuit provided in fig. 5, that is, a schematic view of a lamination structure after the lamination etching is finished, referring to fig. 11, after steps S13, S14, S12, and S15 are sequentially and cyclically repeated until an aluminum metal layer 220 and an SiO layer exposed to an opening are formed 2 The dielectric layer 210 is etched away, the opening exposes the substrate 110, and finally the photoresist layer is removed by NMP.
Fig. 12 is an FIB diagram of a finally obtained laminated structure by using the method for implementing sidewall steepness of laminated etching in an aluminum-based superconducting circuit according to the foregoing embodiment of the present invention, and it can be seen that, when the method provided by the present invention is used for laminated etching, the finally obtained laminated structure has no obvious step.
Namely, in the invention, the silicon oxide layer is deposited on the upper surface of the photoresist layer, the side wall of the opening and the bottom surface of the opening by the ALD technology, and the silicon oxide layer on the upper surface of the photoresist layer and the bottom surface of the opening is etched, and the thin silicon oxide protective layer is formed on the side wall of the opening.
The applicant states that the present invention is illustrated by the above embodiments and the accompanying drawings to describe the method for realizing the steepness of the etched side wall in the aluminum-based superconducting circuit according to the present invention, but the present invention is not limited to the above embodiments, that is, the present invention does not mean that the present invention must be implemented by the above embodiments. It will be apparent to those skilled in the art that any modifications to the present invention, equivalent substitutions of selected materials and additions of auxiliary components, selection of specific forms, etc., are within the scope and disclosure of the present invention.
Claims (5)
1. A method for realizing the steepness of a side wall etched by a lamination in an aluminum-based superconducting circuit is characterized by comprising the following steps of:
(1) Patterning the photoresist:
providing a substrate, and forming a laminated structure comprising a plurality of layers of aluminum metal layers and a plurality of layers of dielectric layers on one side of the substrate, wherein the aluminum metal layers and the dielectric layers are alternately arranged, and in the laminated structure, the dielectric layer is closest to the substrate, and the aluminum metal layer is farthest from the substrate;
forming a photoresist layer on one side of the laminated structure far away from the substrate, and patterning the photoresist layer; the patterned photoresist layer comprises at least one opening;
(2) Etching the aluminum metal layer exposed from the opening in the step (1) by adopting a wet etching mode, wherein the opening is exposed out of the dielectric layer;
(3) Depositing a silicon oxide layer on the upper surface of the photoresist layer, the side wall of the opening and the bottom surface of the opening by adopting an atomic layer deposition method;
(4) Etching the silicon oxide layers on the upper surface of the photoresist layer and the bottom surface of the opening in the step (3);
(5) Etching the silicon oxide layer on the side wall of the opening and the dielectric layer exposed by the opening by adopting a dry etching mode;
(6) Sequentially and circularly repeating the step (3), the step (4), the step (2) and the step (5) until the aluminum metal layer and the dielectric layer exposed by the opening are etched away to expose the substrate, and finally removing the photoresist layer;
the dielectric layer in the step (1) comprises a silicon oxide layer;
the thickness of the silicon oxide layer in the step (3) is 5.0-15.0 nm;
and (5) in the dry etching mode, when the dielectric layer exposed by the opening is etched, the physical action and the chemical action act simultaneously in the vertical direction, so that the dielectric layer is removed, and when the silicon oxide layer on the side wall of the opening is etched, the purpose of transverse etching is achieved by utilizing the chemical action.
2. The method for realizing the steepness of the etched side wall of the laminated layer in the aluminum-based superconducting circuit as claimed in claim 1, wherein the aluminum metal layers in step (1) are at least 3 aluminum metal layers, and the dielectric layers in step (1) are at least 3 dielectric layers.
3. The method for realizing the steepness of the etched side wall of the laminated layer in the aluminum-based superconducting circuit according to claim 1, wherein the thickness of each aluminum metal layer in the plurality of aluminum metal layers in the step (1) is 0.5-2.0 μm independently.
4. The method for realizing the steepness of the etched sidewall of the laminated layer in the aluminum-based superconducting circuit as claimed in claim 1, wherein the thickness of each of the dielectric layers in the step (1) is 3.0-5.0 μm.
5. The method for achieving the steepness of the etched sidewall of the laminated layer in the aluminum-based superconducting circuit as claimed in claim 1, wherein the etching manner of step (4) comprises ion beam etching.
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| CN202211121005.0A CN115207203B (en) | 2022-09-15 | 2022-09-15 | Method for realizing steep side wall of laminated etching in aluminum-based superconducting circuit |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101030554A (en) * | 2006-02-28 | 2007-09-05 | 三洋电机株式会社 | Method for manufacturing integrated circuit |
| TW200924058A (en) * | 2007-09-11 | 2009-06-01 | Ibm | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
| CN102398887A (en) * | 2010-09-14 | 2012-04-04 | 中微半导体设备(上海)有限公司 | Deep hole silicon etching method |
| CN102738074A (en) * | 2012-07-05 | 2012-10-17 | 中微半导体设备(上海)有限公司 | Method for forming semiconductor structure |
| CN107658305A (en) * | 2017-08-31 | 2018-02-02 | 长江存储科技有限责任公司 | A kind of semiconductor etching method and its formation structure |
| CN111510096A (en) * | 2020-04-20 | 2020-08-07 | 苏州汉天下电子有限公司 | Bulk acoustic wave resonator and method for manufacturing the same |
| CN113755840A (en) * | 2021-08-16 | 2021-12-07 | 合肥本源量子计算科技有限责任公司 | Etching liquid and etching method |
| CN114388472A (en) * | 2020-10-22 | 2022-04-22 | 南亚科技股份有限公司 | Semiconductor element, semiconductor assembly and preparation method thereof |
-
2022
- 2022-09-15 CN CN202211121005.0A patent/CN115207203B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101030554A (en) * | 2006-02-28 | 2007-09-05 | 三洋电机株式会社 | Method for manufacturing integrated circuit |
| TW200924058A (en) * | 2007-09-11 | 2009-06-01 | Ibm | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias |
| CN102398887A (en) * | 2010-09-14 | 2012-04-04 | 中微半导体设备(上海)有限公司 | Deep hole silicon etching method |
| CN102738074A (en) * | 2012-07-05 | 2012-10-17 | 中微半导体设备(上海)有限公司 | Method for forming semiconductor structure |
| CN107658305A (en) * | 2017-08-31 | 2018-02-02 | 长江存储科技有限责任公司 | A kind of semiconductor etching method and its formation structure |
| CN111510096A (en) * | 2020-04-20 | 2020-08-07 | 苏州汉天下电子有限公司 | Bulk acoustic wave resonator and method for manufacturing the same |
| CN114388472A (en) * | 2020-10-22 | 2022-04-22 | 南亚科技股份有限公司 | Semiconductor element, semiconductor assembly and preparation method thereof |
| CN113755840A (en) * | 2021-08-16 | 2021-12-07 | 合肥本源量子计算科技有限责任公司 | Etching liquid and etching method |
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