JPS5932151A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the withstand voltage and the reliability of a semiconductor device by superposing the second wiring layer on the first wiring layer while placing a resist mask thereon, exfoliating a mask, superposing the third wiring layer, dry etching it, thereby flattening the surface of the device. CONSTITUTION:An aluminum layer 22 on an Si substrate 21 is patterned by a resist mask 23, and an SiO2 film 24 is covered. When the mask 23 is removed after etching lightly with HF solution, a V-shaped groove 25 is obtained in the vicinity of the stepwise difference. Then, an SiO2 film 26 is covered, is etched by reactive ion etching to expose the surface of the aluminum layer 22. Then, the groove 25 is filled with the film 26 to flatten the surface. Further, an SiO2 film 27 is superposed, and an aluminum layer 29 is deposited. Since the insulating layer 27 and the aluminum layer 29 are formed on the flattened surface, the layer 27 is formed densely in a uniform thickness, a semiconductor device which has high withstand voltage and high reliability can be obtained, the thickness of the conductive layer can become constant, thereby preventing the wirings from being disconnected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device.
The present invention relates to a method for flattening the surface of a conductor device suitable for applying multilayer wiring.

A method for manufacturing electrodes and interconnections for semiconductor devices, which has been widely used in the past, will be explained using a two-culm diagram shown in FIG. First, as shown in Figure (a), after various steps are performed to form a base material on a semiconductor substrate 11 (not shown), a first conductive layer 12 to be used as an electrode or wiring is formed. After applying a resist to the surface of the first conductive layer 12 and patterning it, the - portion of the first conductive layer 12 is removed by plasma etching or the like using the resist as a mask, and then the resist is removed. Next, as shown in (1)),
An insulating layer 13 is formed on the substrate 1 including the remaining first conductive layer 12.
is formed, and through poles 14 are provided on this insulating layer 1:3. Thereafter, as shown in FIG.
form.

In the conventional method constructed in this way, the first conductive layer 12 is etched by plasma etching or the like.
1. Since the cross-sectional shape is perpendicular to the substrate 11 and has a step, the insulating layer 13 formed in this section may have an overbank shape at the end of the first conductive layer 12 or may overlap the sidewalls of the first conductive layer 12. It hardly adheres to the surface. Q) "'+": As a result, even if the second conductive layer 15 is formed on the insulating layer +3j-, the insulating layer 1:
(The second conductive layer 15 becomes extremely thin in the overbank-like part of the screen, resulting in high wiring resistance, which has the drawback of slowing down the operation speed of the 9-body device or causing malfunction. In such a case, the second conductive layer 15 is cut at the overbank-shaped portion of the insulating layer 1; - The thickness of the insulating layers 1 and 3 in the bank-shaped portion is not uniform (and the electrical withstand voltage is low, so the insulation between the first conductive layer 12 and the second conductive layer 15!11' This has the drawback of poor performance and reduced reliability of the semiconductor device.

The present invention has been made to eliminate these drawbacks, and provides a method for manufacturing a semiconductor device with high electrical breakdown voltage and high reliability with high yield by flattening the surface of the semiconductor device. It is something.

Hereinafter, the present invention will be explained in detail with reference to examples as shown in FIG.
A) to (Fl) are process diagrams 1' showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. It shows the cross-sectional shape of the main part of the semiconductor device (the part related to the present invention) at the key point of the culm. The above steps will be explained in accordance with the order (A) to (T-1) of the drawings.

(c): First, aluminum 1. is used as an electrode or wiring on 1- of the 1' conductor substrate 21 which has been subjected to predetermined processing (formation of elements and insulating films, etc.). A first layer (conductive layer) 22 such as (At) or polycrystalline Noricon is formed, and then a polymer renost (for example, Nnoplay product AZ-1350.J) is formed.
etc.) and patterning the resist using lithography technology to obtain a structure having a Renost pattern 23.

(B) Using the resist pattern 23 as a mask, the first layer (conductive layer) 22 is minutely etched by a plasma etching method or a wet method.

(C) A second layer (insulating film) 24 exhibiting insulating properties such as a silicon oxide film (5iO2) is formed on the substrate containing the first layer 22 of the resist pattern 23 by sputtering or vapor deposition. The film is formed at a substrate temperature of 200° C. or lower. The principle of keeping the substrate temperature below 200'C [1st layer, 2nd layer 24
This is to prevent the resist pattern 2:3 from melting when forming the resist pattern. 1- The second layer (insulating film) 24 is the first layer (
It is also deposited on the sidewalls of the conductive layer 22 and the Renost pattern 2.

At this time, the first layer (conductive layer) 22 palm/stock tongue 2
; Near the step 3, it is in the shadow of this step, and 81
The second layer (insulating film) 24 such as 02 becomes porous.

(1-)) A lift-off process for removing the unnecessary second layer (insulating film) 24 of the Niresist dopakun 23-1- together with the renost was not performed. To facilitate lift-off of C, a solution that corrodes the second layer 24, such as 5i02 as the second layer, is used.
When using a solution containing hydrofluoric acid, it is most effective if it is not immersed in a solution containing hydrofluoric acid for a very short time. In this upper culm, the porous insulating film in the vicinity of step (1) is also etched/removed.
A deep groove 25 is formed between the layer (]9 electrical layer) 22 and the second layer (insulating film) 2/I. This groove 25 is
The source of '1 is width 0.5/"" + Q'i,
5 pm V-shaped 1. [Conditions] First layer 22; material: At or polycrystalline silicon, film thickness: Q, vertically etched at 57 zm.

Resist pattern 23; film thickness 05 μm.

Second layer 24; thickness is 5102, film thickness is 0.511 m,
Snow (formed using the ivy method at a pressure of 5X 1031'orr.

(E): A third layer 26 made of a conductive layer or an insulating film is formed over the entire surface of the substrate. As this third layer 26, for example, the thickness of 5i02 is 0511m.
When formed under a pressure of 5×10 3 Torr, the surface irregularities become grooves with a width of 0.3 pm and a depth of 0.3 μm.

(F'): The third layer 26 is etched by dry etching until the surface of the first layer 22 is exposed.

As this dry etching method, the etching rate of the depressions formed on the surface of layer 2 (5) is different from that of other flat etching methods. As a result, as shown in the figure, the groove 25 formed between the first layer 22 and the second layer 24 is filled with the third layer 26 and becomes flat. become.

A specific example of this etching step 1 is shown below: The third layer 2G is the sample exemplified in step (E) above, that is, the surface unevenness is a groove with a width of 0.3 pm and a depth of 03 μm. A 5102 film was prepared, and this film was etched by the ion-on-ya [queso-tink method] under the following conditions.

1 article f'1] (1) Ar ions are used, the neutral angle is 60° with respect to the normal to the sample surface, and the collision energy is about 500 eV. (21 The sample was rotated during ion enching. The rotation speed was 5 rpm.

The etching speed at this time is 350 A/min for the 5i02 film of the second layer 24 and the third layer 2G, and 320 A/min for the At film when At is used as the first layer 22.
min, 3 when using 1 copy of polycrystalline solicon
80 A/min.

(G) The insulating layer 27 is formed and the through poles 28 are opened 11. As the insulating layer 27, for example, a 5i02 film formed by a sputtering method or a CVI method is used.

(IN): A tIrIr conductive layer 20 is formed. As the conductive layer 29, for example, an At film formed into a shape I by sputtering or vacuum evaporation is used.

After the above steps, as shown in the figure, the insulating layer 27
and a conductive layer 29 are formed on the surface 1-.

For this reason, the insulating layer 27 has a dense density and is formed with almost the same thickness, so the electrical withstand voltage is increased and the gap between the first layer (conductive layer) 22 and the conductive layer 29 is increased. Insulation! lJ
+'1'l (), a highly reliable semiconductor device can be manufactured.Furthermore, there is no step in the insulating layer 27,
Since the conductive layer 29 can be formed to have almost the same thickness, it is possible to prevent part of the conductive layer from becoming extremely thin or disconnecting.
Therefore, the manufacturing yield of semiconductor devices can be improved by 1.

In the embodiment of the present invention (FIG. 2), a case has been described in which the first layer (conductive layer) 22 is etched and the second layer (insulating film) 24 is lifted off. However, in the present invention, contrary to the case 1-, the insulating film is used as the first layer, and the insulating film is used as the second layer.
It is also effective when using a conductive layer as the layer. In this case, whether the third layer is a conductive layer or an insulating layer, the surface of the semiconductor device is planarized, and the above-mentioned effect is remarkable.

In addition, in the embodiment shown in FIG. 2, after forming the third layer, trial etching is performed.
E), (F) By performing the formation of the third layer and etching simultaneously or alternately during the job, the groove 25 created between the first layer and the second layer can be filled. 81 Shibakawa conversion is planned. The formation and etching of the third layer can be easily performed using the apparatus shown in FIGS. 3 and 4, or at the same time.

FIG. 3 is an explanatory diagram when a plasma sputtering device is used. The substrate 31 that has undergone the steps shown in FIG.
Take 4 and subtract 1. The inside of the sputtering tank 35 is
After 1 atmosphere, an inert gas such as argon is introduced to a predetermined level (for example, 10''-10''f'orr), and a direct current or high frequency (for example, 13.5 (i) When a voltage of MIIZ ) is applied, 1
- The active particles of the handle become ionized and collide with the target surface with high energy. This collision knocks out constituent atoms of the target 34, and these atoms are transferred to the substrate 311.
is deposited in At this time, when a DC or AC voltage is applied to the plate volta 32, the substrate 31 is also bombarded with high-energy ions and is ejected from the Jl plate again. (For example, if the target has a diameter of 20 mmφ
By adjusting the power of about 3 kW when
)) The speed at which the atoms reach the groove 25 can be set to be less than the speed at which they are ejected from the groove. As a result, the groove 25 in FIG. 2(D) is filled with the third layer 26 and becomes flat as shown in FIG. 2(F).

Note that the voltage is applied to the substrate holter 32 not only at the same time as the application to the sputtering electrode 33, but also at the alternating/7. Excellent flattening characteristics can be obtained even if the

FIG. 4 is an explanatory diagram when an ion beam sputtering device is used. Substrate 4 that has gone through the steps up to Figure 2 (D)
1 is installed in the apparatus, inert gas ions (for example, Ar') 43 are extracted from the ion gun 42 and are made to collide with the target 1-/14 with high energy (for example, 500 eV). Due to this collision, Tharkera 1-Configuration 1j;
j (- (for example, 5i02)) is ejected and reaches the substrate 41 surface.At this time, when the inert gas ions (for example, Ar') 46 drawn out from another ion can 45 collide with the old surface of the substrate, they reach the substrate surface. The - part of the third layer 2G is ejected.As a result, the surface of the semiconductor device can be flattened for the same reason as explained in Fig. The formation and etching may be performed in the same step 11- or in the intersecting step 11.

By performing the formation of the third layer 26 and the etching simultaneously or alternately as described in 1- above, the manufacturing time of the semiconductor device can be reduced by ft7 compared to the method shown in FIG. Therefore, this method has the advantage of making the semiconductor device inexpensive.

As described below, according to the present invention, since the surface can be made into a carrier, there is an advantage that a highly reliable conductor device with high electrical withstand voltage can be manufactured at a high yield.

[Brief explanation of the drawing]

Figures 1 (a) to (C) are explanatory diagrams of the conventional process for manufacturing electrodes and wiring for semiconductor devices, and Figures 2 (A) to (14) are diagrams showing a method for manufacturing semiconductor devices according to the present invention. , step explanatory diagram 3rd
The figure is an explanatory diagram when a plasma sputtering apparatus is used in the manufacturing method of the present invention, and FIG. 4 is an explanatory diagram when an ion beat sputtering apparatus is used. ++, 2+ Pall 11 conductor substrate I2...first conductive layer 13/insulating layer 1/l, 28...through pole 15/
- Second conductive layer 22... First layer 2; 3... Resist pattern 24... Second layer 25... Groove
2G...Third layer 27...Insulating layer
29... Conductive layer 31. 41... Substrate ;(
2...Substrate holder: 33...Sputtering electrode 34.44...Target 35...Sputtering tank 42, 45...Ion gun 43.46...Inert gas ion patent applicant Nippon Telegraph and Telephone Public Corporation agent Patent attorney Junnosuke Nakamura 1 圀su 2 fig. 2 no M' 3 rA ya 4 bar. 2

Claims (2)

[Claims] (1) Forming a first layer on the semiconductor substrate 1, forming a resist film on the first layer 1, and using the resist film as a mask] Processing the first layer 7 Mark the cyst pattern as 4'?
Form a second layer on the mounted ``11 conductor plate''.
- culm and 1- marked cyst baton, 1] - includes lift-off 1- culm to remove the second layer mentioned in 1- marked 1- along with the cyst batten, and step 11 to form a third layer and perform I-ly etching. A method for manufacturing a semiconductor device, characterized in that: (2) In about 11 regarding layer No. 3, said No. 3:
Formation of layer 3 and dry etching may be performed simultaneously or alternately (1):
11. A method for manufacturing a conductor device according to claim 1, wherein