CN107658305A - A kind of semiconductor etching method and its formation structure - Google Patents
A kind of semiconductor etching method and its formation structure Download PDFInfo
- Publication number
- CN107658305A CN107658305A CN201710774751.2A CN201710774751A CN107658305A CN 107658305 A CN107658305 A CN 107658305A CN 201710774751 A CN201710774751 A CN 201710774751A CN 107658305 A CN107658305 A CN 107658305A
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- Prior art keywords
- raceway groove
- hole
- stepped construction
- etching
- layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Drying Of Semiconductors (AREA)
Abstract
The invention provides a kind of stepped construction lithographic method of applied linings; the side wall of through hole in etching process is protected not expand by forming lining; so as to the expansion by preventing via openings genius loci size (CD), to ensure depth of the etching in vertical direction extension.The present invention may be such that the maximum characteristic size of passage reduces by 30% relative to traditional handicraft, realize each layer of whole through stepped construction；The method of the present invention is applicable to the etching procedure of 64 layers and more than 64 layers of stepped construction.
Description
Technical field
The present invention relates to semiconductor applications, systems a kind of etching for three-dimensional storage stepped construction
Method, and structure is formed accordingly.
Background technology
Due to conventional planar structure nand memory already close to expanding storage depth the limit, thus, in order to enter
One step improves memory capacity, proposes the 3D nand memories using three-dimensional data storage component structure in recent years.
On the accumulation layer among 3D nand memories, there is nitride multilayer thing and the overlapping stacking knot formed of oxide
Structure (TIER).Also, for the stepped construction, and then each layer therethrough is etched by etching technics, form raceway groove
Through hole (channel hole, abbreviation CH) and gate line (Gate-line Slite, abbreviation GLS).
However, the raceway groove through hole that existing etching technics is formed, the opening features size (CD) on stepped construction upper strata
Maximum, as raceway groove through hole successively gos deep among stepped construction, its size progressively reduces, and ultimately forms thinner tip.Ditch
The shape of road through hole is as shown in figures 1 a-1d.
Shown in Figure 1A -1D, Figure 1A is that the total stepped construction for 32 layers of conductive layer and insulating layer is performed etching to run through；Figure
1B is that the total stepped construction for 48 layers of conductive layer and insulating layer is performed etching to run through, the characteristic size of its superiors' opening
It is 1.1 times of Figure 1A；Fig. 1 C are that total 64 layers stepped construction is performed etching to run through, the characteristic size of its superiors' opening
It is 1.3 times of Figure 1A；And Fig. 1 D are that total 128 layers stepped construction is performed etching to run through, the feature of its superiors' opening
Size reaches 1.5 times of Figure 1A.
This is due to that the raceway groove through hole is that each layer of stepped construction is from top to bottom successively etched to form.The opening on upper strata
Position is completed by etching first, and following each layer is performed etching until running through, it is also desirable to certain etch period is consumed,
Opening continues to be etched during this, thus characteristic size constantly expands.Obviously, the stacking number of stepped construction is more,
Time required for whole etching technics terminates is longer, then the characteristic size of the opening formed is bigger.
The content of the invention
The opening of raceway groove through hole conference cause ditch trace overlap, so as to electrical property failure, so the characteristic size of raceway groove through hole
Control be very important.Pass through the present invention so that (upper strata characteristic size and orlop are special by the B/T ratio of raceway groove through hole
Levy the ratio of size) it can become big, so have very great help to being made for trench bottom.
The present invention provides a kind of semiconductor etching method, and this method comprises the following steps：
Stepped construction is provided；
First time etching procedure is carried out to stepped construction, a part of layer in stepped construction, local raceway groove is formed and leads to
Pore structure；
Lining is formed in the side wall of local raceway groove through-hole structure and the bottom of the structure；
By etching the part for removing the lining and being located at local raceway groove through-hole structure bottom；Expose not yet by described
The stepped construction that etching procedure runs through；
To each layer of stepped construction not run through by first time etching procedure, continue second of etching procedure, until passing through
Each layer of whole of stepped construction is worn, forms complete raceway groove through hole；
Remove the lining of the raceway groove through-hole side wall residual.
Preferably, total number of plies of the stepped construction is 64 layers or more than 64 layer.
Preferably, the lining material has etching selection relative to the stepped construction material as raceway groove through-hole side wall
Property.
Preferably, the lining is polysilicon.
Preferably, the removal to raceway groove through-hole side wall lining uses THAM or NH4OH, the THAM or NH4OH for
Stepped construction material has high selectivity.
Preferably, the raceway groove through-hole side wall lining is removed to characteristic size (CD) expansion caused by raceway groove through hole to be less than
1nm。
A kind of structure formed using any one above-mentioned lithographic method, including stepped construction and raceway groove through hole, its
Middle raceway groove through hole runs through each layer of the stepped construction, and raceway groove through hole is consistent in the characteristic size (CD) of each layer up and down.
The present invention and then the structure for providing use above-mentioned lithographic method formation, including stepped construction and raceway groove through hole,
Wherein raceway groove through hole runs through each layer of the stepped construction, and raceway groove through hole is consistent in the characteristic size (CD) of each layer up and down.
Thus it is clear that it is of the invention it is critical that protect the side wall of through hole in etching process not expand by forming lining, from
And by preventing the expansion of via openings genius loci size (CD), to ensure depth of the etching in vertical direction extension, relatively
The maximum characteristic size that may be such that passage in traditional handicraft reduces by 30%, realizes each layer of whole through stepped construction；The present invention
Method be applicable to the stepped constructions of 64 layers and more than 64 layers, such as 96 layers, 128 layers or 160 layers of stepped construction
Etching procedure, avoid the increased cost of twice etching and the alignment of two layers raceway groove is made difficulty.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Accompanying drawing 1A-1D shows the raceway groove through hole for etching formation in the stepped construction of three-dimensional storage using existing process
Form；
Accompanying drawing 2A-2F shows the schematic diagram in lithographic method each stage according to embodiment of the present invention；
Accompanying drawing 3 shows the lithographic method flow chart according to embodiment of the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
According to the embodiment of the present invention, a kind of three-dimensional storage stepped construction lithographic method of applied linings is proposed, with
And the raceway groove through-hole structure formed.
Accompanying drawing 2A-2F shows the schematic diagram in lithographic method each stage according to embodiment of the present invention.Fig. 3 is this method
Flow chart, this method comprises the following steps：
S1, there is provided stepped construction (TIER), such as Fig. 2A, the stepped construction is vertically alternately divided by plurality of conductive layers and insulating barrier
Cloth is formed, such as can be vertically alternately distributed by oxide layer and nitration case；The present embodiment is to amount to 73 layers of stepped construction
Exemplified by (TIER1, TIER2, TIER3 ... TIER73), it will be appreciated by a person skilled in the art that the technique of the application is not limited to
The specific number of plies of stepped construction, go for the stepped construction of 64 layers and more than 64 layers, such as 96 layers, 128 layers or 160
Layer.Accumulation layer of the stepped construction as three-dimensional storage, for working processes such as follow-up formation conductive structures, it is necessary in the layer
Raceway groove through hole, each layer in stepped construction are formed on stack structure.
S2, first time etching procedure is carried out to stepped construction, forms local raceway groove through-hole structure.First time etching procedure institute
A part of layer that the local raceway groove through hole formed only runs through in stepped construction, because etching duration is shorter, as shown in Figure 2 B, no
The characteristic size (CD) of upper strata opening can be caused to be significantly greater than following layer.
The step generally use of above-mentioned formation raceway groove through hole is silicon perforation (TSV) technique, and silicon perforation technology is a kind of new
The semiconductor technology of grain husk.Silicon through electrode technology, which essentially consists in, solves the problems, such as chip chamber interconnection, belongs to a kind of new three-dimensional space
Between three-dimensional encapsulation technology.Hot silicon perforation technology createed by the stacking of three dimensions, via silicon perforation more meet it is light,
Thin, short, small market demand product, there is provided needed for the wafer-class encapsulation such as MEMS (MEMS), photoelectricity and electronic component
Packaging technology technology.
Silicon perforation technology is to be drilled on chip in a manner of etching or laser, then by conductive material such as copper, polysilicon, tungsten
Conductive raceway groove (bond wires for connecting inside and outside portion) is formed etc. guide hole (Via) is inserted.It is last then by chip or tube core
(die) thinning is stacked, with reference to (bonding) again, and as the piling IC (3DIC) of three dimensions.Such one
Come, it is possible to remove lead and link (wire bonding) mode.Change drilled in a manner of etching or laser (Via) and electric conduction
Pole, lead space can be not only saved, the usable floor area of circuit board and the volume of packaging part can also be reduced.
Due to filling interior bonds distance, the as thickness of the chip after thinning or tube core, phase using the structure of silicon perforation technology
Compared with the traditional stack encapsulation for taking lead to link, the inside access path of three dimensions piling IC is shorter, relatively can
Make the transmission resistance of chip chamber is smaller, speed faster, noise is smaller, efficiency more preferably.Especially in central processing unit (CPU) and cache
In data transfer in memory, and memory card applications, the short distance interior bonds path institute of silicon perforation technology can be more highlighted
The performance advantages brought.In addition, the size after the encapsulation of three dimensions piling IC is equal to die-size.Emphasizing more work(
Energy, the portable electronic product field of small size, the small size performance of three dimensions piling IC is even more entrance into market
Primary factor.
In order to ensure that the characteristic size of the upper strata opening for the through hole that etching is formed for the first time will not be significantly greater than lower floor's opening
Characteristic size, it is necessary to the number of plies of the strict control etching stepped construction of etching for the first time, for example, the stacking that first time etches away
The number of plies of structure is preferably less than 50 layers, less than 30 layers or less than 10 layers less than 70 layers.In order to reach the mesh of above-mentioned etching
And effect, the selection of the parameter such as etching agent species and concentration and etch period is important parameter, by grasping use in advance
In the species, concentration and temperature of the etch liquids of etching, then according to forming the material of chip and the etching speed of its oxide
Rate calculates suitable etching period to carry out, to cause etch depth in the range of above-mentioned requirements.Wherein, the etching liquid can
To be tetramethylammonium hydroxide (TMAH), HF, KOH or NaOH.For example, when etching temperature is 70 degrees Celsius, various concentrations
TMAH is to the etch rate of silicon：4100 angstrom mins (concentration 2.5%), 5100 angstrom mins (concentration 5%), 4800 angstroms/
Minute (concentration 10%), 4300 angstrom mins (concentration 15%), 4000 angstrom mins (concentration 20%).When TMAH concentration
For 8% when, TMAH is to the etch rate of silicon at a temperature of different etching：2000 angstrom mins (etching temperature is 50 degrees Celsius),
3500 angstrom mins (etching temperature is 60 degrees Celsius), 5000 angstrom mins (etching temperature is 70 degrees Celsius), 6100 angstrom mins
(etching temperature is 80 degrees Celsius), 9000 angstrom mins (etching temperature is 90 degrees Celsius).According to above etch process parameters, and
, can be to select specific technological parameter according to the specific etching number of plies with reference to the thickness of each layer in stepped construction.
S3, lining is formed in the side wall of local raceway groove through-hole structure and the bottom of the structure；The lining is polymeric liner
In, the polymer includes but is not limited to：Polyacrylate, polymethacrylates, substitution and unsubstituted polystyrene, take
Generation and unsubstituted polyvinylnaphthaleneand, substitution and unsubstituted polyvinyl anthracene, cyclic olefin polymer, cyclic olefin and
Maleic anhydride copolymer, the copolymer containing maleic anhydride, substitution and unsubstituted polythiophene, substitution and it is unsubstituted
Polyaniline, polyester, polyacenaphthylene and novolaks；Polysilicon lining can also be used；Relative to the stacking as raceway groove through-hole side wall
Structure oxide and nitride material, when wet etching removes polysilicon, to oxide skin(coating) and nitride layer (the i.e. nitrogen in hole
Oxide stack) there is high selectivity, thus cause the loss of 1nm or smaller oxide skin(coating) and nitride layer.As shown in Figure 2 C,
Lining includes being attached to the vertical extension of the side wall of the local raceway groove through-hole structure, and positioned at the local raceway groove through hole
The diaphragm section of structural base.The technique for forming the lining can be with using plasma chemical vapor deposition (PECVD) technique, shape
Into the lining thickness be 3-10 angstroms, preferably 4-9 angstroms, more preferably 5-8 angstroms.
S4, by etching the diaphragm section for removing the lining and being located at local raceway groove through-hole structure bottom, expose not yet
Each layer of stepped construction run through by S2 first time etching procedure.As shown in Figure 2 D, after step S4, lining only retains
The vertical extension for being attached to local raceway groove through-hole structure side wall.Above-mentioned etching is located at the lining of raceway groove via bottoms
Partial technique can be dry etching or wet-etching technology, and wherein dry etch process is preferably plasma etching work
Skill, more preferably reactive plasma etching technics.Wet-etching technology can be corresponding according to the different choice of lining material
Etching liquid, such as：Azanol (HDA)；2- (2- amino ethoxies) ethanol (DGA)；Lead benzenediol (Catechol) solution.
S5, to each layer of stepped construction not run through by first time etching procedure, continue second of etching procedure, until
Through each layer of the whole of stepped construction, complete raceway groove through hole is formed.Referring to Fig. 2 E, in second of etching procedure, it is attached to
The lining itself of former local raceway groove through-hole structure side wall is thinning, protects stepped construction to be formed in first time etching procedure upper
The characteristic size (CD) of layer opening does not increase.The thinning scope of the above-mentioned substrate thickness in the through-hole structure side wall is
1-4 angstroms, it is preferably：1-3 angstroms, more preferably 1-2 angstroms.
S6, after complete raceway groove through hole is formd by S5 second of etching procedure, in through hole upper side
The lining of wall residual is removed.THAM or NH is used to the removal for remaining lining4OH is performed, THAM or NH4OH is for layer
Stack structure nitration case in itself and oxide layer all have extremely strong Etch selectivity, therefore get rid of residual lining and give raceway groove through hole
Caused characteristic size (CD), which expands, is less than 1nm.Referring to Fig. 2 F, characteristic size (CD) one above and below the raceway groove through hole ultimately formed
Cause, it is big in the absence of the characteristic size of the raceway groove through hole positioned at stepped construction upper strata opening, and positioned at each layer below stepped construction
The phenomenon that comes to a point of raceway groove through hole.
Thus it is clear that it is of the invention it is critical that protect the side wall of through hole in etching process not expand by forming lining, from
And by preventing the expansion of via openings genius loci size (CD), to ensure depth of the etching in vertical direction extension, relatively
The maximum characteristic size that may be such that passage in traditional handicraft reduces by 30%, realizes each layer of whole through stepped construction；The present invention
Method be applicable to the stepped constructions of 64 layers and more than 64 layers, such as 96 layers, 128 layers or 160 layers of stepped construction
Etching procedure, difficulty is made for avoid the increased cost of twice etching and the alignment of two layers hole.It should be noted that this reality
Applying example is illustrated to forming raceway groove through hole (channel hole, abbreviation CH), alternately, to forming gate line (Gate-
Line Slite, abbreviation GLS) identical method in the present embodiment can also be used to carry out.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (7)
- A kind of 1. semiconductor etching method, it is characterised in that this method comprises the following steps：Stepped construction is provided；First time etching procedure is carried out to stepped construction, a part of layer in stepped construction, forms local raceway groove through hole knot Structure；Lining is formed in the side wall of local raceway groove through-hole structure and the bottom of the structure；By etching the part for removing the lining and being located at local raceway groove through-hole structure bottom；Expose not yet by the first time The stepped construction that etching procedure runs through；To each layer of stepped construction not run through by first time etching procedure, continue second of etching procedure, until running through layer Each layer of whole of stack structure, forms complete raceway groove through hole；Remove the lining of the raceway groove through-hole side wall residual.
- 2. lithographic method according to claim 1, it is characterised in that total number of plies of the stepped construction is for 64 layers or big In 64 layers.
- 3. lithographic method according to claim 1, it is characterised in that the lining material is relative to as raceway groove through-hole side The stepped construction material of wall has Etch selectivity.
- 4. lithographic method according to claim 3, it is characterised in that the lining is polysilicon.
- 5. according to the lithographic method any one of claim 1-4, it is characterised in that raceway groove through-hole side wall lining is gone Except using THAM or NH4OH, the THAM or NH4OH has high selectivity for stepped construction material.
- 6. according to the lithographic method any one of claim 1-5, it is characterised in that remove the raceway groove through-hole side wall liner In give caused by raceway groove through hole characteristic size (CD) expand be less than 1nm.
- 7. the structure that a kind of lithographic method using above-mentioned any one claim is formed, including stepped construction and raceway groove Through hole, wherein raceway groove through hole run through each layer of the stepped construction, and raceway groove through hole is in the characteristic size (CD) one of each layer up and down Cause.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110808251A (en) * | 2019-11-12 | 2020-02-18 | 中国科学院微电子研究所 | Channel preparation method of three-dimensional memory |
| CN111430233A (en) * | 2020-04-02 | 2020-07-17 | 长江存储科技有限责任公司 | Etching method |
| CN111640761A (en) * | 2020-06-09 | 2020-09-08 | 长江存储科技有限责任公司 | Method for manufacturing three-dimensional memory |
| CN115207203A (en) * | 2022-09-15 | 2022-10-18 | 材料科学姑苏实验室 | Method for realizing steep side wall of laminated etching in aluminum-based superconducting circuit |
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| CN1855382A (en) * | 2005-04-06 | 2006-11-01 | 亿恒科技股份公司 | Method for etching grooves in the semiconductor substrate |
| WO2014010499A1 (en) * | 2012-07-10 | 2014-01-16 | 東京エレクトロン株式会社 | Plasma processing method, and plasma processing device |
| CN105448841A (en) * | 2014-08-28 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855382A (en) * | 2005-04-06 | 2006-11-01 | 亿恒科技股份公司 | Method for etching grooves in the semiconductor substrate |
| WO2014010499A1 (en) * | 2012-07-10 | 2014-01-16 | 東京エレクトロン株式会社 | Plasma processing method, and plasma processing device |
| CN105448841A (en) * | 2014-08-28 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110808251A (en) * | 2019-11-12 | 2020-02-18 | 中国科学院微电子研究所 | Channel preparation method of three-dimensional memory |
| CN111430233A (en) * | 2020-04-02 | 2020-07-17 | 长江存储科技有限责任公司 | Etching method |
| CN111640761A (en) * | 2020-06-09 | 2020-09-08 | 长江存储科技有限责任公司 | Method for manufacturing three-dimensional memory |
| CN115207203A (en) * | 2022-09-15 | 2022-10-18 | 材料科学姑苏实验室 | Method for realizing steep side wall of laminated etching in aluminum-based superconducting circuit |
| CN115207203B (en) * | 2022-09-15 | 2022-12-02 | 材料科学姑苏实验室 | Method for realizing steep side wall of laminated etching in aluminum-based superconducting circuit |
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Application publication date: 20180202 |