CN111640761A - Method for manufacturing three-dimensional memory - Google Patents
Method for manufacturing three-dimensional memory Download PDFInfo
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- CN111640761A CN111640761A CN202010516676.1A CN202010516676A CN111640761A CN 111640761 A CN111640761 A CN 111640761A CN 202010516676 A CN202010516676 A CN 202010516676A CN 111640761 A CN111640761 A CN 111640761A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The invention provides a manufacturing method of a three-dimensional memory, belongs to the technical field of semiconductor storage, and aims to solve the problem that a functional layer on the side wall of a channel hole is damaged when a channel structure at the bottom of the channel hole is opened. The manufacturing method comprises the following steps: providing a substrate; stacking at least two laminated structures on a substrate, and forming a channel hole penetrating through each laminated structure; forming a functional layer in the trench hole and forming a first protective layer on the inner side wall of the functional layer; etching and removing the functional layer positioned at the bottom of the channel hole to form a through hole extending to the substrate; wherein, the etching selection ratio of the functional layer to the first protective layer is more than 1. According to the manufacturing method of the three-dimensional memory, when the bottom of the functional layer is opened by taking the channel hole as the etching channel, the functional layer formed on the side wall of the channel hole can be prevented from being damaged, and the yield and the reliability of the three-dimensional memory are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a manufacturing method of a three-dimensional memory.
Background
As semiconductor memory devices have been developed, the demand for semiconductor memory devices having high-density data memory cells has been continuously increased, and thus, three-dimensional memories having a plurality of data memory cell layers vertically stacked have been a hot spot of research.
The three-dimensional memory comprises a substrate and a plurality of laminated structures stacked on the substrate, for example, two laminated structures are stacked on the substrate, an upper channel hole is formed in the laminated structure positioned at the upper part, a lower channel hole is formed in the laminated structure positioned at the lower part, the upper channel hole is communicated with the lower channel hole to form a channel hole penetrating through the two laminated structures, a functional layer and a channel layer positioned in the functional layer are formed on the inner side wall of the channel hole and the surface of the substrate positioned in the channel hole, and one end, facing the substrate, of the functional layer is required to be etched to form an opening communicated with an epitaxial region of the substrate, so that the channel layer is electrically connected with the epitaxial region of the substrate.
However, in the process of manufacturing the three-dimensional memory, a misalignment phenomenon is easily generated between the upper channel hole and the lower channel hole, so that when the bottom of the functional layer is etched and opened by using the channel hole as an etching channel, the functional layer on the sidewall of the lower channel hole is damaged, the storage function of the three-dimensional memory is further disabled, and the yield and the reliability of the three-dimensional memory are reduced.
Disclosure of Invention
The embodiment of the invention provides a manufacturing method of a three-dimensional memory, which is used for avoiding damaging a functional layer formed on the inner side wall of a channel hole when the bottom of the functional layer is opened by taking the channel hole as an etching channel, and improving the yield and the reliability of the three-dimensional memory.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
the embodiment of the invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps:
providing a substrate;
stacking at least two laminated structures on the substrate, and forming a channel hole penetrating through each laminated structure along a first direction;
forming a functional layer on the inner side wall of the channel hole and the surface of the substrate in the channel hole;
forming a first protective layer on an inner side wall of the functional layer;
etching and removing the functional layer positioned at the bottom of the channel hole to form a through hole extending to the substrate;
wherein the etching selection ratio of the functional layer to the first protective layer is greater than 1.
In the above method for manufacturing a three-dimensional memory, an etching selection ratio of the functional layer to the first protective layer is 5 to 10.
The method for manufacturing the three-dimensional memory further includes: forming sacrificial layers on the inner side wall and the bottom wall of the functional layer; and the etching selection ratio of the functional layer to the sacrificial layer is greater than 1.
In the method for manufacturing the three-dimensional memory, an etching selection ratio of the functional layer to the sacrificial layer is 5 to 10.
In the above method for manufacturing a three-dimensional memory, before the step of forming the first protection layer on the inner sidewall of the sacrificial layer, the method further includes: and forming a second protective layer at the bottom of the channel hole and on the surface of the sacrificial layer far away from the substrate.
In the method for manufacturing the three-dimensional memory, the sacrificial layer includes polysilicon, the second protective layer includes silicon oxide, and the first protective layer includes silicon nitride.
In the method for manufacturing a three-dimensional memory, the step of forming the first protection layer on the inner sidewall of the sacrificial layer includes: introducing nitrogen into the channel hole; and the nitrogen reacts with the inner side wall of the sacrificial layer to generate a silicon nitride protective film, and the silicon nitride protective film is the first protective layer.
In the method for manufacturing a three-dimensional memory, the step of forming the functional layer on the inner sidewall of the channel hole and the surface of the substrate in the channel hole includes:
forming a blocking dielectric layer on the inner side wall of the channel hole and the surface of the substrate in the channel hole;
forming charge storage layers on the inner side wall and the bottom wall of the blocking dielectric layer;
forming tunneling dielectric layers on the inner side wall and the bottom wall of the charge storage layer;
the blocking dielectric layer and the tunneling dielectric layer are both silicon oxide layers, and the charge storage layer is a silicon nitride layer.
In the above method for manufacturing a three-dimensional memory, the step of removing the functional layer at the bottom of the channel hole by etching to form a through hole extending to the substrate includes:
removing the second protective layer, the sacrificial layer and the tunneling dielectric layer which are positioned at the bottom of the channel hole; etching selection ratios of the second protection layer, the sacrificial layer, the tunneling dielectric layer and the first protection layer are all larger than 1;
removing the charge storage layer positioned at the bottom of the channel hole, wherein the etching selection ratio of the charge storage layer to the blocking dielectric layer is more than 1;
removing the blocking dielectric layer at the bottom of the channel hole to form a through hole which penetrates through the functional layer at the bottom of the channel hole and extends the substrate; and the etching selection ratio of the blocking dielectric layer to the sacrificial layer is more than 1.
In the above method for manufacturing a three-dimensional memory, an etching selection ratio of the second protection layer, the sacrificial layer, the tunneling dielectric layer and the first protection layer is 5 to 10.
In the above method for manufacturing a three-dimensional memory, an etching selection ratio of the charge storage layer to the blocking dielectric layer is 5 to 8.
In the above method for manufacturing a three-dimensional memory, an etching selection ratio of the blocking dielectric layer to the sacrificial layer is 5 to 10.
In the method for manufacturing a three-dimensional memory, the method for manufacturing a three-dimensional memory further includes: etching to remove the sacrificial layer on the inner side wall and the bottom wall of the functional layer; and forming a channel layer on the inner side wall of the functional layer, wherein the channel layer is electrically connected with the epitaxial region of the substrate.
In the method for manufacturing a three-dimensional memory as described above, the steps of forming at least two stacked structures stacked on the substrate and forming a channel hole penetrating each of the stacked structures in a first direction include:
forming a lower laminated structure on the substrate, wherein a lower channel hole penetrating through the lower laminated structure is formed in the lower laminated structure;
and forming an upper laminated structure on the surface of the lower laminated structure far away from the substrate, wherein an upper channel hole penetrating through the upper laminated structure is formed in the upper laminated structure, and the upper channel hole is communicated with the lower channel hole.
In the method for manufacturing a three-dimensional memory as described above, the step of forming the upper stacked structure on the surface of the lower stacked structure away from the substrate includes:
forming a support layer in the lower channel hole;
forming the upper laminated structure on the surface of the support layer far away from the substrate, and an upper channel hole penetrating through the upper laminated structure;
and etching the supporting layer to reform the lower channel hole, wherein the upper channel hole is communicated with the lower channel hole.
In the method for manufacturing the three-dimensional memory, the supporting layer is a polysilicon layer.
In the method for manufacturing a three-dimensional memory as described above, the step of forming the upper stacked structure on the surface of the lower stacked structure away from the substrate includes: and carrying out planarization treatment on the surface of the support layer, which is far away from the substrate, so that the surface of the support layer, which is far away from the substrate, is flush with the surface of the lower laminated structure, which is far away from the substrate.
Compared with the related art, the manufacturing method of the three-dimensional memory provided by the embodiment of the invention has the following advantages;
in the method for manufacturing the three-dimensional memory provided by the embodiment of the invention, after the functional layer is formed on the inner side wall of the trench hole, the first protective layer is further formed on the inner side wall of the functional layer, and the etching rate of the functional layer is greater than that of the first protective layer. Therefore, when the functional layer positioned at the bottom of the channel hole is etched by using the channel hole as the etching channel to form a through hole communicated with the substrate, the etching selection ratio of the functional layer to the first protective layer is greater than 1, so that the first protective layer can protect the functional layer in the etching process, the functional layer positioned on the inner side wall of the channel hole is prevented from being damaged, and the yield and the reliability of the three-dimensional memory are improved.
In addition to the technical problems solved by the embodiments of the present invention, the technical features constituting the technical solutions, and the advantages brought by the technical features of the technical solutions described above, other technical problems that can be solved by the method for manufacturing a three-dimensional memory according to the embodiments of the present invention, other technical features included in the technical solutions, and advantages brought by the technical features will be further described in detail in the detailed description.
Drawings
In order to more clearly illustrate the embodiments of the present invention or technical solutions in related arts, the drawings used in the description of the embodiments of the present invention or related arts will be briefly introduced below, it is obvious that the drawings in the following description are only a part of the embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present invention;
FIG. 3 is a schematic view of a lower stack structure and a lower channel hole according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a support layer formed in a lower trench hole according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an upper stack structure and an upper channel hole according to an embodiment of the present invention;
FIG. 6 is a schematic view of the upper channel hole and the lower channel hole communicating according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a functional layer formed in a trench hole according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a first protective layer formed on an inner sidewall of a functional layer according to an embodiment of the present invention;
FIG. 9 is a schematic view of a doped region of a substrate being connected to a channel layer formed in a functional layer according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram of a sacrificial layer formed in a functional layer according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a second protective layer formed at the bottom of the functional layer according to an embodiment of the present invention;
FIG. 12 is a schematic structural diagram of a first protection layer formed on an inner sidewall of a sacrificial layer according to an embodiment of the present invention;
fig. 13 to fig. 15 are schematic structural diagrams corresponding to stages of removing a functional layer at the bottom of a channel hole according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of the functional layer after removing the sacrificial layer on the inner sidewall of the functional layer according to the embodiment of the present invention.
Description of reference numerals:
10-a substrate; 11-an epitaxial region;
20-a laminated structure; 21-an insulating layer;
22-gate layer; 23-a transition layer;
30-channel holes; 31-lower channel holes;
32-upper channel holes; 33-a support layer;
40-a functional layer; 41-tunneling dielectric layer;
42-a charge storage layer; 43-barrier dielectric layer;
50-a channel layer; 60-a sacrificial layer;
70-a first protective layer; 80-a second protective layer;
90-a through hole; 201-lower stack structure;
202-upper laminate structure.
Detailed Description
In the related art, a three-dimensional memory includes a substrate and a stacked structure disposed on the substrate; the laminated structure comprises insulating layers, grid layers and channel holes penetrating through the laminated structure, the channel structure is formed in the channel holes, and the channel structure comprises a functional layer and a channel layer, wherein the functional layer and the channel layer are sequentially formed on the inner side wall of the channel hole, the surface of the substrate in the channel hole; in order to electrically connect one end of the channel structure close to the substrate with the epitaxial region of the substrate, the functional layer at the bottom of the channel hole needs to be opened to form a through hole communicated with the epitaxial region of the substrate. One end of the channel layer close to the substrate extends to the substrate through the through hole and is electrically connected with the epitaxial region of the substrate.
At least two laminated structures are stacked on the substrate; for example, a lower stacked structure and an upper stacked structure are stacked in this order on a substrate; the upper laminated structure is provided with an upper channel hole, the lower laminated structure is provided with a lower channel hole, the upper channel hole and the lower channel hole are communicated to form a channel hole penetrating through the two laminated structures, and the inner side wall of the channel hole and the surface of the substrate in the channel hole are provided with functional layers. However, in the process of manufacturing the three-dimensional memory, misalignment is likely to occur between the upper channel hole and the lower channel hole, so that when the bottom of the functional layer is etched and opened by using the channel hole as an etching channel, the functional layer on the inner side wall of the lower channel hole is easily damaged, the storage function of the three-dimensional memory is further failed, and the yield and the reliability of the three-dimensional memory are reduced.
In order to solve the above problems, an embodiment of the present invention provides a method for manufacturing a three-dimensional memory, in which a first protection layer is formed on an inner sidewall of a functional layer, and an etching selection ratio of the functional layer to the first protection layer is greater than 1; when the functional layer positioned at the bottom of the channel hole is etched by using the channel hole as an etching channel to form an opening communicated with the substrate, the first protective layer can protect the functional layer positioned on the inner side wall of the channel hole, and the functional layer positioned on the inner side wall of the channel hole is prevented from being damaged, so that the yield and the reliability of the three-dimensional memory are improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 1 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the invention; as shown in fig. 1, the three-dimensional memory provided by the present embodiment includes a substrate 10 and at least two stacked structures 20 disposed on the substrate 10. Wherein the substrate 10 may be made of a semiconductor material, the material of the substrate 10 includes, but is not limited to, silicon, germanium, silicon germanium, and the like, and the substrate 10 may be made of monocrystalline silicon. The substrate 10 is a plate-like structure for supporting and protecting the laminated structure 20.
The substrate 10 is stacked with at least two stacked structures 20, and the substrate 10 is stacked with two stacked structures 20: a lower laminate structure 201 and an upper laminate structure 202. Each of the stacked structures 20 includes a plurality of insulating layers 21 and a plurality of gate layers 22 alternately arranged; the thickness of the gate layer 22 and the thickness of the insulating layer 21 may be the same or different. The gate layer 22 is made of a conductive material, and the conductive material from which the gate layer 22 is made includes, but is not limited to, tungsten, copper, aluminum, doped silicon, and/or silicide. The insulating layer 21 is made of an insulating material, and the insulating material for forming the insulating layer 21 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. Of course, more than two stacked structures 20 may be stacked on the substrate 10 in sequence, and the number of the stacked gate layers 22 may be set according to the actual number.
Illustratively, the lower stacked structure 201 is formed on the substrate 10, the lower stacked structure 201 is provided with a lower channel hole 31 penetrating through the lower stacked structure 201, and one end of the lower channel hole 31 near the substrate 10 may extend to the substrate 10. The upper laminated structure 202 is formed on the surface of the lower laminated structure 201 far from the substrate 10, the upper laminated structure 202 is provided with an upper channel hole 32 penetrating through the upper laminated structure 202, and the upper channel hole 32 is communicated with the lower channel hole 31 to form a channel hole 30 penetrating through the upper laminated structure 202 and the lower laminated structure 201. As shown in fig. 6, that is, the channel hole 30 is a through hole penetrating the two laminated structures 20 and extending to the surface of the substrate 10, the channel hole 30 includes an upper channel hole 32 and a lower channel hole 31 communicating with each other.
The functional layer 40 is formed on the inner sidewall of the channel hole 30 and the surface of the substrate 10 located in the channel hole 30, i.e., a portion of the functional layer 40 is formed on the inner sidewall of the channel hole 30 and a portion of the functional layer 40 is formed on the surface of the substrate 10 located in the channel hole 30. The functional layer 40 comprises a blocking dielectric layer 43, a charge storage layer 42 and a tunneling dielectric layer 41 which are sequentially arranged; the blocking dielectric layer 43 may be in contact with the inner sidewall of the channel hole 30 and the substrate 10 located in the channel hole 30, that is, located at the outermost layer of the three-layer structure of the functional layer 40, the tunneling dielectric layer 41 is located at the innermost layer, and the charge storage layer 42 is located between the blocking dielectric layer 43 and the tunneling dielectric layer 41. The tunneling dielectric layer 41 and the blocking dielectric layer 43 are respectively made of oxide, such as silicon oxide; the charge storage layer 42 is made of a material including, but not limited to, silicon nitride, silicon oxynitride, or a combination of silicon oxide and silicon nitride, or a combination of the above materials; the tunneling dielectric layer 41, the charge storage layer 42 and the blocking dielectric layer 43 are connected to the gate layers 22 to form a plurality of memory cells.
A channel layer 50 is formed on the inner side wall and the bottom wall of the functional layer 40, the channel layer 50 can be made of doped polysilicon, and the channel layer 50 needs to be connected with the epitaxial region 11 of the substrate 10 to form a loop; therefore, the functional layer 40 at the bottom of the channel hole 30 needs to be opened to form a through hole penetrating the functional layer 40 so as to electrically connect the channel layer 50 with the epitaxial region 11 of the substrate 10.
The embodiment also provides a manufacturing method of the three-dimensional memory, and the method can be used for manufacturing the three-dimensional memory. Fig. 2 is a flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention, and fig. 3 to 16 are schematic structural diagrams corresponding to different stages in a process of the method for manufacturing a three-dimensional memory according to an embodiment of the present invention.
As shown in fig. 2, the method for manufacturing a three-dimensional memory according to an embodiment of the present invention includes the following steps:
step S100, a substrate 10 is provided, for example, the substrate 10 may be made of monocrystalline silicon, and is used for protecting and supporting the subsequently formed stacked structure 20.
Step S200, forming at least two stacked structures 20 on the substrate 10 in a stacked manner, and forming a trench hole 30 penetrating the two stacked structures 20 along a first direction. Illustratively, a lower stacked structure 201 and an upper stacked structure 202 located on the lower stacked structure 201 are sequentially stacked on the substrate 10, and the lower stacked structure 201 is etched along a first direction to form a lower channel hole 31; the upper laminated structure 202 is formed on the surface of the lower laminated structure 201 far away from the substrate 10, the upper laminated structure 202 is etched along the first direction to form an upper channel hole 32, and the upper channel hole 32 is communicated with the lower channel hole 31 to form a channel hole 30 which penetrates through the upper laminated structure 202 and the lower laminated structure 201 and extends to the substrate 10. It is to be understood that the first direction is a direction perpendicular or approximately perpendicular to the substrate 10, as will be described below.
There are various specific ways to form the stacked structure 20 on the substrate 10, and in an alternative embodiment, the step S200 includes:
a lower stack 201 is formed on the substrate 10, and the structure resulting from this step is shown in fig. 3. Illustratively, a plurality of transition layers 23 and a plurality of insulating layers 21 are alternately deposited on the substrate 10, and the lower stacked structure 201 is a structure formed by alternately stacking the transition layers 23 and the insulating layers 21; the material for forming the insulating layer 21 includes, but is not limited to, silicon oxide, and the material for forming the transition layer 23 includes, but is not limited to, silicon nitride. The transition layer 23 and the insulating layer 21 may be formed by a Chemical Vapor Deposition (CVD), an Atomic Layer Deposition (ALD), or other suitable deposition method, and the transition layer 23 and the insulating layer 21 are sequentially deposited on the substrate 10. It is understood that the layered structures at the bottom and top of the lower stacked structure 201 are both the insulating layer 21.
After forming the lower stacked structure 201 on the substrate 10, a lower channel hole 31 penetrating the lower stacked structure 201 and extending to the substrate 10 is formed in the lower stacked structure 201, and the structure formed in this step is shown in fig. 3. Illustratively, the lower stacked structure 201 formed by the plurality of transition layers 23 and the plurality of insulating layers 21 may be etched in a direction perpendicular to the substrate 10 to form the lower channel hole 31, and the lower channel hole 31 penetrates through the lower stacked structure 201. For example, the lower stacked structure 201 may be etched using dry etching, stopping after etching to the surface of the substrate 10, to form the lower channel hole 31 penetrating to the substrate 10.
After forming the lower channel hole 31 in the lower stacked structure 201, an upper stacked structure 202 is formed on the lower stacked structure 201, and the structure formed in this step is as shown in fig. 5. The upper stacked structure 202 is formed in the same manner as the lower stacked structure 201, and is not described in detail here. In addition, the layered structures located at the bottom and top of the upper stacked structure 202 are both insulating layers 21.
After the upper stacked structure 202 is formed on the lower stacked structure 201, an upper channel hole 32 penetrating the upper stacked structure 202 is formed in the upper stacked structure 202, the upper channel hole 32 communicates with the lower channel hole 31 to form a channel hole 30 penetrating the upper stacked structure 202 and the lower stacked structure 201, and one end of the channel hole 30 near the substrate 10 extends to the substrate 10, and this step forms a structure as shown in fig. 5 and 6.
Illustratively, after the predetermined etching position of the upper stacked structure 202 is aligned with the lower channel hole 31 of the lower stacked structure 201, the upper stacked structure 202 is etched in a first direction, for example, by dry etching, to form an upper channel hole 32 penetrating through the upper stacked structure 202; the lower end of the upper channel hole 32 communicates with the upper end of the lower channel hole 31.
In some embodiments, before the step of forming the upper stacked structure 202 on the lower stacked structure 201, the following steps are generally further included:
forming a support layer 33 within the lower channel hole 31, as shown in fig. 4; a support layer 33 is formed within the lower channel hole 31, and in particular, the channel hole 30 is filled with a sacrificial material, including but not limited to polysilicon, to form the support layer 33. With such a design, the support effect of the support layer 33 can prevent the lower stacked structure 201 from being deformed when the upper stacked structure 202 is formed on the lower stacked structure 201, thereby improving the stability of the three-dimensional memory in which the stacked structures 20 are sequentially stacked.
As shown in fig. 5 and 6, after the support layer 33 is formed, an upper stacked structure 202 is formed on a surface of the lower stacked structure 201 away from the substrate 10 and a surface of the support layer 33 away from the substrate 10. After the upper stacked structure 202 forms the upper channel hole 32 penetrating through it, the support layer 33 located in the lower channel hole 31 is etched and removed to reform the lower channel hole 31, thereby realizing communication between the upper channel hole 32 and the lower channel hole 31.
Further, after the lower trench hole 31 is filled with polysilicon to form the support layer 33, in order to ensure that the surface of the support layer 33 away from the substrate 10 and the surface of the lower stacked structure 201 away from the substrate 10 are located on the same horizontal plane, that is, the upper surface of the support layer 33 and the upper surface of the lower stacked structure 201 are kept flush, the support layer 33 may be subjected to a planarization process. For example, the upper surface of the support layer 33 may be subjected to Chemical Mechanical Polishing (CMP) to make the lower surface of the upper stacked structure 202 and the upper surface of the support layer 33 flush, thereby improving the stability of the upper stacked structure 202 formed on the lower stacked structure 201 and reducing the possibility of tilting or collapsing of each stacked structure 20.
After forming the channel hole 30 penetrating the upper laminated structure 202 and the lower laminated structure 201 by communicating the upper channel hole 32 with the lower channel hole 31, step S300 is performed: forming a functional layer 40 on an inner sidewall of the channel hole 30 and on a surface of the substrate 10 within the channel hole 30; alternatively, the functional layer 40 is formed on the inner sidewall of the channel hole 30 and the surface of the substrate 10 exposed in the channel hole 30.
Illustratively, as shown in fig. 7, the functional layer 40 formed within the channel hole 30 includes, but is not limited to, a blocking dielectric layer 43 layer, a charge storage layer 42, and a tunneling dielectric layer 41; the blocking dielectric layer 43 is in contact with the inner sidewall of the channel hole 30 and the substrate 10 located in the channel hole 30, that is, located at the outermost layer of the three-layer structure of the functional layer 40, the tunneling dielectric layer 41 is located at the innermost layer, and the charge storage layer 42 is located between the blocking dielectric layer 43 and the tunneling dielectric layer 41.
The tunneling dielectric layer 41 may be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The charge storage layer 42 is used for storing charge, and the material of the charge storage layer 42 includes, but is not limited to, silicon nitride, silicon oxynitride, or a combination of silicon oxide and silicon nitride, or a combination of the above materials. The blocking dielectric layer 43 may be an insulating material layer, for example, the material of the blocking dielectric layer 43 may be silicon oxide or silicon nitride. It is understood that the functional layer 40 may be formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), among other suitable methods.
After the functional layer 40 is formed on the inner sidewall of the channel hole 30 and the surface of the substrate 10 in the channel hole 30, the first protective layer 70 is formed on the inner sidewall of the functional layer 40, and the structure formed by this step is as shown in fig. 8.
Illustratively, the first protective layer 70 is formed on the inner sidewall of the functional layer 40, and the material of the first protective layer 70 includes, but is not limited to, silicon nitride; under the same etching condition, the etching rate of the functional layer 40 is greater than that of the first protective layer 70, that is, the etching selection ratio of the functional layer 40 to the first protective layer 70 is greater than 1; when the functional layer 40 at the bottom of the channel hole 30 is opened by using the channel hole 30 as an etching channel in the subsequent steps, the functional layer 40 on the inner side wall of the channel hole 30 can be protected, so that the functional layer 40 on the inner side wall of the channel hole 30 is prevented from being damaged, and the yield and the reliability of the three-dimensional memory are improved. In this embodiment, under the same etching condition, the etching selection ratio of the functional layer 40 to the first protective layer 70 is 5 to 10, preferably, the etching selection ratio of the functional layer 40 to the first protective layer 70 is set to 10, and the larger the ratio of the etching selection ratio of the functional layer 40 to the first protective layer 70 is, the better the protection effect of the first protective layer 70 on the functional layer 40 located on the inner sidewall of the channel hole 30 is, so that setting the ratio of the etching selection ratio of the functional layer 40 to the first protective layer 70 to 10 can improve the protection effect of the first protective layer 70 on the functional layer 40 located on the inner sidewall of the channel hole 30.
After the first protective layer 70 is formed on the inner sidewall of the functional layer 40, step S500 is performed: the functional layer 40 at the bottom of the channel hole 30 is etched to form a through hole with the substrate 10. Illustratively, the channel hole 30 is used as an etching channel, and the functional layer 40 at the bottom of the channel hole 30 is etched by dry etching, and the functional layer 40 at the bottom of the channel hole 30 is removed to form a through hole, which is communicated with the epitaxial region 11 of the substrate 10.
After the functional layer 40 located at the bottom of the channel hole 30 forms a through hole communicating with the substrate 10, step S600 is performed: forming a channel layer 50 on the functional layer 40, wherein the channel layer 50 is electrically connected with the epitaxial region 11 of the substrate 10; the structure formed in this step is shown in fig. 9.
Illustratively, the channel layer 50 may be formed on the inner sidewall of the functional layer 40 by deposition, and the material of the channel layer 50 includes, but is not limited to, polysilicon. One end of the channel layer 50 near the substrate 10 is electrically connected to the epitaxial region 11 of the substrate 10 through the via hole. Further, one end of the channel layer 50 close to the substrate 10 may fill the entire through hole, so as to increase a contact area between the channel layer 50 and the epitaxial region 11, and improve reliability of electrical connection between the channel layer 50 and the epitaxial region 11 of the substrate 10. In addition, before the channel layer 50 electrically connected to the epitaxial region 11 of the substrate 10 is formed on the inner sidewall of the functional layer 40, the first protective layer 70 on the inner sidewall of the functional layer 40 needs to be removed, and then the channel layer 50 needs to be deposited and formed on the inner sidewall of the functional layer 40.
In the method for manufacturing the three-dimensional memory provided in this embodiment, the first protection layer 70 is formed on the inner sidewall of the functional layer 40, and the etching selection ratio of the functional layer 40 to the first protection layer 70 is greater than 1; therefore, when the functional layer 40 located at the bottom of the channel hole 30 is etched using the channel hole 30 as an etching channel to form a through hole communicating with the substrate 10, since the etching selection ratio of the functional layer 40 to the first protective layer 70 is greater than 1 under the same etching condition; therefore, the first protective layer 70 can protect the functional layer 40 during the etching process, and the functional layer 40 on the inner sidewall of the channel hole 30 is prevented from being damaged, thereby improving the yield and reliability of the three-dimensional memory.
In the above embodiment, the first protection layer 70 is formed on the inner sidewall of the functional layer 40, and there are various methods for forming the first protection layer 70, in an optional embodiment, the step S400 includes:
after the functional layer 40 is formed on the inner side walls of the channel hole 30 and on the surface of the substrate 10 located in the channel hole 30, a sacrificial layer 60 is formed on the inner side walls and the bottom wall of the functional layer 40, and the structure formed by this step is as shown in fig. 10. The material of the sacrificial layer 60 is not limited to polysilicon, but in the present embodiment, the sacrificial layer 60 is made of polysilicon, and specifically, the sacrificial layer 60 may be formed by depositing polysilicon on the inner sidewall and the bottom wall of the functional layer 40.
In this embodiment, under the same etching condition, the etching rate of the functional layer 40 is greater than that of the sacrificial layer 60, that is, the etching selection ratio of the functional layer 40 to the sacrificial layer 60 is greater than 1, so that when the functional layer 40 located at the bottom of the channel hole 30 is opened, the sacrificial layer 60 can provide protection for the functional layer 40 located on the inner sidewall of the channel hole 30. In addition, the ratio of the etching selectivity of the functional layer 40 to the sacrificial layer 60 may be 5 to 10 under the same etching condition. Preferably, the etching selection ratio of the functional layer 40 to the sacrificial layer 60 is set to 10, and the etching rate of the functional layer 40 is much greater than that of the sacrificial layer 60, so as to improve the protection effect of the sacrificial layer 60 on the functional layer 40 located on the inner sidewall of the channel hole 30.
In another alternative embodiment, step S400 includes:
after forming the sacrificial layer 60 on the inner sidewall and the bottom wall of the functional layer 40, a second protective layer 80 is formed on the bottom of the sacrificial layer 60, and the structure formed in this step is as shown in fig. 11. Illustratively, first, a transition protection layer may be formed on the inner sidewall and the bottom wall of the sacrificial layer 60 by deposition; then, the transition protection layer on the inner sidewall of the sacrificial layer 60 is removed, and the transition protection layer at the bottom of the sacrificial layer 60 is remained to form the second protection layer 80. The material of the second protection layer 80 includes, but is not limited to, silicon oxide; of course, the method of forming the second protection layer 80 on the bottom of the sacrificial layer 60 is not limited to the method described in this step, and other processing methods may be used.
After forming the second protection layer 80 on the bottom of the sacrificial layer 60, nitrogen may be introduced into the trench hole 30, and the nitrogen reacts with the surface of the sacrificial layer 60 to form the first protection layer 70, and the structure formed in this step is as shown in fig. 12.
Illustratively, the sacrificial layer 60 may be made of polysilicon, and a silicon oxide layer is formed on the bottom of the sacrificial layer 60 and the surface far away from the substrate 10; after nitrogen is introduced into the channel hole 30 in a high-temperature environment, the nitrogen reacts with the polysilicon on the inner side wall of the sacrificial layer 60 to generate a silicon nitride protective film, and the second protective layer 80 at the bottom of the sacrificial layer 60 does not react with the nitrogen, namely the second protective layer 80 is equivalent to a passivation layer; and the first protective layer 70 is formed only on the inner sidewalls of the sacrificial layer 60. Of course, the method of forming the first protective layer 70 on the inner sidewall of the sacrificial layer 60 is not limited to the method described in this step, and other processes may be used.
After the above steps, the functional layer 40, the sacrificial layer 60 and the first protective layer 70 are sequentially formed on the inner sidewall of the trench hole 30; wherein the functional layer 40 is in contact with the inner sidewall of the trench hole 30, and the sacrificial layer 60 is located between the functional layer 40 and the first protective layer 70. A second protective layer 80, a sacrificial layer 60 and a functional layer 40 are formed at the bottom of the trench hole 30, wherein the functional layer 40 is closest to the substrate 10 or in contact with the substrate 10, and the sacrificial layer 60 is located between the second protective layer 80 and the functional layer 40.
On the basis of the above embodiment, after the first protective layer 70 is formed on the inner sidewall of the sacrificial layer 60, the functional layer 40 located at the bottom of the channel hole 30 may be etched to form a through hole communicating with the substrate 10. Specifically, the functional layer 40 located at the bottom of the channel hole 30 is etched by using the channel hole 30 as an etching channel, different etching conditions may be selected according to different manufacturing materials of each of the sacrificial layer 60, the first protective layer 70, the second protective layer 80, and the functional layer 40 located at the bottom of the channel hole 30, the sacrificial layer 60 located on the surface of the functional layer 40, and the second protective layer 80 are etched in batches, for example, in three times.
Specifically, the second protection layer 80, the sacrificial layer 60 and the tunneling dielectric layer 41 at the bottom of the channel hole 30 can be removed by the first etching; the structure formed in this step is shown in fig. 13. The second protection layer 80 and the tunneling dielectric layer 41 are both silicon oxide layers, the sacrificial layer 60 is a polysilicon layer, and the first protection layer 70 is a silicon nitride protection film; under the same etching condition, the etching rates of the second protection layer 80, the sacrificial layer 60 and the tunneling dielectric layer 41 are all greater than the etching rate of the first protection layer 70, that is, the etching selection ratios of the second protection layer 80, the sacrificial layer 60, the tunneling dielectric layer 41 and the first protection layer 70 are all greater than 1; in the etching process, the etching rate of the silicon oxide and the polysilicon is greater than that of the silicon nitride, so as to remove the second protection layer 80, the sacrificial layer 60 and the tunneling dielectric layer 41 at the bottom of the channel hole 30. It is understood that, in the etching process, the ratio of the etching selectivity of the silicon oxide and the polysilicon to the silicon nitride can be set to 5 to 10, i.e., the ratio of the etching selectivity of the second protection layer 80, the sacrificial layer 60, and the tunneling dielectric layer 41 to the first protection layer 70 can be set to 5 to 10.
The second etching removes the charge storage layer 42 at the bottom of the channel hole 30; the structure formed in this step is shown in fig. 14. Wherein, the charge storage layer 42 is made of silicon nitride material, and the blocking dielectric layer 43 is made of silicon oxide material; under the same etching condition, the etching rate of the charge storage layer 42 is greater than that of the blocking dielectric layer 43, that is, the etching selection ratio of the charge storage layer 42 to the blocking dielectric layer 43 is greater than 1. In this etching process, the etching selectivity ratio of silicon nitride to silicon oxide is set to be greater than 1 for removing the charge storage layer 42 and protecting the sacrificial layer 60 on the inner sidewall of the channel hole 30. In addition, the ratio of the etching selectivity of the charge storage layer 42 to the blocking dielectric layer 43 in this embodiment may be set to 5 to 8. Further, the first protection layer 70 is a silicon nitride layer, which is made of the same material as the charge storage layer 42, and the first protection layer 70 can be removed together during the process of removing the charge storage layer 42, so as to save the process.
The third etch removes the blocking dielectric layer 43 at the bottom of the channel hole 30 to form a via 90 through the functional layer 40 at the bottom of the channel hole 30, which results in the structure shown in fig. 15. For example, the sacrificial layer 60 is made of polysilicon, and the blocking dielectric layer 43 is made of silicon oxide; under the same etching condition, the etching rate of the silicon oxide is greater than that of the polysilicon, that is, the etching selection ratio of the blocking dielectric layer 43 to the sacrificial layer 60 is greater than 1, so as to remove the blocking dielectric layer 43 at the bottom of the channel hole 30 and form a through hole 90 penetrating through the substrate 10. In addition, during the etching process, the etching selectivity ratio of the blocking dielectric layer 43 to the sacrificial layer 60 can be set to 5 to 10.
Removing the blocking dielectric layer 43 at the bottom of the channel hole 30 to form a through hole 90 penetrating the functional layer 40 at the bottom of the channel hole 30, and then forming a channel layer 50 on the inner sidewall of the functional layer 40, wherein the channel layer 50 is electrically connected to the epitaxial region 11 of the substrate 10; the structure formed in this step is shown in fig. 1. Illustratively, after removing the barrier dielectric layer 43 located at the bottom of the channel hole 30, the sacrificial layer 60 still remains on the inner sidewall of the functional layer 40, and therefore, the sacrificial layer 60 needs to be removed before forming the channel layer 50 in the channel hole 30, and the structure after removing the sacrificial layer 60 on the inner sidewall of the channel layer 50 is shown in fig. 16.
After the sacrificial layer 60 is removed, as shown in fig. 1, polysilicon is deposited in the channel hole 30 to form a channel layer 50, and one end of the channel layer 50 close to the substrate 10 is electrically connected to the epitaxial region 11 of the substrate 10 through the through hole 90. It will be appreciated that the channel layer 50 may fill the entire via 90 to enhance the reliability of the electrical connection of the channel layer 50 to the epitaxial region 11 of the substrate 10.
On the basis of the above embodiment, after forming the channel layer 50 electrically connected to the epitaxial region 11 of the substrate 10 in the channel hole 30, step S700 is performed: the transition layer 23 in each stack 20 is replaced with a gate layer 22.
Illustratively, a gate slit penetrating each stacked structure 20 is formed on each stacked structure 20, and an end of the gate slit near the substrate 10 may extend to the substrate 10. For example, a photoresist mask may be formed on the surface of the stacked structure 20, then the stacked structure 20 may be etched using dry etching, and by controlling the etching time such that the etching is stopped near the upper surface of the substrate 10 to form a gate slit extending to the substrate 10, finally the photoresist mask is removed by dissolving or ashing in a solvent. The dry etching may include ion milling etching, plasma etching, reactive ion etching, laser ablation, and the like.
After forming the gate slit in the stacked structure 20, replacing the transition layer 23 with the gate slit; for example, with the gate gap as an etchant channel, the transition layer 23 in the stacked-layer structure 20 is removed by the etchant to form a cavity between each adjacent two insulating layers 21; then, the gate gap is used as a deposition channel, and the conductive material is filled in each cavity by adopting an atomic layer deposition method to form each gate layer 22.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (17)
1. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
providing a substrate;
stacking at least two laminated structures on the substrate, and forming a channel hole penetrating through each laminated structure along a first direction;
forming a functional layer on the inner side wall of the channel hole and the surface of the substrate in the channel hole;
forming a first protective layer on an inner side wall of the functional layer;
etching and removing the functional layer positioned at the bottom of the channel hole to form a through hole extending to the substrate;
wherein the etching selection ratio of the functional layer to the first protective layer is greater than 1.
2. The method of claim 1, wherein an etching selectivity ratio of the functional layer to the first protective layer is 5 to 10.
3. The method of claim 1, further comprising:
and forming sacrificial layers on the inner side wall and the bottom wall of the functional layer, wherein the etching selection ratio of the functional layer to the sacrificial layers is greater than 1.
4. The method of claim 3, wherein an etching selectivity ratio of the functional layer to the sacrificial layer is 5 to 10.
5. The method for fabricating the three-dimensional memory according to claim 3, further comprising, before the step of forming the first protection layer on the inner sidewall of the sacrificial layer:
and forming a second protective layer at the bottom of the channel hole and on the surface of the sacrificial layer far away from the substrate.
6. The method of claim 5, wherein the sacrificial layer comprises polysilicon, the second protective layer comprises silicon oxide, and the first protective layer comprises silicon nitride.
7. The method of claim 6, wherein the step of forming the first protection layer on the inner sidewall of the sacrificial layer comprises:
introducing nitrogen into the channel hole;
and the nitrogen reacts with the inner side wall of the sacrificial layer to generate a silicon nitride protective film, and the silicon nitride protective film is the first protective layer.
8. The method of claim 6, wherein the step of forming a functional layer on the inner sidewall of the channel hole and the surface of the substrate in the channel hole comprises:
forming a blocking dielectric layer on the inner side wall of the channel hole and the surface of the substrate in the channel hole;
forming charge storage layers on the inner side wall and the bottom wall of the blocking dielectric layer;
forming tunneling dielectric layers on the inner side wall and the bottom wall of the charge storage layer;
the blocking dielectric layer and the tunneling dielectric layer are both silicon oxide layers, and the charge storage layer is a silicon nitride layer.
9. The method of claim 8, wherein the step of etching away the functional layer at the bottom of the channel hole to form a via extending to the substrate comprises:
removing the second protective layer, the sacrificial layer and the tunneling dielectric layer which are positioned at the bottom of the channel hole; etching selection ratios of the second protection layer, the sacrificial layer, the tunneling dielectric layer and the first protection layer are all larger than 1;
removing the charge storage layer positioned at the bottom of the channel hole, wherein the etching selection ratio of the charge storage layer to the blocking dielectric layer is more than 1;
removing the blocking dielectric layer at the bottom of the channel hole to form a through hole which penetrates through the functional layer at the bottom of the channel hole and extends the substrate; and the etching selection ratio of the blocking dielectric layer to the sacrificial layer is more than 1.
10. The method for manufacturing the three-dimensional memory according to claim 9, wherein an etching selection ratio of the second protection layer, the sacrificial layer, and the tunneling dielectric layer to the first protection layer is 5 to 10.
11. The method of claim 9, wherein the three-dimensional memory is formed by a three-dimensional memory,
and the etching selection ratio of the charge storage layer to the blocking dielectric layer is 5-8.
12. The method of claim 9, wherein the three-dimensional memory is formed by a three-dimensional memory,
and the etching selection ratio of the barrier dielectric layer to the sacrificial layer is 5-10.
13. The method for fabricating a three-dimensional memory according to any one of claims 3 to 9, further comprising:
etching to remove the sacrificial layer on the inner side wall and the bottom wall of the functional layer;
and forming a channel layer on the inner side wall of the functional layer, wherein the channel layer is electrically connected with the epitaxial region of the substrate.
14. The method of claim 1, wherein the step of forming at least two stacked structures stacked on the substrate and forming a channel hole extending through each of the stacked structures in a first direction comprises:
forming a lower laminated structure on the substrate, wherein a lower channel hole penetrating through the lower laminated structure is formed in the lower laminated structure;
and forming an upper laminated structure on the surface of the lower laminated structure far away from the substrate, wherein an upper channel hole penetrating through the upper laminated structure is formed in the upper laminated structure, and the upper channel hole is communicated with the lower channel hole.
15. The method of claim 14, wherein the step of forming the upper stack structure on the surface of the lower stack structure away from the substrate comprises:
forming a support layer in the lower channel hole;
forming the upper laminated structure on the surface of the support layer far away from the substrate, and an upper channel hole penetrating through the upper laminated structure;
and etching the supporting layer to reform the lower channel hole, wherein the upper channel hole is communicated with the lower channel hole.
16. The method of claim 15, wherein the support layer is a polysilicon layer.
17. The method of claim 15, wherein the step of forming the upper stack structure on the surface of the lower stack structure away from the substrate comprises:
and carrying out planarization treatment on the surface of the support layer, which is far away from the substrate, so that the surface of the support layer, which is far away from the substrate, is flush with the surface of the lower laminated structure, which is far away from the substrate.
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